SAFC166中文资料
Microcontrollers
C166Family
16-Bit Single-Chip Microcontroller
C161PI User’s Manual 1999-08V 1.0w w w .i n f i n e o n .c o
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Edition 1999-08Published by Infineon Technologies AG,St.-Martin-Strasse 53D-81541 München ? Infineon Technologies AG 1999.All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be con-sidered as warranted characteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties,including but not limited to warranties of non-infringement, regarding circuits, de-scriptions and charts stated herein.Infineon Technologies is an approved CECC https://www.wendangku.net/doc/651419261.html,rmation For further information on technology, de-livery terms and conditions and prices please contact your nearest Infineon Tech-nologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).Warnings Due to technical requirements components may contain dangerous substances. For in-formation on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or sys-tems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support de-vice or system, or to affect the safety or ef-fectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to sup-port and/or maintain and sustain and/or protect human life. If they fail, it is reason-able to assume that the health of the user or other persons may be endangered.
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Microcontrollers
C166Family
16-Bit Single-Chip Microcontroller C161PI
V 1.0, 1999-08
User’s Manual
C161PI
Revision History:1999-08 (V 1.0)
Previous Versions:User’s Manual C161RI, 05.98 (V 1.0)
Page Subjects (major changes since last revision)
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The C161PI is the successor of the C161RI. Therefore this manual also replaces the C161RI manual.
C161PI
Table of Contents Page 1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 1.1The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . .1-2 1.2Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 1.3Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
2Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 2.1Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . .2-2 2.1.1High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . .2-3 2.1.2Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . .2-7 2.2The On-chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8 2.3The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11 2.4Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18 2.5Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20 3Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 3.1Internal ROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.2Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 3.3The On-Chip XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9 3.4External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11 3.5Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12 4The Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 4.1Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4 4.2Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7 4.3Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11 4.4Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-12 4.5CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13 5Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 5.1Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 5.1.1Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5 5.2Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11 5.3Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . .5-15 5.4Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . .5-17 5.5Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18 5.6PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21 5.7Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.8External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24 5.9Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 6Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 6.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2 6.2Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4 6.3Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8 User’s Manual -11999-08
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6.4Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
7Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 7.1Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2 7.2Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 7.3Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7 7.4PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9 7.5PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-13 7.6Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16 7.7Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19 7.8Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24 7.9Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27 7.10Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30
8Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
9The External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 9.1Single Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2 9.2External Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3 9.3Programmable Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12 9.4READY Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-17 9.5Controlling the External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . .9-19 9.6EBC Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-27 9.7The XBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-28 10The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 10.1Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 10.1.1GPT1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3 10.1.2GPT1 Auxiliary Timers T2 and T4 . . . . . . . . . . . . . . . . . . . . . . . . . .10-13 10.1.3Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . .10-22 10.2Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-23 10.2.1GPT2 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-25 10.2.2GPT2 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28 10.2.3Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . . . .10-36 11The Asynchronous/Synchronous Serial Interface . . . . . . . . . . . . . .11-1 11.1Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-5 11.2Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-8 11.3Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . . . .11-10 11.4ASC0 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-11 11.5ASC0 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-15 12The High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . .12-1 12.1Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-7 12.2Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-10
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12.3Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-11 12.4Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-12 12.5Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-13 12.6Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-14 12.7SSC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-16
13The Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 13.1Operation of the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-3 13.2Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-6 14The Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1
15The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
16The Analog / Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1 16.1Mode Selection and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-2 16.2Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-11 16.3A/D Converter Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-13 17The I2C Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 17.1I2C Bus Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2 17.2The Physical I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-4 17.3Operating the I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-6 17.3.1Operation in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-6 17.3.2Operation in Multimaster Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-7 17.3.3Operation in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-7 17.4I2C Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-12 17.5Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-14 18System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1 18.1Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2 18.2Status After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-5 18.3Application-Specific Initialization Routine . . . . . . . . . . . . . . . . . . . . . . . .18-9 18.4System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-12 18.4.1System Startup Configuration upon an External Reset . . . . . . . . . .18-13 18.4.2System Startup Configuration upon a Single-Chip Mode Reset . . .18-20 19Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 19.1Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3 19.2Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-5 19.3Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-7 19.3.1Status of Output Pins during Power Reduction Modes . . . . . . . . . . . .19-8 19.4Slow Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-10 19.5Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-14 19.6Programmable Frequency Output Signal . . . . . . . . . . . . . . . . . . . . . .19-16
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19.7Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-20
20System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 20.1Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-4 20.2Register Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-9 20.3Procedure Call Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-9 20.4Table Searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-12 20.5Floating Point Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-12 20.6Peripheral Control and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-13 20.7Trap/Interrupt Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-13 20.8Unseparable Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . .20-14 20.9Overriding the DPP Addressing Mechanism . . . . . . . . . . . . . . . . . . . .20-14 20.10Handling the Internal Code Memory . . . . . . . . . . . . . . . . . . . . . . . . . .20-16 20.11Pits, Traps and Mines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-18
21The Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1 21.1Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1 21.2CPU General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . .21-2 21.3Special Function Registers ordered by Name . . . . . . . . . . . . . . . . . . . .21-4 21.4Registers ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-9 21.5Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-14
22Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1
23Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-1
24Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1
1Introduction
The rapidly growing area of embedded control applications is representing one of the most time-critical operating environments for today’s microcontrollers. Complex control algorithms have to be processed based on a large number of digital as well as analog input signals, and the appropriate output signals must be generated within a defined maximum response time. Embedded control applications also are often sensitive to board space, power consumption, and overall system cost.
Embedded control applications therefore require microcontrollers, which...
?offer a high level of system integration
?eliminate the need for additional peripheral devices and the associated software overhead ?provide system security and fail-safe mechanisms
?provide effective means to control (and reduce) the device’s power consumption. With the increasing complexity of embedded control applications, a significant increase in CPU performance and peripheral functionality over conventional 8-bit controllers is required from microcontrollers for high-end embedded control systems. In order to achieve this high performance goal Infineon has decided to develop its family of 16-bit CMOS microcontrollers without the constraints of backward compatibility.
Of course the architecture of the 16-bit microcontroller family pursues successfull hardware and software concepts, which have been established in Infineons popular 8-bit controller families.
About this Manual
This manual describes the functionality of the 16-bit microcontroller C161PI of the Infineon C166Family.
The descriptions in this manual refer to the following derivatives:
?C161PI-LM
?C161PI-LF
This manual is valid for the mentioned derivatives. Of course it refers to all devices of the different available temperature ranges and packages.
For simplicity all these various versions are referred to by the term C161PI throughout this manual. The complete pro-electron conforming designations are listed in the respective data sheets.
1.1The Members of the 16-bit Microcontroller Family
The microcontrollers of the Infineon 16-bit family have been designed to meet the high performance requirements of real-time embedded control applications. The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli (interrupts). Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent. This also minimizes the need for communication via the external bus interface. The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive, industrial control, or data communications.
The core of the 16-bit family has been developped with a modular family concept in mind. All family members execute an efficient control-optimized instruction set (additional instructions for members of the second generation). This allows an easy and quick implementation of new family members with different internal memory sizes and technologies, different sets of on-chip peripherals and/or different numbers of IO pins. The XBUS concept opens a straight forward path for the integration of application specific peripheral modules in addition to the standard on-chip peripherals in order to build application specific derivatives.
As programs for embedded control applications become larger,high level languages are favoured by programmers, because high level language programs are easier to write, to debug and to maintain.
The 80C166-type microcontrollers were the first generation of the 16-bit controller family. These devices have established the C166 architecture.
The C165-type and C167-type devices are members of the second generation of this family. This second generation is even more powerful due to additional instructions for HLL support, an increased address space, increased internal RAM and highly efficient management of various resources on the external bus.
Enhanced derivatives of this second generation provide additional features like additional internal high-speed RAM, an integrated CAN-Module, an on-chip PLL, etc. Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance, while minimizing the part count. These efforts are supported by the so-called XBUS, defined for the Infineon 16-bit microcontrollers (second generation). This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required interface. One representative taking advantage of this technology is the integrated CAN module.
The C165-type devices are reduced versions of the C167 which provide a smaller package and reduced power consumption at the expense of the A/D converter, the CAPCOM units and the PWM module.
The C164-type devices and some of the C161-type devices are further enhanced by a flexible power management and form the third generation of the 16-bit controller family. This power management mechanism provides effective means to control the power that is consumed in a certain state of the controller and thus allows the minimization of the overall power consumption with respect to a given application.
A variety of different versions is provided which offer various kinds of on-chip program memory:
?mask-programmable ROM
?Flash memory
?OTP memory
?ROMless with no non-volatile memory at all.
Also there are devices with specific functional units.
The devices may be offered in different packages, temperature ranges and speed classes.
More standard and application-specific derivatives are planned and in development. Note:Not all derivatives will be offered in any temperature range, speed class, package or program memory variation.
Information about specific versions and derivatives will be made available with the devices themselves. Contact your Infineon representative for up-to-date material. Note:As the architecture and the basic features (i.e. CPU core and built in peripherals) are identical for most of the currently offered versions of the C161PI, the descriptions within this manual that refer to the “C161PI” also apply to the other variations, unless otherwise noted.
1.2Summary of Basic Features
The C161PI is an improved representative of the Infineon family of full featured 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and means for power reduction.
Several key features contribute to the high performance of the C161PI (the indicated timings refer to a CPU clock of 25MHz).
High Performance 16-Bit CPU With Four-Stage Pipeline
?80 ns minimum instruction cycle time, with most instructions executed in 1 cycle ?400 ns multiplication (16-bit *16-bit), 800 ns division (32-bit/16-bit)
?Multiple high bandwidth internal data buses
?Register based design with multiple variable register banks
?Single cycle context switching support
?16 MBytes linear address space for code and data (von Neumann architecture)?System stack cache support with automatic stack overflow/underflow detection Control Oriented Instruction Set with High Efficiency
?Bit, byte, and word data types
?Flexible and efficient addressing modes for high code density
?Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags
?Hardware traps to identify exception conditions during runtime
?HLL support for semaphore operations and efficient data access
Power Management Features
?Programmable system slowdown (slowdown divider SDD)
?Flexible peripheral management (individual disabling)
?Sleepmode including wakeup via external interrupts
?Programmable frequency output
Integrated On-chip Memory
? 1 KByte internal RAM for variables, register banks, system stack and code
? 2 KByte on-chip high-speed XRAM for variables, user stack and code
External Bus Interface
?Multiplexed or demultiplexed bus configurations
?Segmentation capability and chip select signal generation
?8-bit or 16-bit data bus
?Bus cycle characteristics selectable for five programmable address areas
16-Priority-Level Interrupt System
?27 interrupt nodes with separate interrupt vectors
?240/400 ns typical/maximum interrupt latency in case of internal program execution ?Fast external interrupts
8-Channel Peripheral Event Controller (PEC)
?Interrupt driven single cycle data transfer
?Transfer count option (std. CPU interrupt after programmable number of PEC transfers)?Eliminates overhead of saving and restoring system state for interrupt requests Intelligent On-chip Peripheral Subsystems
?4-Channel 10-bit A/D Converter with programmable conversion time
(7.76 μs minimum), auto scan modes, channel injection mode
? 2 Multifunctional General Purpose Timer Units
GPT1: three 16-bit timers/ counters, maximum resolution I CPU/8
GPT2: two 16-bit imers/counters, maximum resolution I CPU/4
?Asynchronous/Synchronous Serial Channel (USART)
with baud rate generator, parity, framing, and overrun error detection
?High Speed Synchronous Serial Channel
programmable data length and shift direction
?I2C Bus Module with 10-bit addressing and 400 Kbit/sec
?Real Time Clock
?Watchdog Timer with programmable time intervals
?Bootstrap Loader for flexible system initialization
76 IO Lines With Individual Bit Addressability
?Tri-stated in input mode
?Push/pull or open drain output mode
?Programmable port driver control (fast/reduced edge)
Different Temperature Ranges
?0 to +70 °C, – 40 to +85 °C
Infineon CMOS Process
?Low Power CMOS Technology including power saving Idle, Sleep and Power Down modes with flexible power management.
100-Pin Plastic Quad Flat Pack (PQFP) Packages
?P-MQFP, 4*20 mm body, 0.65 mm (25.6 mil) lead spacing, surface mount technology ?P-TQFP, 14*14 mm body, 0.5 mm (19.7 mil) lead spacing, surface mount technology
Complete Development Support
For the development tool support of its microcontrollers, Infineon follows a clear third party concept. Currently around 120 tool suppliers world-wide, ranging from local niche manufacturers to multinational companies with broad product portfolios, offer powerful development tools for the Infineon C500 and C166 microcontroller families, guaranteeing a remarkable variety of price-performance classes as well as early availability of high quality key tools such as compilers, assemblers, simulators, debuggers or in-circuit emulators.
Infineon incorporates its strategic tool partners very early into the product development process, making sure embedded system developers get reliable, well-tuned tool solutions, which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve.
The tool environment for the Infineon 16-bit microcontrollers includes the following tools:?Compilers (C, MODULA2, FORTH)
?Macro-Assemblers, Linkers, Locaters, Library Managers, Format-Converters ?Architectural Simulators
?HLL debuggers
?Real-Time operating systems
?VHDL chip models
?In-Circuit Emulators (based on bondout or standard chips)
?Plug-In emulators
?Emulation and Clip-Over adapters, production sockets
?Logic Analyzer disassemblers
?Starter Kits
?Evaluation Boards with monitor programs
?Industrial boards (also for CAN, FUZZY, PROFIBUS, FORTH applications)?Network driver software (CAN, PROFIBUS)
1.3Abbreviations
The following acronyms and termini are used within this document:
ADC Analog Digital Converter
ALE Address Latch Enable
ALU Arithmetic and Logic Unit
ASC Asynchronous/synchronous Serial Controller
CISC Complex Instruction Set Computing
CMOS Complementary Metal Oxide Silicon
CPU Central Processing Unit
EBC External Bus Controller
ESFR Extended Special Function Register
Flash Non-volatile memory that may be electrically erased GPR General Purpose Register
GPT General Purpose Timer unit
HLL High Level Language
I2C Inter Integrated Circuit (Bus)
IO Input / Output
OTP One Time Programmable memory
PEC Peripheral Event Controller
PLA Programmable Logic Array
PLL Phase Locked Loop
PWM Pulse Width Modulation
RAM Random Access Memory
RISC Reduced Instruction Set Computing
ROM Read Only Memory
SDD Slow Down Divider
SFR Special Function Register
SSC Synchronous Serial Controller
XBUS Internal representation of the External Bus
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2Architectural Overview
The architecture of the C161PI combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features which are combined result in a high performance microcontroller, which is the right choice not only for today’s applications, but also for future engineering challenges. The C161PI not only integrates a powerful CPU core and a set of peripheral units into one chip, but also connects the units in a very efficient way. One of the four buses used concurrently on the C161PI is the XBUS, an internal representation of the external bus interface. This bus provides a standardized method of integrating application-specific peripherals to produce derivates of the standard C161PI.
Figure 2-1C161PI Functional Block Diagram
2.1Basic CPU Concepts and Optimizations
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Figure 2-2CPU Block Diagram
To meet the demand for greater performance and flexibility, a number of areas has been optimized in the processor core. Functional blocks in the CPU core are controlled by signals from the instruction decode logic. These are summarized below, and described in detail in the following sections:
1) High Instruction Bandwidth / Fast Execution
2) High Function 8-bit and 16-bit Arithmetic and Logic Unit
3) Extended Bit Processing and Peripheral Control
4) High Performance Branch-, Call-, and Loop Processing
5) Consistent and Optimized Instruction Formats
6) Programmable Multiple Priority Interrupt Structure
2.1.1High Instruction Bandwidth / Fast Execution
Based on the hardware provisions, most of the C161PI’s instructions can be executed in just one machine cycle, which requires 2 CPU clock cycles (2 * 1/I CPU = 4TCL). For example, shift and rotate instructions are always processed within one machine cycle, independent of the number of bits to be shifted.
Branch-, multiply- and divide instructions normally take more than one machine cycle. These instructions, however, have also been optimized. For example, branch instructions only require an additional machine cycle, when a branch is taken, and most branches taken in loops require no additional machine cycles at all, due to the so-called ‘Jump Cache’.
A 32-bit / 16-bit division takes 20 CPU clock cycles, a 16-bit * 16-bit multiplication takes
10 CPU clock cycles.
The instruction cycle time has been dramatically reduced through the use of instruction pipelining. This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel. The following four stage pipeline provides the optimum balancing for the CPU core:
FETCH: In this stage, an instruction is fetched from the internal ROM or RAM or from the external memory, based on the current IP value.
DECODE: In this stage, the previously fetched instruction is decoded and the required operands are fetched.
EXECUTE: In this stage, the specified operation is performed on the previously fetched operands.
WRITE BACK: In this stage, the result is written to the specified location.
If this technique were not used, each instruction would require four machine cycles. This increased performance allows a greater number of tasks and interrupts to be processed. Instruction Decoder
Instruction decoding is primarily generated from PLA outputs based on the selected opcode. No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs. Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers. Multiple-cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals.
High Function 8-bit and 16-bit Arithmetic and Logic Unit
All standard arithmetic and logical operations are performed in a 16-bit ALU. In addition, for byte operations, signals are provided from bits six and seven of the ALU result to correctly set the condition flags. Multiple precision arithmetic is provided through a ’CARRY-IN’ signal to the ALU from previously calculated portions of the desired operation. Most internal execution blocks have been optimized to perform operations on either 8-bit or 16-bit quantities. Once the pipeline has been filled, one instruction is completed per machine cycle, except for multiply and divide. An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle. Thus, these operations use two coupled 16-bit registers, MDL and MDH, and require four and nine machine cycles, respectively, to perform a 16-bit by 16-bit (or 32-bit by 16-bit) calculation plus one machine cycle to setup and adjust the operands and the result. Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response. Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations. The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements.
A set of consistent flags is automatically updated in the PSW after each arithmetic, logical, shift, or movement operation. These flags allow branching on specific conditions. Support for both signed and unsigned arithmetic is provided through user-specifiable branch tests. These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine.
All targets for branch calculations are also computed in the central ALU.
A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic shifts are also supported.
Extended Bit Processing and Peripheral Control
A large number of instructions has been dedicated to bit processing. These instructions provide efficient control and testing of peripherals while enhancing data manipulation. Unlike other microcontrollers, these instructions provide direct access to two operands in the bit-addressable space without requiring to move them into temporary flags.
The same logical instructions available for words and bytes are also supported for bits. This allows the user to compare and modify a control bit for a peripheral in one instruction. Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations. These are also performed in a single machine cycle.
In addition, bit field instructions have been provided, which allow the modification of multiple bits from one operand in a single instruction.