M6MGT331S8BKT中文资料
33,554,432-BIT (2,097,152 -WORD BY 16-BIT /4,194,304-WORD BY 8-BIT) CMOS
FLASH MEMORY &
8,388,608-BIT (524,288-WORD BY 16-BIT /1,048,576-WORD BY 8-BIT) CMOS SRAM
Stacked-μMCP (micro Multi Chip Package) The M6MGB/T331S8BKT is a Stacked micro Multi Chip
Package (S-μMCP) that contents 32M-bit Flash memory
and 8M-bit Static RAM in a 52-pin TSOP for lead free use.
32M-bit Flash memory is a 4,194,304 bytes / 2,097,152
words, , single power supply and high performance non-
volatile memory fabricated by CMOS technology for the
peripheral circuit and DINOR (Divided bit-line NOR IV)
architecture for the memory cell. All memory blocks are
locked and can not be programmed or erased, when F-WP#
is low. Using Software Lock Release function, program or
erase operation can be executed.
8M-bit SRAM is a 1,048,576 bytes / 524,288 words
asynchronous SRAM fabricated by CMOS technology for the
peripheral circuit .
The M6MGB/T331S8BKT is suitable for a high
performance cellular phone and a mobile PC that are
required to be small mounting area, weight and small
power dissipation
Access Time Flash70ns (Max.)
SRAM85ns (Max.)
Supply Voltage VCC=2.7 ~ 3.0V
Ambient Temperature Ta=-40 ~ 85 °C
Package52pin TSOP(Type-II),
Lead pitch 0.4mm
Outer-lead finishing:Sn-Cu
Application
Outline
52PTJ-A
Mobile communication products
Description
Features
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A15
A14
A13
A12
A11
A10
A9
A8
A19
S-CE1#
F-RP#
F-WP#
S-CE2
A20
A18
A17
A7
A6
A5
A4
A3
S-UB#
GND
S-LB#
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
F-VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
28
27
F-CE#
A0
25
26
A2
A1
10.49mm
S-VCC
WE#
A16
DU
BYTE#
1
.
7
9
m
m
F-VCC
S-VCC
GND
A-1-A18
A19-A20
DQ0-DQ15
F-CE#
S-CE1#
S-CE2
OE#
WE#
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable1
:SRAM Chip Enable2
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
F-WP#
F-RP#
BYTE#
S-LB#
S-UB#
DU
:Flash Write protect
:Flash Reset Power Down
:Flash/SRAM Byte Enable
:SRAM Lower Byte
:SRAM Upper Byte
:Do not use
M6MGB/T331S8BKT
33,554,432-BIT (2,097,152 -WORD BY 16-BIT /4,194,304-WORD BY 8-BIT) CMOS
FLASH MEMORY &
8,388,608-BIT (524,288-WORD BY 16-BIT /1,048,576-WORD BY 8-BIT) CMOS SRAM
Stacked-μMCP (micro Multi Chip Package) Capacitance
MCP Block Diagram
Min.Typ.Max.
CIN
Input
capacitance
A20-A0, OE#, WE#, F-CE#, F-WP#, F-RP#,
S-CE1#, S-CE2, BYTE#, S-LB#, S-UB#
18pF COUT
Output
Capacitance
DQ15-DQ022pF Symbol Conditions
Ta=25 °C,
f=1MHz,
Vin=Vout=0V
Unit
Limits
Parameter
A0 to A20
A0 to A20
F-WP#
F-RP#
WE#
OE#
S-UB#
S-LB#
1)
DQ0 to DQ15
32Mbit DINOR(IV)
Flash Memory
F-Vcc GND
F-CE#
8Mbit
SRAM
S-Vcc
A0 to A18
S-CE1#
S-CE2
BYTE#
1) 2)
1) 2)
1)
Note 1): In case of x8 organization, A-1 is added, and only Lower Byte data(DQ0 to DQ7) are assigned to I/O and Upper Byte data(DQ8 to DQ15) are High-Z.
Note 2): In the data sheet there are “VCC”s which mean “F-VCC”or "S-VCC". In the SRAM part there are “UB#”and “LB#”which mean “S-UB#”and“S-LB#”, respectively.
Note 3): “DU(Don’t Use)”pin must be OPEN ,otherwise be inputted within 0V ~Vcc.
Nippon Bldg.,6-2,Otemachi2-chome,Chiyoda-ku,Tokyo,100-0004 Japan