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MAX2310EEI中文资料

General Description

The MAX2310/MAX2312/MAX2314/MAX2316 are IF receivers designed for dual-band, dual-mode, and sin-gle-mode N-CDMA and W-CDMA cellular phone sys-tems. The signal path consists of a variable gain amplifier (VGA) and I/Q demodulator. The devices fea-ture guaranteed +2.7V operation, a dynamic range of over 110dB, and high input IP3 (-33dBm at 35dB gain,1.7dBm at -35dB).

Unlike similar devices, the MAX2310 family of receivers includes dual oscillators and synthesizers to form a self-contained IF subsystem. The synthesizer’s refer-ence and RF dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architec-tures using any common reference and IF frequency.The differential baseband outputs have enough band-width to suit both N-CDMA and W-CDMA systems, and offer saturated output levels of 2.7Vp-p at a low +2.75V supply voltage. Including the low-noise voltage-con-trolled oscillator (VCO) and synthesizer, the MAX2310draws only 26mA from a +2.75V supply in CDMA (dif-ferential IF) mode.

The MAX2310/MAX2312/MAX2314/MAX2316 are avail-able in 28-pin QSOP packages.

Applications

Single/Dual/Triple-Mode CDMA Handsets Globalstar Dual-Mode Handsets Wireless Data Links

Tetra Direct-Conversion Receivers Wireless Local Loop (WLL)

Features

o Complete IF Subsystem Includes VCO and Synthesizer o Supports Dual-Band, Triple-Mode Operation o VGA with >110dB Gain Control o Quadrature Demodulator o High Output Level (2.7V)

o Programmable Charge-Pump Current

o Supports Any IF Frequency Between 40MHz and 300MHz o 3-Wire Programmable Interface o Low Supply Voltage (+2.7V)

MAX2310/MAX2312/MAX2314/MAX2316

with VCO and Synthesizer

________________________________________________________________Maxim Integrated Products 1

Pin Configurations appear at end of data sheet.Block Diagram appears at end of data sheet.

Ordering Information

Selector Guide

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/6f10906718.html,.

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 2_______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(V CC = +2.7V to +5.5V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10k ?, T A = -40°C to +85°C,registers set to default power-up settings. Typical values are at V CC = +2.75V and T A = +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V CC to GND..............................................................-0.3V, +6.0V SHDN to GND.............................................-0.3V to (V CC + 0.3V)STBY , BUFEN , MODE, EN, DATA,

CLK, DIVSEL...........................................-0.3V to (V CC + 0.3V)VGC to GND...............-0.3V, the lesser of +4.2V or (V CC + 0.3V)AC Signals TankH ±, TankL ±,

REF, FM ±, CDMA ±.................................................1.0V peak

Digital Input Current SHDN , MODE, DIVSEL,

BUFEN , DATA, CLK, EN , STBY .....................................±10mA Continuous Power Dissipation (T A = +70°C)

28-pin QSOP (derate 10mW/°C above T A = +70°C)....800mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +160°C Lead Temperature (soldering, 10s).................................+300°C

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________3

AC ELECTRICAL CHARACTERISTICS

(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, V CC = +2.75V, registers set to default power-up states, f IN = 210.88MHz for CDMA, f IN = 85.88MHz for FM, f REF = 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k ?, all power levels referred to 50?, T A = +25°C, unless otherwise noted.)

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 4_______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

Note 1:FM_IQ and FM_I modes are not available on MAX2312 and MAX2316.Note 2:Recommended operating frequency range.

Note 3:f 1= 210.88MHz, f 2= 210.89MHz, P f1 = P f2 = -15dBm.Note 4:f 1= 210.88MHz, f 2= 210.89MHz, P f1 = P f2= -50dBm.

Note 5:Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at 1.25MHz below the LO frequency is applied at the specified level.Note 6:Guaranteed by design and characterization.

Note 7:f 1= 85.88MHz, f 2= 85.98MHz, P f1 = P f2= -15dBm.Note 8:f 1= 85.88MHz, f 2= 85.98MHz, P f1 = P f2= -50dBm.Note 9:

Measured at LOOUT with BD = 0 (÷2 selected).

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________5

20.00

25.0022.5030.0027.5032.5035.002.5

3.5

4.0

3.0

4.5

5.0

5.5

RECEIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

S U P P L Y C U R R E N T (m A )

00.0040.002

0.008

0.0060.0120.0100.0142.0

3.0

3.5

2.5

4.0

4.5

5.0

5.5

RECEIVE SHUTDOWN CURRENT vs.

SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)S H U T D O W N C U R R E N T (m A )-80

-60-40

-20020406080

0.5

1.0

1.5

2.0

2.5

3.0

GAIN vs. V

V GC (V)

G A I N (d B )

152520353040455550600

100

200

300

400

500

GAIN vs. INPUT FREQUENCY

FREQUENCY (MHz)G A I N (d B )

56.0

57.056.5

57.559.0

59.558.558.060.00

102

1214161820

GAIN vs. BASEBAND FREQUENCY

M A X 2310 t o c 05

FREQUENCY (MHz)

R E L A T I V E G A I N (d B )

-60

-40-50-20-300-1010-60-200-4020

406080

THIRD-ORDER INPUT INTERCEPT vs. GAIN

GAIN (dB)

I I P 3 (d B m )

602010

30405070-40-20-100-3010205040603070

NOISE FIGURE vs. GAIN

M A X 2310 t o c 07

GAIN (dB)

N F (d B )

6.06.46.26.86.6

7.27.07.4-40

-20

100

NOISE FIGURE vs. TEMPERATURE

M A X 2310 t o c 08

TEMPERATURE (°C)

N F (d B )

LOCK

VCO VOLTAGE

VCO VOLTAGE vs. TIME

TIME (500μs/div)

V O L T S (1V /d i v )

SHDN LOCK TIME

1.83ms

Typical Operating Characteristics

Pin Description

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 6_______________________________________________________________________________________

FM PORT

S11 vs. FREQUENCY

3: 4 - j73 210MHz 4: 1.8 - j39 600MHz

TANKL PORT 1/S11 vs. FREQUENCY

M A X 2310

t o c 11

μs, 100MHz μs, 160MHz 3: -3.11ms + j1.45ms, 240MHz 4: -3.04ms + j1.85ms, 300MHz

TANKH PORT 1/S11 vs. FREQUENCY

M A X

2310 t o c 12

3: 2.11ms +j 2.53ms, 420MHz 4: 2.17ms +j 3.71ms, 600MHz

Typical Operating Characteristics (continued)

LOOUT PORT S22 vs. FREQUENCY

? (Re) ? (1m)? (Re)? (1m)? (Re)? (1m)

300MHz

CDMA PORT S11 vs. FREQUENCY

? - j56?? - j200?3: 210MHz, 73? - j169?4: 600MHz, 2.1? - j34?

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________7

Pin Description (continued)

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 8

_______________________________________________________________________________________

_______________Detailed Description

MAX2310

The MAX2310 is intended for dual-band (PCS and cel-lular) and dual-mode code division multiple access (CDMA) and FM applications (Figure 1). The device includes an IF variable-gain amplifier, quadrature demodulator, dual VCOs, and dual-frequency synthe-sizers (Figure 7). Dual VCOs are provided for applica-tions using different IF frequencies for each mode or band of operation. The analog FM output signal can be

configured for conversion to the I channel, or it may be converted in quadrature to both the I and Q channels.The MAX2310’s operation modes are described in Table 1. These modes are set by programming the con-trol register and setting logic levels on control pins. If MODE is left floating, the internal register controls the operation. If driven high or low, mode will override cer-tain register bits, as shown in Table 1.

Figure 1. MAX2310 Typical Operating Circuit

MAX2312/MAX2316

The MAX2312/MAX2316 quadrature demodulators are simplified versions of the MAX2310 that can be used in single-mode CDMA or dual mode using an external FM discriminator (Figures 2a and 2b). The MAX2312 VCO is optimized for the 67MHz to 300MHz IF frequency range, while the MAX2316 VCO is optimized for the 40MHz to 150MHz IF frequency range.

Both devices include a buffered output for the VCO.The buffered VCO output can be used to support sys-tems implementing traditional limiting IF stages for FM demodulation in dual-mode phones as well as for the transmit LO in TDD systems. This buffered output can

be configured for the VCO frequency (twice the IF fre-quency) or one-half the VCO frequency (IF frequency).The BUFEN pin enables this feature. A standby mode,in which only the VCO and synthesizer are operational,can be selected through the serial interface or the STBY pin. The MAX2312/MAX2316s’ operational modes are described in Table 2. These modes are set by pro-gramming the control register and/or setting logic lev-els on control pins. If the control pins (STBY , BUFEN ,DIVSEL) are left floating, the internal register controls the operational mode. If driven high or low, the control pins will override certain register bits, as shown in Table 2.

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

_______________________________________________________________________________________

Table 1. MAX2310 Control Register States

Note:H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low.

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 10______________________________________________________________________________________

Figure 2a. MAX2312 Typical Operating Circuit

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________11

Figure 2b. MAX2316 Typical Operating Circuit

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 12______________________________________________________________________________________

Table 2. MAX2312/MAX2316 Control Register States

Note:H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter.

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________13

MAX2314

The MAX2314 supports CDMA cellular-band, dual-mode operation. As with the MAX2310, the FM mode can be configured for conversion to the I port or quad-rature conversion to both the I and Q ports (Figure 3).The MAX2314’s operational modes are described in Table 3. These modes are set by programming the control register and setting logic levels on control pins.

__________Applications Information

Variable-Gain Amplifier and Demodulator

The MAX2310 family provides a Variable-Gain Amplifier (VG A) with exceptional gain range. The MAX2310/MAX2314 support multimode applications with dual dif-ferential inputs, selectable with the IN_SEL (IS) control bit. On the MAX2310 this function can be controlled with the MODE pin, which overrides the IS control bit.The VGA’s gain is controlled over a 110dB range with

Figure 3. MAX2314 Typical Operating Circuit

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 14______________________________________________________________________________________

the VGC pin. The output of the VGA drives the RF ports of a quadrature demodulator. The MAX2310/MAX2314provide two types of FM demodulation, controlled by the FM_TYPE (FT) control bit. When FM_TYPE is “1,”the signal is passed through both the I and Q signal paths for subsequent lowpass filtering and A/D conver-sion at baseband. If FM_TYPE is “0,” the FM signal is passed through the I mixer only.

Voltage-Controlled Oscillator,

Buffers, and Quadrature Generation

The LO signal for downconversion is provided by a voltage-controlled oscillator (VCO) consisting of an on-chip differential oscillator, and an off-chip high-Q reso-nant network. Figure 4 shows a simplified schematic of the VCO oscillator. Multiband operation is supported by the MAX2310 with dual VCOs. VCO_H and VCO_L are selectable with the MODE pin or the VCO_SEL (VS)

control bit. They oscillate at twice the desired LO fre-quency. For applications requiring an external LO, the VCOs can be bypassed with the VCO_BYP (VB) control bit.

The MAX2312/MAX2316 buffer the output of the VCO and provide this signal at the LOOUT pin. This signal is enabled by the BUFEN (BE) control bit or by the BUFEN control pin. The frequency of this signal is selected by the BUF_DIV (BD) control bit, and can be either the VCO frequency or half the VCO frequency.Quadrature downconversion is realized by providing in-phase (I) and quadrature-phase (Q) components of the LO signal to the LO ports of the demodulator described above. The quadrature LO signals are generated by dividing the VCO output frequency using two latches.The appropriate latch outputs provide I and Q signals at the desired LO frequency.

Note:H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________

Synthesizer

The VCO’s output frequency is controlled by an internal phase-locked-loop (PLL) dual-modulus synthesizer.The loop filter is off-chip to simplify loop design for emerging applications. The tunable resonant network is also off-chip for maximum Q and for system design flexibility. The VCO output frequency is divided down to the desired comparison frequency with the M counter.The M counter consists of a 4-bit A swallow counter and a 10-bit P counter. A reference signal is provided from an external source and is divided down to the comparison frequency with the R counter. The two divided signals are compared with a three-state digital phase-frequency detector. The phase-detector output drives a charge pump as well as lock-detect logic and turbocharge control logic. The charge pump output (CP_OUT) pin is processed by the loop filter and drives the tunable resonant network, altering the VCO fre-quency and closing the loop.

Multimode applications are supported by two indepen-dent programmable registers each for the M counter (M1, M2), the R counter (R1, R2), and the charge-pump output current magnitude (CP1, CP2). The DIVSEL (DS)bit selects which set of registers is used. It can be over-ridden by the MAX2310’s MODE pin or the MAX2312/MAX2316’s DIVSEL pin. Programming these registers is discussed in the 3-Wire Interface and R egisters sec-tion.

When the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the Turbo feature, enabled by the TURBOCHARG E (TC) control bit. Turbo functionality provides a larger charge-pump current during acquisition mode. Once the VCO frequency is acquired, the charge-pump out-put current magnitude automatically returns to the pre-programmed state to maintain loop stability and minimize spurs in the VCO output signal.

The lock detect output indicates when the PLL is locked with a logic high.

3-Wire Interface and Registers

The MAX2310 family incorporates a 3-wire interface for synthesizer programming and device configuration (Figure 5). The 3-wire interface consists of a clock,data, and ENABLE . It controls the VCO dividers (M1and M2), reference frequency dividers (R1 and R2),and a 13-bit control register. The control register is used to set up the operational modes (Table 4). The input shift is 17 data bits long and requires a total of 18clock bits (Figure 6). A single clock pulse is required before enable drops low to initialize the data bus.Whenever the M or R divide register value is pro-grammed and downloaded, the control register must also be subsequently updated. This prevents turbolock from going active when not desired.

The SHDN control bit is notable because it differs from the SHDN pin. When the SHDN control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. In contrast, the SHDN pin, when low,shuts down everything, including the registers and seri-al interface. See the functional diagram in Figure 7.

Registers

Figure 8 shows the programming logic. The 17-bit shift register is programmed by clocking in data at the rising edge of CLK. Before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the CLK input with EN high (see Figure 6). Pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by A0, A1, and A2, respectively (Figure 8). Table 5 lists the power-on default values of all registers. Table 6 lists the charge-pump current,depending on CP0 and CP1.

Figure 4. Voltage-Controlled Oscillators

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 16______________________________________________________________________________________

Figure 5. 3-Wire Control Block Diagram

Figure 6. 3-Wire Interface Timing Diagram

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________

Figure 7. Functional Diagram

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 18______________________________________________________________________________________

Table 4. Control Register, Default State: 0B57h,Address: 110b

Table 5. Register Defaults

Table 6. Charge-Pump Control Bits

MAX2310/MAX2312/MAX2314/MAX2316

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

______________________________________________________________________________________19

Figure 8. Programming Logic

M A X 2310/M A X 2312/M A X 2314/M A X 2316

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

Pin Configurations