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IRF3205ZPBF_15

IRF3205ZPBF_15
IRF3205ZPBF_15

07/23/10

?This HEXFET ? Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications.

Description

l Advanced Process Technology l Ultra Low On-Resistance

l 175°C Operating Temperature l Fast Switching

l Repetitive Avalanche Allowed up to Tjmax Features

IRF3205ZPbF IRF3205ZSPbF IRF3205ZLPbF

D 2Pak IRF3205ZSPbF TO-220AB IRF3205ZPbF

TO-262IRF3205ZLPbF

l

Lead-Free

PD - 95129A

IRF3205ZS/LPbF

https://www.wendangku.net/doc/6817670137.html,

GS = 0V e DD = 25V

IRF3205ZS/LPbF

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Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics Fig 3. Typical Transfer Characteristics

Fig 4. Typical Forward Transconductance

Vs. Drain Current

I , D r a i n -t o -S o u r c e C u r r e n t (A )

I , D r a i n -t o -S o u r c e C u r r e n t (A )

V GS , Gate-to-Source Voltage (V)I D , D r a i n -t o -S o u r c e C u r r e n t ( A )

20

40

60

80

100

I D, Drain-to-Source Current (A)

20406080100120

G f s , F o r w a r d T r a n s c o n d u c t a n c e (S )

IRF3205ZS/LPbF

https://www.wendangku.net/doc/6817670137.html,

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage Fig 7. Typical Source-Drain Diode

Forward Voltage

0.2

0.6

1.0

1.4

1.8

2.2

V SD , Source-toDrain Voltage (V)

0.1

1.0

10.0

100.0

1000.0I S D , R e v e r s e D r a i n C u r r e n t (A )

1

10

100

V DS , Drain-to-Source Voltage (V)

01000

2000

3000

4000

5000

6000

C , C a p a c i t a n c e (p F )

1

10

1001000

V DS , Drain-toSource Voltage (V)

0.1

1

10

100

1000

10000

I D , D r a i n -t o -S o u r c e C u r r e n t (A

)

20

40

60

80

100

120

Q G Total Gate Charge (nC)

04

8

12

16

20V

G S , G a t e -t o -S o u r c e V o l t a g e (V )

IRF3205ZS/LPbF

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Fig 9. Maximum Drain Current Vs.

Case Temperature

Fig 10. Normalized On-Resistance

Vs. Temperature

25

50

75

100

125

150

175

T C , Case Temperature (°C)

020406080100120

I D , D r a i n C u r r e n t (A

)

-60-40-20

20406080100120140160180

T J , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

R D S (o n ) , D r a i n -t o -S o u r c e O n R e s i s t a n c e (N o r m a l i z e d )

IRF3205ZS/LPbF

6

https://www.wendangku.net/doc/6817670137.html,

V Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12a. Unclamped Inductive Test Circuit

I Fig 14. Threshold Voltage Vs. Temperature

V DD

25

50

75

100

125

150

175

Starting T J , Junction Temperature (°C)

050100150200250300350

E A S , S i n g

l e P u l s e A v a l a n c h e E n e r g y (m J )

-75-50-25

25

50

75

100125150175

T J , Temperature ( °C )

1.0

2.0

3.0

4.0

V

G S (t h ) G a t e t h r e s h o l d V o l t a g

e (V )

IRF3205ZS/LPbF

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Fig 15. Typical Avalanche Current Vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:(For further info, see AN-1005 at https://www.wendangku.net/doc/6817670137.html,)1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax . This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.

4. P D (ave) = Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I av = Allowable avalanche current.

7. ?T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25°C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av ·f

Z thJC (D, t av ) = Transient thermal resistance, see figure 11)

P D (ave) = 1/2 ( 1.3·BV·I av ) = D T/ Z thJC

I av = 2D T/ [1.3·BV·Z th ]E AS (AR) = P D (ave)·t av

tav (sec)

A v a l a n c h e C u r r e n t (A

)

25

50

75

100

125

150

175Starting T J , Junction Temperature (°C)

040

80

120

160

200

E A R , A v a l a n c h e E n e r g y (m J )

IRF3205ZS/LPbF

https://www.wendangku.net/doc/6817670137.html,

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET ? Power MOSFETs

* V GS = 5V for Logic Level Devices

V V d(on)

r

d(off)

f

V DD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

IRF3205ZS/LPbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

For the most current drawing please refer to IR website at https://www.wendangku.net/doc/6817670137.html,/package/

https://www.wendangku.net/doc/6817670137.html,

TO-262 Package Outline Dimensions are shown in millimeters (inches)

IRF3205ZS/LPbF

https://www.wendangku.net/doc/6817670137.html,

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at https://www.wendangku.net/doc/6817670137.html, for sales contact information . 07/2010

Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11). Limited by T Jmax , starting T J = 25°C, L = 0.08mH R G = 25?, I AS = 66A, V GS =10V. Part not recommended for use above this value. Pulse width ≤ 1.0ms; duty cycle ≤ 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising

from 0 to 80% V DSS .

Notes:

Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.

This value determined from sample failure population. 100% tested to this value in production. This is only applied to TO-220AB pakcage. This is applied to D 2Pak, when mounted on 1" square PCB (FR- 4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.

3

4

4

TRR

FEED DIRECTION

1.85 (.073)

1.65 (.065)

1.60 (.063)1.50 (.059)

4.10 (.161)3.90 (.153)

TRL

FEED DIRECTION 10.90 (.429)10.70 (.421)

16.10 (.634)15.90 (.626)

1.75 (.069)1.25 (.049)

11.60 (.457)11.40 (.449)

15.42 (.609)15.22 (.601)

4.72 (.136)4.52 (.178)

24.30 (.957)23.90 (.941)

0.368 (.0145)0.342 (.0135)

1.60 (.063)1.50 (.059)

13.50 (.532)12.80 (.504)330.00(14.173) MAX.

27.40 (1.079)23.90 (.941)

60.00 (2.362) MIN.

30.40 (1.197) MAX.

26.40 (1.039)24.40 (.961)

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

D 2Pak Tape & Reel Infomation

Dimensions are shown in millimeters (inches)

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