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ZA7783 mipi转lvds和rgb产品规格书

ZA7783Display Interface Converter

Datasheet

Version1.1

Revision History

Ver.Date Author Content

0.52013-5-14Dai Jin 1.Initial release

0.62013-9-29Jiang Bo 1.Add typical application circuit

2.Add package information

3.Add functional block diagram

0.72014-2-12Jiang Bo 1.Change LVDS_ATO to DVDD18

1.02014-4-28Jiang Bo 1.Add software register description

2.Add more details for typical application circuit

3.Add software guideline

4.Add electrical parameters

1.12014-9-3Jiang Bo 1.Change DVDD12cap to0.47uF

2.Modify power-up sequence

周先生手机丗185******** QQ:490364344

Table of Contents

1OVERVIEW (3)

2TARGET APPLICATIONS (3)

3FEATURE DESCRIPTION (3)

4FUNCTIONAL BLOCK DIAGRAM (5)

5PIN CONFIGURATION (6)

6ELECTRICAL PARAMETERS (9)

7TYPICAL APPLICATION CIRCUIT (13)

8SOFTWARE REGISTER DESCRIPTION (17)

9SOFTWARE GUIDELINE (28)

10PACKAGE INFORMATION (30)

周先生手机丗185******** QQ?F490364344

1Overview

ZA7783is a bridge chip which supports three kinds of display interfaces:

●MIPI DSI RX Interface(1Clock Lane+4Data Lanes)

●LVDS TX Interface(1Clock Lane+4Data Lanes)

●MIPI DPI TX/RX Interface(PCLK+RGB888+VSYNC+HSYNC+

DATAEN)

The chip bridges these display interfaces in three working modes:

●MODE1:MIPI DSI RX=>LVDS TX

●MODE2:MIPI DSI RX=>DPI TX

●MODE3:DPI RX=>LVDS TX

Besides,there is also an I2C control interface(XCLK+I2C_SCL+I2C_SDA)for the host chip(AP or BB)to access ZA7783’s software registers.

Analog IPs of ZA7783are supplied by3.3V voltage(typical).For Digital IOs,the host interface(XCLK+I2C_SCL+I2C_SDA)is supplied by DVDD18(PIN32), while the DPI interface(PCLK+RGB888+VSYNC+HSYNC+DATAEN)is supplied by DVDD33(PIN45and PIN59).Thus,ZA7783is able to bridge AP or BB with 1.8V IO to RGB Panel with 3.3V IO.Besides,an embedded LDO converts3.3V to1.2V to supply the chip’s internal digital logic.In addition,an embedded POR implements a power on reset to the whole chip.

2Target Applications

Tablet PC

3Feature Description

MIPI DSI RX Interface

●Compliant to MIPI DSI V1.01and MIPI D-PHY V1.00

●1Clock Lane+4Data Lanes

●Data rate up to600Mbps per data lane(300MHz high-speed clock on clock lane)

● 2.4Gbps bandwidth on four data lanes in total,giving a display resolution up to

1366x76824bpp@60fps

●Only support MIPI DSI Video Mode(Non-Burst Mode with Sync Pulses)and all lanes

are unidirectional from the host chip to the bridge chip

●The host chip is required to provide continuous high-speed clock

●Only support using all of the four data lanes,in other words,using part of them is not

supported

●Support multiple packets within a single high-speed transmission

●Ignore received virtual channel field

●Only the following packet data types are supported:

6'h01=Sync Event,V Sync Start(Short)

6'h11=Sync Event,V Sync End(Short)

6'h21=Sync Event,H Sync Start(Short)

6'h31=Sync Event,H Sync End(Short)

6'h08=End of Transimission packet(EoTp)(Short)

6'h09=Null Packet,no data(Long)

6'h19=Blanking Packet,no data(Long)

6'h2E=Loosely Packed Pixel Stream,18-bit RGB,6-6-6Format(Long)

6'h3E=Packed Pixel Stream,24-bit RGB,8-8-8Format(Long)

The other packet data types cannot be handled and must not be sent to ZA7783!

●Ignore received ecc field

●Ignore received checksum field

●RGB565Packed Pixel Stream and RGB666Packed Pixel Stream are not supported

●For a data lane,the connection of Dp/Dn can be exchanged

●The order of the four data lanes can be configured

●Dither function for converting RGB888to RGB666

LVDS TX Interface

●Compliant to LVDS Spec

●1Clock Lane+4Data Lanes

●Support RGB888and RGB666

RGB888:1Clock Lane+4Data Lanes

RGB666:1Clock Lane+3Data Lanes

●Support NS Mode and JEIDA Mode

●The polarity of VSYNC/HSYNC/DATAEN can be configured

●For a data lane,the connection of Dp/Dn can be exchanged

●The order of the four data lanes can be configured

●Dither function for converting RGB888to RGB666

DPI TX/RX Interface

●PCLK+RGB888+VSYNC+HSYNC+DATAEN

●The edge of PCLK can be configured

●The polarity of VSYNC/HSYNC/DATAEN can be configured

I2C Interface

●An external clock XCLK should be provided(e.g.26MHz)

●Up to400Kbps

●I2C Slave ID is0x37

4Functional Block Diagram

5Pin Configuration

https://www.wendangku.net/doc/781323030.html, Description

1R4DPI R[7:4]

2R53R64R75DVDD12LDO 1.2V Output (connected to 0.47uF ceramic cap)Digital Core 1.2V Power Supply 6AVDD33LDO 3.3V Power Supply 7

MIPI_CLKP

MIPI DSI RX Clock Lane

8MIPI_CLKN 9MIPI_D0P MIPI DSI RX Data Lane 0~3

10MIPI_D0N 11MIPI_D1P 12MIPI_D1N 13MIPI_D2P 14MIPI_D2N 15MIPI_D3P 16MIPI_D3N 17MIPI_AVDD33MIPI PHY 3.3V Power Supply

18MIPI_REXT Tie a 24KOhm resistor (1%accuracy)to analog ground 19MIPI_BGVDD33MIPI PHY 3.3V BandGap Supply 20LVDS_AVDD33LVDS TX 3.3V Power Supply 21LVDS_D0P LVDS TX Data Lane 022LVDS_D0N 23LVDS_D1P LVDS TX Data Lane 124LVDS_D1N 25LVDS_CLKP LVDS TX Clock Lane 26LVDS_CLKN 27LVDS_D2P LVDS TX Data Lane 228LVDS_D2N 29LVDS_D3P LVDS TX Data Lane 3

30LVDS_D3N 31LVDS_PLLVDD33

LVDS TX 3.3V PLL Supply 32DVDD18

Digital IO 1.8V Power Supply

This power supply is for XCLK/I2C_SCL/I2C_SDA.33I2C_SDA I2C Serial Data Line 34I2C_SCL I2C Serial Clock Line 35XCLK XCLK Input (e.g.26MHz)36B0DPI B[3:0]37B138B239B340DVSS Digital Ground 41B4DPI B[7:4]

42B543B644B745DVDD33Digital IO 3.3V Power Supply

This power supply is for DPI IF,including PCLK,R7~0,G7~0,B7~0,VSYNC,HSYNC,and DATAEN.46DATAEN DPI Data Enable 47HSYNC DPI HSYNC 48VSYNC DPI VSYNC 49G0DPI G[3:0]50G151G252G353DVSS Digital Ground 54G4DPI G[7:4]

56G657G758PCLK DPI Pixel Clock

59DVDD33Digital IO 3.3V Power Supply

This power supply is for DPI IF,including PCLK,R7~0,G7~0,B7~0,VSYNC,HSYNC,and DATAEN.60R0DPI R[3:0]

61R162R263R364DVSS Digital Ground

EP(65)

AVSS

Analog Ground for LDO,MIPI PHY,and LVDS TX

6Electrical Parameters

ABSOLUTE MAXIMUM RATINGS

MIN MAX UNIT

Supply Voltage Range

AVDD33-0.3+4V MIPI_AVDD33-0.3+4V MIPI_BGVDD33-0.3+4V LVDS_AVDD33-0.3+4V LVDS_PLLVDD33-0.3+4V DVDD33-0.3+4V DVDD18-0.3+4V

Input Voltage Range CMOS Input Terminals-0.3DVDD+0.3(1)V DSI Input Terminals-0.4+1.4V

Storage Temperature Ts-65105℃

Electrostatic Discharge

Human Body Model+/-3KV Charged-Device Model+/-500V

(1)For XCLK,I2C_SCL,and I2C_SDA,DVDD means the voltage level of DVDD18.For the other digital IO,DVDD means the

voltage level of DVDD33.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT AVDD33LDO3.3V Power Supply 3.0 3.3 3.6V MIPI_AVDD33MIPI3.3V Power Supply 3.0 3.3 3.6V MIPI_BGVDD33MIPI BandGap3.3V Power Supply 3.0 3.3 3.6V LVDS_AVDD33LVDS3.3V Power Supply 3.0 3.3 3.6V LVDS_PLLVDD33LVDS PLL3.3V Power Supply 3.0 3.3 3.6V

DVDD33Digital IO Power Supply

3.0 3.3 3.6V 1.62 1.8 1.98V

DVDD18Digital IO Power Supply

3.0 3.3 3.6V 1.62 1.8 1.98V

V PSN Supply Noise on Any Power Pin0.05V

T A Operating Temperature-4085℃T CASE Case Temperature85℃V DSI_PIN DSI Input Pin Voltage Range-501350mV

F I2C I2C Input Frequency400KHz

F HS_CLK DSI HS Clock Input Frequency300MHz

T setup DSI HS Data to Clock Setup Time0.15UI(1) T hold DSI HS Data to Clock Hold Time0.15UI

Z L LVDS Output Differential Impedance90132Ohm (1)The unit interval(UI)is one half of the period of the HS clock.

ELECTRICAL CHARACTERISTICS

MIN TYP MAX UNIT V IL Low-level Control Signal Input Voltage0.3*DVDD V V IH High-level Control Signal Input Voltage0.7*DVDD V V OH High-level Output Voltage0.8*DVDD V V OL Low-level Output Voltage0.3V

I OZ High-impedance Output Current+/-10uA

I CC Device Active Current67(1)mA

I STDBY Device Standby Current500(2)uA

(1)Test Condition:

1024x76824-bit LCD Panel@PCLK=65MHz

Enable MIPI DSI RX with1Clock Lane and4Data Lanes,DSI HS Clock=195MHz

Enable LVDS TX with1Clock Lane and4Data Lanes,LVDS Clock=65MHz

Enable DPI TX,PCLK=65MHz

(2)Test Condition:

ZA7783is powered but all functions are disabled by I2C configuration.

XCLK

MIN TYP MAX UNIT F XCLK XCLK Frequency1030MHz T rise/T fall XCLK Rise/Fall Time5ns Duty XCLK Duty Cycle305070% MIPI DSI RX

MIN TYP MAX UNIT V IH-LP LP Receiver Input High Threshold880mV V IL-LP LP Receiver Input Low Threshold550mV |V ID|HS Differential Input Voltage70270mV |V IDT|HS Differential Input Voltage Threshold50mV V CM-HS HS Common Mode Voltage:Steady-State70330mV △V CM-HS HS Common Mode Peak-to-Peak Variation100mV V IH-HS HS Single-Ended Input High Voltage460mV V IL-HS HS Single-Ended Input Low Voltage-40mV R DIFF-HS HS Mode Differential Input Impedance80125Ohm ULPS(Ultra-Low Power State)is not supported.

LVDS TX

MIN TYP MAX UNIT |V OD|Steady-State Differential Output Voltage220310350mV

△|V OD|Change in Steady-State Differential Output Voltage

between Opposite Binary States

101520mV

V OC(SS)Steady State Common Mode Output Voltage 1.15 1.25 1.35V

V OC(PP)Peak-to-Peak Common Mode Output Voltage506080mV R LVDS_DIS Pull-Down Resistance for Disabled LVDS Outputs---------KOhm DPI TX/RX

MIN TYP MAX UNIT F PCLK PCLK Frequency20100MHz T PCLK PCLK Period1050ns T setup VSYNC,HSYNC,DATAEN,RGB Setup Time in DPI RX Mode2ns T hold VSYNC,HSYNC,DATAEN,RGB Hold Time in DPI RX Mode2ns SWITCHING CHARACTERISTICS

MIN TYP MAX UNIT

MIPI DSI RX

t GS DSI LP Glitch Suppression Pulse Width300ps

LVDS TX

t c Output Clock Period1050ns t w High-level Output Clock Pulse Duration4/7*t c-0.14/7*t c4/7*t c+0.1ns t0Delay Time,CLK↑to1st serial bit position-0.20+0.2ns t1Delay Time,CLK↑to2nd serial bit position1/7*t c-0.21/7*t c1/7*t c+0.2ns t2Delay Time,CLK↑to3rd serial bit position2/7*t c-0.22/7*t c2/7*t c+0.2ns t3Delay Time,CLK↑to4th serial bit position3/7*t c-0.23/7*t c3/7*t c+0.2ns t4Delay Time,CLK↑to5th serial bit position4/7*t c-0.24/7*t c4/7*t c+0.2ns

t5Delay Time,CLK↑to6th serial bit position5/7*t c-0.25/7*t c5/7*t c+0.2ns t6Delay Time,CLK↑to7th serial bit position6/7*t c-0.26/7*t c6/7*t c+0.2ns t r Differential Output Rise Time189199209ps t f Differential Output Fall Time186196208ps

LDO+POR

T LDO-SETUP LDO Setup Time to Output1.2V100us

T POR-DELAY POR Delay Time to Release Internal Reset

after1.2V Setup

2ms

Figure6-1MIPI DSI HS Mode Receiver Timing Definitions

Figure6-2MIPI DSI Receiver Voltage Definitions

Figure6-3Test Load and Voltage Definitions for LVDS Outputs

Figure6-4LVDS Timing Definitions

7Typical Application Circuit

Figure7-1Typical Application Circuit

7.1MIPI=>LVDS Reference Design

MIPI=>LVDS Reference Design derives from Typical Application Circuit:

1.ZA7783DPI IF is not used in this scenario.Leave the related pins not

connected.That is,PCLK,VSYNC,HSYNC,DATAEN,R[7:0],G[7:0],and B[7:0]are left open.

2.Connect MIPI IF of the host chip and ZA7783in a straight way.The MIPI IF

includes1clock lane and4data lanes.Just route MIPI_CLKp to MIPI_CLKp, MIPI_CLKn to MIPI_CLKn,MIPI_D0p to MIPI_D0p,MIPI_D0n to MIPI_D0n, and so on.

3.Connect LVDS IF of ZA7783and LVDS Panel in a straight way.The LVDS IF

includes1clock lane and4data lanes for24-bit LVDS Panel,or3data lanes for18-bit LVDS Panel.Just route LVDS_CLKp to LVDS_CLKp,LVDS_CLKn to LVDS_CLKn,LVDS_D0p to LVDS_D0p,LVDS_D0n to LVDS_D0n,and so on.For18-bit LVDS Panel,LVDS_D3p and LVDS_D3n are not used and left open.

4.The host chip should provide a10~30MHz clock to ZA7783’s XCLK pin.This

clock is required during I2C configuration and normal display.When the host chip shuts down LVDS Panel and switches to sleep mode,this clock may be stopped,so as to minimize power consumption.

5.The host chip uses its I2C Master IF to connect ZA7783’s I2C Slave IF to do

configuration.

6.XCLK,I2C_SCL,and I2C_SDA of ZA7783are powered by DVDD18(PIN32).

The IO voltage level of these pins on both sides(the host chip and ZA7783) should be consistent.

7.LVDS Panel may have some control pins,such as LCD_EN,LCD_RSTN,

LCD_PWM,etc.These pins should be controlled directly by the host chip.

ZA7783does nothing to these control pins.

7.2MIPI=>RGB Reference Design

MIPI=>RGB Reference Design derives from Typical Application Circuit:

1.ZA7783LVDS IF is not used in this scenario.Leave these pins open.

2.Connect MIPI IF of the host chip and ZA7783in a straight way.The MIPI IF

includes1clock lane and4data lanes.Just route MIPI_CLKp to MIPI_CLKp, MIPI_CLKn to MIPI_CLKn,MIPI_D0p to MIPI_D0p,MIPI_D0n to MIPI_D0n, and so on.

3.Connect DPI IF of ZA7783and RGB Panel in a straight way.For18-bit RGB

Panel,route R[7:2],G[7:2],and B[7:2]to the panel,while leave R[1:0],G[1:0], and B[1:0]open.

4.The host chip should provide a10~30MHz clock to ZA7783’s XCLK pin.This

clock is required during I2C configuration and normal display.When the host chip shuts down RGB Panel and switches to sleep mode,this clock may be stopped,so as to minimize power consumption.

5.The host chip uses its I2C Master IF to connect ZA7783’s I2C Slave IF to do

configuration.

6.XCLK,I2C_SCL,and I2C_SDA of ZA7783are powered by DVDD18(PIN32).

The IO voltage level of these pins on both sides(the host chip and ZA7783) should be consistent.

7.RGB Panel may have some control pins,such as LCD_EN,LCD_RSTN,

LCD_PWM,etc.These pins should be controlled directly by the host chip.

ZA7783does nothing to these control pins.

7.3RGB=>LVDS Reference Design

RGB=>LVDS Reference Design derives from Typical Application Circuit:

1.ZA7783MIPI IF is not used in this scenario.Leave these pins open.

2.Connect DPI IF of the host chip and ZA7783in a straight way.If the host chip

only outputs18-bit DPI IF,route them to R[7:2],G[7:2],and B[7:2]of ZA7783, while R[1:0],G[1:0],and B[1:0]of ZA7783are left open.

3.Connect LVDS IF of ZA7783and LVDS Panel in a straight way.The LVDS IF

4.The host chip should provide a10~30MHz clock to ZA7783’s XCLK pin.This

clock is required during I2C configuration and normal display.When the host chip shuts down LVDS Panel and switches to sleep mode,this clock may be stopped,so as to minimize power consumption.

5.The host chip uses its I2C Master IF to connect ZA7783’s I2C Slave IF to do

configuration.

6.XCLK,I2C_SCL,and I2C_SDA of ZA7783are powered by DVDD18(PIN32).

The IO voltage level of these pins on both sides(the host chip and ZA7783) should be consistent.

7.LVDS Panel may have some control pins,such as LCD_EN,LCD_RSTN,

LCD_PWM,etc.These pins should be controlled directly by the host chip.

ZA7783does nothing to these control pins.

7.4FAQ

7.4.1AVDD33and DVDD33

AVDD33and DVDD33can be supplied with a single3.3V LDO.Place decoupling capacitance close to each power supply pin to decrease noise,as Typical Application Circuit shows.

7.4.2DVDD33and DVDD18

PCLK,VSYNC,HSYNC,DATAEN,and RGB888are powered by DVDD33

(PIN45and PIN59),while XCLK,I2C_SCL,and I2C_SDA are powered by DVDD18(PIN32).Although DVDD33and DVDD18are named with the voltage level,in fact both of them can be supplied with1.8V~3.3V power.For example, users can supply1.8V to DVDD33,or3.3V to DVDD18.

7.4.3Power-Up Sequence

DVDD18should be supplied first,and then AVDD33and DVDD33.

7.4.4Power-Down Sequence

The sequence of removing AVDD33,DVDD33,and DVDD18is unconstrained. 7.4.5PCB Layout of MIPI/LVDS

MIPI and LVDS include high-speed differential pairs.When routing these signals, users should follow the general and common rules for differential pairs.Besides, there is no more special requirement.

7.4.6XCLK Requirement

ZA7783XCLK is supplied by the host chip.The frequency should be10~30MHz. If DVDD18is1.8V,the amplitude of XCLK should also be1.8V(waveform with low-level voltage0V and high-level voltage1.8V).

Please carefully check this amplitude requirement.Make sure that you have selected a correct clock output from the host chip.Especially note that some host chip clock pins only output500mV Vpp waveform or so,thus such clock outputs cannot be used as the source of ZA7783XCLK.

8Software Register Description

8.1Software Register Overview

The host chip(AP or BB)may access ZA7783’s software registers through I2C interface.The7-bit I2C Slave ID is0x37,and the following table lists all the software registers.

Table8-1Software Register Overview

https://www.wendangku.net/doc/781323030.html, Attr.Default Description

0x00GLOBAL_SW_RSTN RW0x00Global Software Reset

0x08PADO_DPI_OEN RW0x01DPI Related PAD Output Enable

0x10MIPI_PD RW0x3F MIPI PHY Power Down Control

0x11MIPI_DATLANE_RSTN RW0x00MIPI PHY Data Lane Reset Control

0x12MIPI_DATLANE_PN_EXCH RW0x00MIPI PHY Data Lane Dp/Dn Swap

0x13MIPI_DATLANE_ORDER RW0xE4MIPI PHY Data Lane Reorder

0x14TIME_CLK_SETTLE RW0x02MIPI PHY Clock Lane Timing

0x15TIME_D_TERM_EN RW0x02MIPI PHY Data Lane Timing1

0x16TIME_HS_SETTLE RW0x24MIPI PHY Data Lane Timing2

0x17MIPI_DITHER_EN RW0x00MIPI DSI RX Dither Enable

0x18MIPI_DLY_TRIM RW0x21MIPI DSI RX Delay Trim

0x20LVDS_PD RW0x3F LVDS PHY Power Down Control

0x21X7PLL_PD RW0xFF X7PLL Power Down Control

0x22LVDS_RSTN RW0x00LVDS PHY Reset Control

0x23LVDS_FIFO_EN RW0x00LVDS TX Enable

0x24LVDS_FORMAT RW0x00LVDS TX Format

0x25LVDS_DATLANE_PN_EXCH RW0x00LVDS PHY Data Lane Dp/Dn Swap

0x26LVDS_DATLANE_ORDER RW0xE4LVDS PHY Data Lane Reorder

0x27LVDS_DITHER_EN RW0x00LVDS TX Dither Enable

0x28LVDS_SSC RW0x28LVDS PHY SSC Control

0x29LVDS_PHY RW0x01LVDS PHY Trim

0x2A X7PLL_ADJ1RW0x00X7PLL Adjustment1

0x2B X7PLL_ADJ2RW0x01X7PLL Adjustment2

0x2C X7PLL_ADJ3RW0x0E X7PLL Adjustment3

0x2D X7PLL_ADJ4RW0x00X7PLL Adjustment4

0x2E X7PLL_ADJ5RW0x18X7PLL Adjustment5

0x2F X7PLL_ADJ6RW0x02X7PLL Adjustment6

0x30X7PLL_ADJ7RW0x02X7PLL Adjustment7

0x31LVDS_TEST RW0x00LVDS PHY Test Control

0x32LVDS_TDI RW0x63LVDS PHY Test Data In

0x33LVDS_TDO RO--LVDS PHY Test Data Out

0x34LVDS_TSO RO--LVDS PHY Test Result

0x35X7PLL_LOCK RO0x00X7PLL Lock Status

0x40PADI_DPI_ADJ RW0x00Adjust DPI from PAD inputs

0x41PADO_DPI_ADJ RW0x00Adjust DPI to PAD outputs

0x42LVDS_SOURCE RW0x00LVDS TX Source DPI Selection

8.2Software Register Description

8.2.1GLOBAL_SW_RSTN

Global Software Reset

ADDR=0x00(RW)

Bits Field Default Description

[7:1]Reserved

[0]sw_rstn1’b0reset all digital logic except i2c slave and software register,low active

8.2.2PADO_DPI_OEN

DPI Related PAD Output Enable

DPI Related PAD:PCLK,R7~R0,G7~G0,B7~B0,VSYNC,HSYNC,DATAEN

ADDR=0x08(RW)

Bits Field Default Description

[7:3]Reserved

[2]debug_mode21’b0switch to debug mode2:

R0=CK_FIFO from LVDS PHY

G0=LOCK from LVDS PHY

B0=TPSO from LVDS PHY

[1]debug_mode1’b0switch to debug mode:

PCLK=RC0_MIPI from MIPI D-PHY

VSYNC=RX_LPCLKOP from MIPI D-PHY

HSYNC=RX_LPCLKON from MIPI D-PHY

G[3:0]={RX0_LPDATAOP,RX0_LPDATAON,RD0_MIPI[1:0]}from

MIPI D-PHY

G[7:4]={RX1_LPDATAOP,RX1_LPDATAON,RD1_MIPI[1:0]}from

MIPI D-PHY

B[3:0]={RX2_LPDATAOP,RX2_LPDATAON,RD2_MIPI[1:0]}from

MIPI D-PHY

B[7:4]={RX3_LPDATAOP,RX3_LPDATAON,RD3_MIPI[1:0]}from

MIPI D-PHY

R[7:0]=byte_stream[7:0]after mipi dsi rx merger

DATAEN=byte_start indicator after mipi dsi rx merger

[0]pado_dpi_oen1’b1low active

8.2.3MIPI_PD

MIPI D-PHY Power Down Control

ADDR=0x10(RW)

Bits Field Default Description

[7:6]Reserved

[5]pd_bias1’b1power down bias,high active

[4]rx_clkpd1’b1power down clock lane,high active

[3]rx3_datapd1’b1power down data lane3,high active

[2]rx2_datapd1’b1power down data lane2,high active

[1]rx1_datapd1’b1power down data lane1,high active

[0]rx0_datapd1’b1power down data lane0,high active

8.2.4MIPI_DATLANE_RSTN

MIPI D-PHY Data Lane Reset Control

ADDR=0x11(RW)

Bits Field Default Description

[7:4]Reserved

[3]rx3_resetn1’b0reset data lane3,low active

[2]rx2_resetn1’b0reset data lane2,low active

[1]rx1_resetn1’b0reset data lane1,low active

[0]rx0_resetn1’b0reset data lane0,low active

8.2.5MIPI_DATLANE_PN_EXCH

MIPI D-PHY Data Lane Dp/Dn Exchange

ADDR=0x12(RW)

Bits Field Default Description

[7:4]Reserved

[3]rx3_pn_exch1’b0exchange data lane3Dp/Dn,high active

[2]rx2_pn_exch1’b0exchange data lane2Dp/Dn,high active

[1]rx1_pn_exch1’b0exchange data lane1Dp/Dn,high active

[0]rx0_pn_exch1’b0exchange data lane0Dp/Dn,high active

8.2.6MIPI_DATLANE_ORDER

MIPI D-PHY Data Lane Reorder

ADDR=0x13(RW)

Bits Field Default Description [7:6]sel_4th_datlane2’h3the4th data lane is from

2'h0:data lane0

2'h1:data lane1

2'h2:data lane2

2'h3:data lane3

[5:4]sel_3rd_datlane2’h2the3rd data lane is from

2'h0:data lane0

2'h1:data lane1

2'h2:data lane2

2'h3:data lane3

[3:2]sel_2nd_datlane2’h1the2nd data lane is from

2'h0:data lane0

2'h1:data lane1

2'h2:data lane2

2'h3:data lane3

[1:0]sel_1st_datlane2’h0the1st data lane is from

2'h0:data lane0

2'h1:data lane1

2'h2:data lane2

2'h3:data lane3

8.2.7TIME_CLK_SETTLE

MIPI D-PHY Clock Lane Timing Parameter:TIME_CLK_SETTLE

ADDR=0x14(RW)

Bits Field Default Description

[7:4]Reserved

[3:0]time_clk_settle4'h2time interval during which the HS receiver shall ignore any Clock

Lane HS transitions,starting from the beginning of LP-00state.

this time interval is counted based on xclk,and should be within

[95ns,300ns]

8.2.8TIME_D_TERM_EN

MIPI D-PHY Data Lane Timing Parameter:TIME_D_TERM_EN

ADDR=0x15(RW)

Bits Field Default Description

[7:4]Reserved

[3:0]time_d_term_en4'h2time for the Data Lane receiver to enable the HS line termination,

starting from the time point when Dn crosses Vil,max.this time

interval is counted based on hs_clk(high-speed clock received

from Clock Lane),and should be within[time for Dn to reach

Vterm-en,35ns+4*UI](UI=hs_clk/2).

8.2.9TIME_HS_SETTLE

MIPI D-PHY Data Lane Timing Parameter:TIME_HS_SETTLE

ADDR=0x16(RW)

Bits Field Default Description

[7:6]Reserved

[5:0]time_hs_settle6'h24time interval during which the HS receiver shall ignore any Data

Lane HS transitions,starting from the beginning of LP-00state.

this time interval is counted based on hs_clk(high-speed clock

received from Clock Lane),and should be within[85ns+6*UI,

145ns+10*UI](UI=hs_clk/2).

8.2.10MIPI_DITHER_EN

MIPI DSI RX RGB888->RGB666Dither Enable

ADDR=0x17(RW)

Bits Field Default Description

[7:1]Reserved

[0]mipi_dither_en1'b0high active

8.2.11MIPI_DLY_TRIM

MIPI DSI RX HSA and HBP Delay Trim

ADDR=0x18(RW)

Bits Field Default Description

[7:4]hbp_delay4'b0010please refer to timing diagram.one and only one bit should be1'b1.

hbp_delay[0]=1'b1:no delay

hbp_delay[1]=1'b1:3-byte delay