AD7521LN中文资料

TL H 5689DAC1020 DAC1021 DAC102210-Bit Binary Multiplying D A Converter DAC1220 DAC122212-Bit Binary Multiplying D A Converter

May 1996

DAC1020 DAC1021 DAC1022

10-Bit Binary Multiplying D A Converter DAC1220 DAC1222

12-Bit Binary Multiplying D A Converter

General Description

The DAC1020and the DAC1220are respectively 10and 12-bit binary multiplying digital-to-analog converters A de-posited thin film R-2R resistor ladder divides the reference current and provides the circuit with excellent temperature tracking characteristics (0 0002% C linearity error temper-ature coefficient maximum) The circuit uses CMOS current switches and drive circuitry to achieve low power consump-tion (30mW max)and low output leakages (200nA max) The digital inputs are compatible with DTL TTL logic levels as well as full CMOS logic level swings This part combined with an external amplifier and voltage reference can be used as a standard D A converter however it is also very attractive for multiplying applications (such as digitally con-trolled gain blocks)since its linearity error is essentially in-dependent of the voltage reference All inputs are protected from damage due to static discharge by diode clamps to V a and ground

This part is available with 10-bit (0 05%) 9-bit (0 10%) and 8-bit (0 20%)non-linearity guaranteed over temperature

(note 1of electrical characteristics) The DAC1020 DAC1021and DAC1022are direct replacements for the 10-bit resolution AD7520and AD7530and equivalent to the AD7533family The DAC1220and DAC1222are direct re-placements for the 12-bit resolution AD7521and AD7531family

Features

Y Linearity specified with zero and full-scale adjust only Y Non-linearity guaranteed over temperature Y Integrated thin film on CMOS structure Y 10-bit or 12-bit resolution

Y Low power dissipation 10mW 15V typ

Y Accepts variable or fixed reference b 25V s V REF s 25V Y 4-quadrant multiplying capability

Y Interfaces directly with DTL TTL and CMOS Y Fast settling time 500ns typ

Y

Low feedthrough error LSB 100kHz typ

Equivalent Circuit

Note Switches shown in digital high state

TL H 5689–1

10-BIT D A CONVERTERS

Ordering Information

Temperature Range 0 C to 70 C b 40 C to 85 C

Non-0 05%DAC1020LCN AD7520LN AD7530LN DAC1020LCV DAC1020LIV

Linearity

0 10%DAC1021LCN AD7520KN AD7530KN 0 20%

DAC1022LCN

AD7520JN AD7530JN Package Outline N16A

V20A

12-BIT D A CONVERTERS Temperature Range 0 C to 70 C

b 40 C to a 85 C

Linearity

Non-0 05%DAC1220LCN AD7521LN AD7531LN DAC1220LCJ AD7521LD AD7531LD 0 20%

DAC1222LCN

AD7521JN AD7531JN DAC1222LCJ

AD7521JD AD7531JD Package Outline

N18A

J18A

Note Devices may be ordered by either part number

C 1996National Semiconductor Corporation RRD-B30M96 Printed in U S A

http www national com

Absolute Maximum Ratings(Note5)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications V a to Gnd17V V REF to Gnd g25V Digital Input Voltage Range V a to Gnd DC Voltage at Pin1or Pin2(Note3)b100mV to V a Storage Temperature Range b65 C to a150 C Lead Temperature(Soldering 10sec )

Dual-In-Line Package(plastic)260 C Dual-In-Line Package(ceramic)300 C ESD Susceptibility(Note4)800V Operating Ratings

Min Max Units Temperature(T A)

DAC1020LIV DAC1220LCJ

DAC1222LCJ b40a85 C DAC1020LCN DAC1020LCV

DAC1021LCN0a70 C DAC1022LCN DAC1220LCN0a70 C DAC1222LCN0a70 C

Electrical Characteristics(V a e15V V REF e10 000V T A e25 C unless otherwise specified)

DAC1020 DAC1021

DAC1220 DAC1222 Parameter Conditions DAC1022Units

Min Typ Max Min Typ Max

Resolution1012Bits

Linearity Error T MIN k T A k T MAX

b10V k V REF k a10V

(Note1)End Point Adjustment Only

(See Linearity Error in Definition of Terms)

10-Bit Parts DAC1020 DAC12200 050 05%FSR 9-Bit Parts DAC10210 100 10%FSR 8-Bit Parts DAC1022 DAC12220 200 20%FSR Linearity Error Tempco b10V s V REF s a10V 0 00020 0002%FS C (Notes1and2)

Full-Scale Error b10V s V REF s a10V 0 31 00 31 0%FS (Notes1and2)

Full-Scale Error Tempco T MIN k T A k T MAX 0 0010 001%FS C (Note2)

Output Leakage Current T MIN s T A s T MAX

I OUT1All Digital Inputs Low200200nA

I OUT2All Digital Inputs High200200nA

Power Supply Sensitivity All Digital Inputs High 0 0050 005%FS V 14V s V a s16V (Note2)

(Figure2)

V REF Input Resistance101520101520k X

Full-Scale Current Settling R L e100X from0to99 95%

Time FS

All Digital Inputs Switched500500ns

Simultaneously

V REF Feedthrough All Digital Inputs Low 1010mVp-p V REF e20Vp-p 100kHz

J Package(Note4)6969mVp-p

N Package2525mVp-p

Output Capacitance

I OUT1All Digital Inputs Low4040pF

All Digital Inputs High200200pF

I OUT2All Digital Inputs Low200200pF

All Digital Inputs High4040pF http www national com2

Electrical Characteristics(V a e15V V REF e10 000V T A e25 C unless otherwise specified)(Continued)

DAC1020 DAC1021

DAC1220 DAC1222 Parameter Conditions DAC1022Units

Min Typ Max Min Typ Max

Digital Input(Figure1)

Low Threshold T MIN k T A k T MAX0 80 8V

High Threshold T MIN k T A k T MAX2 42 4V

Digital Input Current T MIN s T A s T MAX

Digital Input High11001100m A

Digital Input Low b50b200b50b200m A

Supply Current All Digital Inputs High0 21 60 21 6mA

All Digital Inputs Low0 620 62mA

Operating Power Supply(Figures1and2)515515V Range

Note1 V REF e g10V and V REF e g1V A linearity error temperature coefficient of0 0002%FS for a45 C rise only guarantees0 009%maximum change in linearity error For instance if the linearity error at25 C is0 045%FS it could increase to0 054%at70 C and the DAC will be no longer a10-bit part Note however that the linearity error is specified over the device full temperature range which is a more stringent specification since it includes the linearity error temperature coefficient

Note2 Using internal feedback resistor as shown in Figure3

Note3 Both I OUT1and I OUT2must go to ground or the virtual ground of an operational amplifier If V REF e10V every millivolt offset between I OUT1or I OUT2

0 005%linearity error will be introduced

Note4 Human body model 100pF discharged through a1 5k X resistor

Note5 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions

Note6 The maximum power dissipation must be derated at elevated temperatures and is dictated by T JMAX i JA and the ambient temepature T A The maximum allowable power dissipation at any temperature is P D e(T JMAX b T A) i JA or the number given in the Absolute Maximum Ratings whichever is lower For this device T JMAX e125 C and the typical junction-to-ambient thermal resistance of the J18package when board mounted is85 C W For the N18package i JA is 120 C W for the N16this number is125 C W and for the V20this number is95 C W

Typical Performance Characteristics

TL H 5689–2

FIGURE2 Gain Error Variation vs V a FIGURE1 Digital Input Threshold vs

Ambient Temperature

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Typical Applications

The following applications are also valid for12-bit systems using the DAC1220and2additional digital inputs Operational Amplifier Bias Current(Figure3)

The op amp bias current I b flows through the15k internal feedback resistor BI-FET op amps have low I b and there-fore the15k c I b error they introduce is negligible they are strongly recommended for the DAC1020applications

V OS Considerations

The output impedance R OUT of the DAC is modulated by the digital input code which causes a modulation of the op-erational amplifier output offset It is therefore recommend-ed to adjust the op amp V OS R OUT is E15k if more than4 digital inputs are high R OUT is E45k if a single digital input is high and R OUT approaches infinity if all inputs are low Operational Amplifier V OS Adjust(Figure3)

Connect all digital inputs A1–A10 to ground and adjust the potentiometer to bring the op amp V OUT pin to within g1 mV from ground potential If V REF is less than10V a finer V OS adjustment is required It is helpful to increase the reso-lution of the V OS adjust procedure by connecting a1k X resistor between the inverting input of the op amp to ground After V OS has been adjusted remove the1k X Full-Scale Adjust(Figure4)

Switch high all the digital inputs A1–A10 and measure the op amp output voltage Use a500X potentiometer as shown to bring ll V OUT ll to a voltage equal to V REF c 1023 1024

SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER

Op Amp Family C F R i P V W Circuit Settling Circuit Small Time t s Signal BW

LF35710pF2 4k25k V a1 5m s1M LF35622pF%25k V a3m s0 5M LF35124pF%10k V b4m s0 5M LM7410%10k V b40m s200kHz

TL H 5689–3

V OUT e b V REF A12a A24a A38a A101024J

b10V s V REF s10V

0s V OUT s b 1023 1024

V REF

where A N e1if the A N digital input is high

A N e0if the A N digital input is low

FIGURE3 Basic Connection Unipolar or2-Quadrant Multiplying

Configuration(Digital Attenuator)

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Typical Applications(Continued)

FIGURE4 Full-Scale Adjust

FIGURE5 Alternate Full-Scale Adjust (Allows Increasing or Decreasing the Gain)

TL H 5689–4

V OUT1e b V REF A12a A24a A38a A101024J

V OUT2e V REF A12a A24a A38a A101024J c B12a B24a B38a B101024J

where V REF can be an AC signal

FIGURE6 Precision Analog-to-Digital Multiplier

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Typical Applications (Continued)

TL H 5689–5

V OUT e b V REF

A1

2

a

A24a a A101024b 1

1024

J

where AN e a 1if A N input is high

AN e b 1if A N input is low

COMPLEMENTARY OFFSET BINARY

(BIPOLAR)OPERATION DIGITAL INPUT V OUT

0000000000

a V REF 0000000001V REF c 1022 1024

0111111111V REF c 2 102410000000000

1000000001b V REF c 2 1024111111111

1b V REF (1022 1024)

Note that

I OUT 1a I OUT 2e

V REF

R LADDER c

1023

1024

J

By doubling the output range we get half the resolution

The 10M resistor adds a 1LSB ‘‘thump’’ to

allow full offset binary operation where the out-put reaches zero for the half-scale code If

symmetrical output excursions are required omit the 10M resistor

FIGURE 7 Bipolar 4-Quadrant Multiplying Configuration

Operational Amplifiers V OS Adjust (Figure 7)a)

Switch all the digital inputs high adjust the V OS potenti-ometer of op amp B to bring its output to a value equal to b (V REF 1024)(V)

b)

Switch the MSB high and the remaining digital inputs low Adjust the V OS potentiometer of op amp A to bring its output value to within a 1mV from ground potential For V REF k 10V a finer adjust is necessary as already mentioned in the previous application

Gain Adjust (Full-Scale Adjust)

Assuming that the external 10k resistors are matched to better than 0 1% the gain adjust of the circuit is the same with the one previously discussed

TL H 5689–6

TRUE OFFSET BINARY OPERATION DIGITAL INPUT

V OUT

1111111111V REF c 1022 1024

100000000000

b V REF

t s e 1 8m s

use LM336for a voltage reference

FIGURE 8 Bipolar Configuration with a Single Op Amp

R4e (2A V b b

1)R R2R1e A V b A V b b 1

R3a R1ll R2e R A V b e V OUT(PEAK)

V REF

R e 20k

Example V REF e 2V V OUT (swing)j g 10V A V b e 5V Then R4e 9R R1e 0 8R2 If R1e 0 2R then R2e 0 25R R3e 0 64R

FIGURE 9 Bipolar Configuration with

Increased Output Swing

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Typical Applications(Continued)

V OUT e

b V REF

A12a A24a A38a A101024J

where V REF can be an AC signal

By connecting the DAC in the feedback loop of an opera-

tional amplifier a linear digitally control gain block can be

realized

Note that with all digital inputs low the gain of the amplifier

is infinity that is the op amp will saturate In other words we

cannot divide the V REF by zero

FIGURE10 Analog-to-Digital Divider(or Digitally Gain Controlled Amplifier)

V OUT e V REF

%A1

2

a

A2

4

a a

A10

1024

A1

2

a

A2

4

a a

A10

1024–

or V OUT e V REF 1023b N N J

where 0s N s1023

N e0for A N e all zeros

N e1for A10e1 A1–A9e0

N e1023for A N e all1’s

FIGURE11 Digitally controlled Amplifier-Attenuator

TL H 5689–7

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Typical Applications (Continued)

TL H 5689–8

Output frequency e f CLK

512

f MAX j 2kHz Output voltage range e 0V b 10V peak THD k 0 2%

Excellent amplitude and frequency stability with temperature

Low pass filter shown has a 1kHz corner (for output frequencies below 10Hz filter corner should be reduced) Any periodic function can be implemented by modifying the contents of the look up table ROM

No start up problems

FIGURE 12 Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM

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Typical Applications(Continued)

MM74C00 NAND gates

MM74C32 OR gates

MM74C74 D flip-flop

MM74C193 Binary up

down counters

TL H 5689–9

Binary up down counter digitally‘‘ramps’’the DAC

output

Can stop counting at any desired10-bit input code

Senses up or down count overflow and automatically

reverses direction of count

FIGURE13 A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits

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Definition of Terms

Resolution Resolution is defined as the reciprocal of the number of discrete steps in the D A output It is directly related to the number of switches or bits within the D A For example the DAC1020has 210or 1024steps while the DAC1220has 212or 4096steps Therefore the DAC1020has 10-bit resolution while the DAC1220has 12-bit resolu-tion

Linearity Error Linearity error is the maximum deviation from a straight line passing through the endpoints of the D A transfer characteristic It is measured after calibrating for zero (see V OS adjust in typical applications)and full-scale Linearity error is a design parameter intrinsic to the device and cannot be externally adjusted

Power Supply Sensitivity Power supply sensitivity is a measure of the effect of power supply changes on the D A full-scale output

Settling Time Full-scale settling time requires a zero to full-scale or full-scale to zero output change Settling time is the time required from a code transition until the D A output reaches within g LSB of final output value

Full-Scale Error Full-scale error is a measure of the output error between an ideal D A and the actual device output Ideally for the DAC1020full-scale is V REF b 1LSB For V REF e 10V and unipolar operation V FULL-SCA-LE e 10 0000V 9 8mV e 9 9902V Full-scale error is ad-justable to zero as shown in Figure 5

TL H 5689–10

a

b1

b2

(a)End point test after zero and full-scale adjust The DAC has 1LSB linearity error

(b)By shifting the full-scale calibration on of the DAC of

Figure (b1)we could pass the ‘‘best straight line’’(b2)test and meet the g linearity error specification

Note (a) (b1)and (b2)above illustrate the difference between ‘‘end point’’National’s linearity test (a)and ‘‘best straight line’’test Note that both devices in (a)and (b2)meet the g LSB linearity error specification but the end point test is a more ‘‘real life’’way of characterizing the DAC

Connection Diagrams

DAC102X

Dual-In-Line Package

TL H 5689–13

DAC1020PLCC Package

TL H 5689–12

DAC122X

Dual-In-Line Package

TL H 5689–11

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Physical Dimensions inches(millimeters)unless otherwise noted

Cavity Dual-In-Line Package(J)

Order Number DAC1220LCJ or DAC1222LCJ

NS Package Number J18A

Molded Dual-In-Line Package(N)

Order Number DAC1020LCN DAC1021LCN or DAC1022LCN

NS Package Number N16A

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Physical Dimensions inches(millimeters)unless otherwise noted(Continued)

Molded Dual-In-Line Package(N)

Order Number DAC1220LCN DAC1221LCN or DAC1222LCN

NS Package Number N18A

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D A C 1020 D A C 1021 D A C 102210-B i t B i n a r y M u l t i p l y i n g D A C o n v e r t e r D A C 1220 D A C 122212-B i t B i n a r y M u l t i p l y i n g D A C o n v e r t e r

Physical Dimensions inches (millimeters)unless otherwise noted (Continued)

Molded Plastic Leaded Chip Carrier (V)Order Number DAC1020LCV or DAC1020LIV

NS Package Number V20A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness

be reasonably expected to result in a significant injury to the user

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