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IS61LF12836A-7.5B2中文资料

ISSI

IS61(64)LF12832A IS64VF12832A IS61(64)LF12836A IS61(64)VF12836A IS61(64)LF25618A IS61(64)VF25618A Copyright ? 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to FEATURES

?Internal self-timed write cycle

?Individual Byte Write Control and Global Write ?Clock controlled, registered address, data and control ?Burst sequence control using MODE input ?Three chip enable option for simple depth expan-sion and address pipelining ?Common data inputs and data outputs ?Auto Power-down during deselect ?Single cycle deselect

?Snooze MODE for reduced-power standby ?Power Supply

LF: V DD 3.3V + 5%, V DDQ 3.3V/2.5V + 5%VF: V DD 2.5V -5% +10%, V DDQ 2.5V -5% +10%?JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-pin PBGA packages ?Automotive temperature available ?Lead-free available

PRELIMINARY INFORMATION

AUGUST 2005

128K x 32, 128K x 36, 256K x 18

4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

DESCRIPTION

The ISSI IS61(64)LF12832A, IS64VF12832A,

IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for commu-nication and networking applications. The IS61(64)LF12832A is organized as 131,072 words by 32bits. The IS61(64)LF/VF12836A is organized as 131,072words by 36 bits. The IS61(64)LF/VF25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI 's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All syn-chronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written.Byte write operation is performed by using byte write enable (BWE ) input combined with one or more individual byte write signals (BWx ). In addition, Global Write (GW ) is available for writing all bytes at one time, regardless of the byte write controls.

Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller)input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address ad-vance) input pin.

The mode pin is used to select the burst sequence order,Linear burst is achieved when this pin is tied LOW.Interleave burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol Parameter

-6.5-7.5Units t KQ Clock Access Time 6.57.5ns t KC

Cycle Time 7.58.5ns Frequency

133

117

MHz

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

BLOCK DIAGRAM

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

165-PIN BGA

165-Ball, 13x15 mm BGA

119-PIN BGA

119-Ball, 14x22 mm BGA

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

119 BGA PACKAGE PIN CONFIGURATION 128K X 36 (TOP VIEW)

PIN DESCRIPTIONS

23456

A V DDQ A A ADSP A A V DDQ

B N

C CE2A ADSC A CE2 NC C NC A A V D

D A A NC D DQc DQPc Vss NC Vss DQPb DQb

E DQc DQc Vss CE Vss DQb DQb

F V DDQ DQc Vss OE Vss DQb V DDQ

G DQc DQc BWc ADV BWb DQb DQb

H DQc DQc Vss GW Vss DQb DQb J V DDQ V DD NC V DD NC V DD V DDQ K DQd DQd Vss CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M V DDQ DQd Vss BWE Vss DQa V DDQ N DQd DQd Vss A 1*Vss DQa DQa P DQd DQPd Vss A 0*Vss DQPa DQa R NC A MODE V DD NC A NC T NC NC A A A NC ZZ U

V DDQ

NC V DDQ Symbol

Pin Name

A Address Inputs

A0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance

ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock

CE , CE2, CE2Synchronous Chip Select

BW x (x=a-d)Synchronous Byte Write Controls BWE

Byte Write Enable

Symbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply V DD Power Supply V DDQ Output Power Supply Vss

Ground

Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

119 BGA PACKAGE PIN CONFIGURATION 256K X 18 (TOP VIEW)

PIN DESCRIPTIONS

Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.1

23456

A V DDQ A A ADSP A A

V DDQ B NC CE2A ADSC A CE2 NC C NC A A V DD A A NC D DQb NC Vss NC Vss DQPa NC E NC DQb Vss CE Vss NC DQa F V DDQ NC Vss OE Vss DQa V DDQ G NC DQb BWb ADV Vss NC DQa H DQb NC Vss GW Vss DQa NC J V DDQ V DD NC V DD NC V DD V DDQ K NC DQb Vss CLK Vss NC DQa L DQb NC Vss NC BWa DQa NC M V DDQ DQb Vss BWE Vss NC V DDQ N DQb NC Vss A 1*Vss DQa NC P NC DQPb Vss A 0*Vss NC DQa R NC A MODE V DD NC A NC T NC A A NC A A ZZ U

V DDQ

NC V DDQ Symbol Pin Name

A Address Inputs

A0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance

ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK

Synchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a,b)Synchronous Byte Write Controls BWE

Byte Write Enable

Symbol Pin Name OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Output Power Supply V DD Power Supply V DDQ Output Power Supply Vss

Ground

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

PIN DESCRIPTIONS

165 PBGA PACKAGE PIN CONFIGURATION

128K X 36 (TOP VIEW)

Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

1234567891011A NC A CE BWc BWb CE2BWE ADSC ADV A NC B NC A CE2BWd BWa CLK GW OE ADSP A NC C DQPc NC V DDQ Vss Vss Vss Vss Vss V DDQ NC DQPb

D DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQb

E DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQb

F DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQb

G DQc DQc V DDQ V DD Vss Vss Vss V DD V DDQ DQb DQb

H NC NC NC V DD Vss Vss Vss V DD NC NC ZZ J DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa K DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa L DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa M DQd DQd V DDQ V DD Vss Vss Vss V DD V DDQ DQa DQa N DQPd NC V DDQ Vss NC NC NC Vss V DDQ NC DQPa

P NC NC A A NC A 1*NC A A A NC R

MODE

A 0*

Symbol Pin Name

A Address Inputs

A0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance

ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK

Synchronous Clock CE , CE2, CE2

Synchronous Chip Select

BW x (x=a,b,c,d)Synchronous Byte Write

Controls

Symbol Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect

DQx Data Inputs/Outputs DQPx Data Inputs/Outputs V DD 3.3V/2.5V Power Supply

V DDQ

Isolated Output Power Supply 3.3V /2.5V Vss

Ground

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

Note: * A 0 and A 1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

165 PBGA PACKAGE PIN CONFIGURATION

256K X 18 (TOP VIEW)

PIN DESCRIPTIONS

234567891011A NC A CE BWb NC CE2BWE ADSC ADV A A B NC A CE2NC BWa CLK GW OE ADSP A NC C NC NC V DDQ Vss Vss Vss Vss Vss V DDQ NC DQPa D NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa E NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa F NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa G NC DQb V DDQ V DD Vss Vss Vss V DD V DDQ NC DQa H NC NC NC V DD Vss Vss Vss V DD NC NC ZZ J DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC K DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC L DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC M DQb NC V DDQ V DD Vss Vss Vss V DD V DDQ DQa NC N DQPb NC V DDQ Vss NC NC NC Vss V DDQ NC NC P NC NC A A NC A 1*NC A A A NC R

MODE

A 0*

Symbol Pin Name

A Address Inputs

A0, A1Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance

ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK

Synchronous Clock CE , CE2, CE2Synchronous Chip Select BW x (x=a,b)

Synchronous Byte Write Controls

Symbol Pin Name

BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect

DQx Data Inputs/Outputs DQPx Data Inputs/Outputs V DD 3.3V/2.5V Power Supply

V DDQ

Isolated Output Power Supply 3.3V/2.5V Vss

Ground

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus.

A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa -BWd Synchronous Byte Write Enable BWE

Synchronous Byte Write Enable

CE , CE2, CE2Synchronous Chip Enable CLK

Synchronous Clock

DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output

GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable

V DD 3.3V/2.5V Power Supply V DDQ Isolated Output Buffer Supply:3.3V/2.5V Vss Ground ZZ

Snooze Enable

PIN CONFIGURATION

100-PIN TQFP (128K x 36)

100-PIN TQFP (128K x 32)

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

PIN CONFIGURATION

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus.

A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa -BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE , CE2, CE2Synchronous Chip Enable

CLK Synchronous Clock

DQa-DQb

Synchronous Data Input/Output

DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable

V DD 3.3V/2.5V Power Supply V DDQ Isolated Output Buffer Supply:3.3V/2.5V Vss Ground ZZ

Snooze Enable

100-PIN TQFP (256K x 18)

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

PARTIAL TRUTH TABLE

Function GW BWE BWa BWb BWc BWd Read H H X X X X Read

H L H H H H Write Byte 1H L L H H H Write All Bytes H L L L L L TRUTH TABLE (1-8)

OPERATION

ADDRESS CE CE2CE2ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst

Current

L-H

NOTE:

1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2.For WRITE , L means one or more byte write enable signals (BWa-d ) and BWE are LOW or GW is LOW. WRITE = H for all BWx , BWE , GW HIGH.

3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version.DQPa-DQPd are available on the x36 version.

4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5.Wait states are inserted by suspending burst.

6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time.

7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

INTERLEAVED BURST ADDRESS TABLE (MODE = V DD or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1A0

00011011010011101011000111

LINEAR BURST ADDRESS TABLE (MODE = VSS)

ABSOLUTE MAXIMUM RATINGS (1)

Symbol Parameter

Value Unit T STG Storage Temperature –55 to +150°C

P D Power Dissipation

1.6W I OUT

Output Current (per I/O)

100mA

V IN , V OUT Voltage Relative to Vss for I/O Pins –0.5 to V DDQ + 0.5V V IN Voltage Relative to Vss for –0.5 to V DD + 0.5V

for Address and Control Inputs V DD

Voltage on V DD Supply Relative to Vss

–0.5 to 4.6

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

3.3V

2.5V

Symbol Parameter Test Conditions Min.Max.Min.Max.Unit V OH Output HIGH Voltage I OH = –4.0 mA (3.3V) 2.4— 2.0—V I OH = –1.0 mA (2.5V)V OL Output LOW Voltage I OL = 8.0 mA (3.3V)—0.4—0.4V I OL = 1.0 mA (2.5V)

V IH Input HIGH Voltage 2.0V DD + 0.3 1.7V DD + 0.3V V IL Input LOW Voltage –0.30.8–0.30.7V I LI Input Leakage Current V SS ≤ V IN ≤ V DD (1)

–55–55μA I LO

Output Leakage Current

V SS ≤ V OUT ≤ V DDQ , OE = V IH –5

–5

μA

OPERATING RANGE (IS61/64LFxxxxx)

Range

Ambient Temperature

V DD

V DDQ

Commercial 0°C to +70°C 3.3V ± 5% 3.3V/2.5V ± 5%Industrial -40°C to +85°C 3.3V ± 5% 3.3V/2.5V ± 5%Automotive

-40°C to +125°C

3.3V ± 5%

3.3V/2.5V ± 5%

OPERATING RANGE (IS61/64VFxxxxx)

Range

Ambient Temperature

V DD

V DDQ

Commercial 0°C to +70°C 2.5V -5% +10% 2.5V -5% +10%Industrial -40°C to +85°C 2.5V -5% +10% 2.5V -5% +10%Automotive

-40°C to +125°C

2.5V -5% +10%

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range)

6.5

7.5 MAX

MAX

Symbol Parameter Test Conditions Temp. range

x18x32/x36x18x32/x36Uni t I CC

AC Operating Device Selected,Com.175175155155mA

Supply Current

OE = V IH , ZZ ≤ V IL ,

Ind.180180160160 All Inputs ≤ 0.2V or ≥ V DD – 0.2V,A UTO .190190175175Cycle Time ≥ t KC min.typ.(2) 120 110

I SB

Standby Current Device Deselected,Com.90909090mA

TTL Input

V DD = Max.,

Ind.100100100100All Inputs ≤ V IL or ≥ V IH ,Auto.120

120

ZZ ≤ V IL , f = Max.

I SBI

Standby Current Device Deselected,Com.70707070mA

CMOS Input

V DD = Max.,

Ind.75757575V IN ≤ V SS + 0.2V or ≥V DD – 0.2V Auto.90909090 f = 0typ. 40 40I SB 2Sleep Mode ZZ>V IH

Com.30303030mA

Ind.35353535Auto.45454545typ.

Note:

1.MODE pin has an internal pullup and should be tied to V DD or V SS . It exhibits ±100 μA maximum leakage current when tied to ≤V SS + 0.2V or ≥ V DD – 0.2V.

2. Typical values are measured at V DD =

3.3V, T A = 25o C and not 100% tested.

CAPACITANCE (1,2)

Symbol Parameter Conditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUT

Input/Output Capacitance

V OUT = 0V

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.

2.Test conditions: T A = 25°C, f = 1 MHz, V DD =

3.3V.

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

3.3V I/O AC TEST CONDITIONS

Parameter

Unit Input Pulse Level

0V to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V and Reference Level Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 2

Figure 1

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

2.5V I/O AC TEST CONDITIONS

Parameter

Unit Input Pulse Level

0V to 2.5V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.25V and Reference Level Output Load

See Figures 3 and 4

Figure 3Figure 4

2.5V I/O OUTPUT LOAD EQUIVALENT

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (1) (Over Operating Range)

6.5

7.5

Symbol Parameter Min.Max.Min.Max.Unit fmax Clock Frequency —133—117MHz t KC Cycle Time 7.5—8.5—ns t KH Clock High Time 2.2— 2.5—ns t KL Clock Low Time 2.2— 2.5—ns t KQ Clock Access Time — 6.5—7.5ns t KQX (2)Clock High to Output Invalid 2.5— 2.5—ns t KQLZ (2,3)Clock High to Output Low-Z 2.5— 2.5—ns t KQHZ (2,3)Clock High to Output High-Z — 3.8— 4.0ns t OEQ Output Enable to Output Valid — 3.2— 3.4ns t OEQX (2)Output Enable to Output Invalid 2.5— 2.5—ns t OELZ (2,3)Output Enable to Output Low-Z 0—0—ns t OEHZ (2,3)Output Disable to Output High-Z — 3.5— 3.5ns t AS Address Setup Time 1.5— 1.5—ns t WS Read/Write Setup Time 1.5— 1.5—ns t CES Chip Enable Setup Time 1.5— 1.5—ns t AVS Address Advance Setup Time 1.5— 1.5—ns t DS Data Setup Time 1.5— 1.5—ns t AH Address Hold Time 0.5—0.5—ns t WH Write Hold Time 0.5—0.5—ns t CEH Chip Enable Hold Time 0.5—0.5—ns t AVH Address Advance Hold Time 0.5—0.5—ns t DH Data Hold Time 0.5—0.5—ns t PDS ZZ High to Power Down —2—2cyc t PUS ZZ Low to Power Down

—

cyc

Notes:

1.Configuration signal MODE is static and must not change during normal operation.

2.Guaranteed but not 100% tested. This parameter is periodically sampled.

3.Tested with load in Figure 2.

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

READ/WRITE CYCLE TIMING

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

WRITE CYCLE TIMING

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

SNOOZE MODE TIMING

SNOOZE MODE ELECTRICAL CHARACTERISTICS

Symbol Parameter

Conditions Min.Max.Unit I SB 2Current during SNOOZE MODE ZZ ≥ Vih

—60mA t PDS ZZ active to input ignored —2cycle t PUS ZZ inactive to input sampled 2—cycle t ZZI ZZ active to SNOOZE current —2cycle t RZZI

ZZ inactive to exit SNOOZE current

—

ISSI

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

ORDERING INFORMATION (V DD = 3.3V/V DDQ = 2.5V/3.3V)Commercial Range: 0°C to +70°C

Configuration Access Time

Order Part Number Package 128Kx32

6.5

IS61LF12832A-6.5TQ 100 TQFP IS61LF12832A-6.5B2119 PBGA IS61LF12832A-6.5B3165 PBGA 128Kx327.5

IS61LF12832A-7.5TQ 100 TQFP IS61LF12832A-7.5B2119 PBGA IS61LF12832A-7.5B3

165 PBGA 128Kx36

6.5

IS61LF12836A-6.5TQ 100 TQFP IS61LF12836A-6.5B2119 PBGA IS61LF12836A-6.5B3165 PBGA 128Kx367.5

IS61LF12836A-7.5TQ 100 TQFP IS61LF12836A-7.5B2119 PBGA IS61LF12836A-7.5B3

165 PBGA 256Kx18

6.5

IS61LF25618A-6.5TQ 100 TQFP IS61LF25618A-6.5B2119 PBGA IS61LF25618A-6.5B3165 PBGA 256Kx187.5

IS61LF25618A-7.5TQ 100 TQFP IS61LF25618A-7.5B2119 PBGA IS61LF25618A-7.5B3

165 PBGA