当前位置：文档库 › TISP5080H3BJR-S中文资料

TISP5080H3BJR-S中文资料

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005

Description

Low Voltage Overshoot under Surge

Rated for International Surge Wave Shapes

Device Symbol

These devices are designed to limit overvoltages on the telephone and data lines. Overvoltages are normally caused by a.c. power system or lightning flash disturbances which are induced or conducted on to the telephone line. A single device provides 2-point protection and is

typically used for the protection of ISDN power supply feeds. T wo devices, one for the Ring output and the other for the Tip output, will provide protection for single supply analogue SLICs. A combination of three devices will give a low capacitance protector network for the 3-point protection of ISDN lines.

The protector consists of a voltage-triggered unidirectional thyristor with an anti-parallel diode. Negative overvoltages are initially clipped by breakdown clamping until the voltage rises to the breakover level, which causes the device to crowbar into a low-voltage on state. This low-voltage on state causes the current resulting from the overvoltage to be safely diverted through the device. The high crowbar holding current prevents d.c. latchup as the diverted current subsides. Positive overvoltages are limited by the conduction of the anti-parallel diode.

UL Recognized Component

Device Name V DRM V V (BO)V TISP5070H3BJ -58-70TISP5080H3BJ -65-80TISP5095H3BJ -75-95TISP5110H3BJ -80-110TISP5115H3BJ -90-115TISP5150H3BJ -120-150TISP5190H3BJ

-160

-190

Wave Shape

Standard I PPSM A 2/10GR-1089-CORE 5008/20ANSI C62.4130010/160TIA-968-A 25010/700ITU-T K.20/21/45

20010/560TIA-968-A 16010/1000

GR-1089-CORE

100

*RoHS Directive 2002/95/EC Jan 27 2003 including Annex *R o

H S C O M P L I A N T V E R S I O N S A V A I L A B L E

TISP5xxxH3BJ Overvoltage Protection Series

2.Initially the device must be in thermal equilibrium with T J = 25 °C.

3.The surge may be repeated after the device returns to its initial cond itions.

4.See Figure 10 for current ratings at other temperatures.

5.EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5A rated printed wiring

track widths. Derate current values at -0.61%/°C for ambient temperatures above 25°C. See Figure 8 for current ratings at other durations.

JANUARY 1998 - REVISED FEBRUARY 2005

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005

Thermal Characteristics, T A = 25 °C (Unless Otherwise Noted)

TISP5xxxH3BJ Overvoltage Protection Series

dependent on connection inductance.

Parameter

Test Conditions

Min

Typ

Max Unit

R θJA

Junction to ambient thermal resistance

EIA/JESD51-3 PCB, I T = I TSM(1000) (see Note 7)

113

°C/W 265 mm x 210 mm populated line card, 4-layer PCB, I T = I TSM(1000)

NOTE:

7. EIA/JESD51-2 environment and PCB has standard footprint dimensions connected w ith 5A rated printed wiring track widths.

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005Parameter Measurement Information

TISP5xxxH3BJ Overvoltage Protection Series

Figure 1. Voltage-Current Characteristic for Terminal Pair

All Measurements are Referenced to the Thyristor Anode, A (Pin 1)

-v

I (BR)V (BR)

V (BR)M

V DRM I DRM

V D

I H

I T V T

I TRM I PPSM

V (BO)

I (BO)

I D

Quadrant I

Forward Conduction Characteristic

I F

V F

I FRM

I PPSM -i

Quadrant III

Switching Characteristic

PM-TISP5xxx-001-a

I FSM I TSM

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005

Typical Characteristics

TISP5xxxH3BJ Overvoltage Protection Series

Figure 2. Figure 3.

Figure 4.

Figure 5.

T - Junction Temperature - °C

-25

100

125

150

I D - O f f -S t a t e C u r r e n t - μA

0·001

0·01

0·1

10100

T J J - Junction Temperature - °C

-25

100

125

150

N o r m a l i z e d B r e a k o v e r V o l t a g e

0.95

1.00

1.05

1.10

TC5XAIA

V T , V F - On-State Voltage, Forward Voltage - V

0.7

1.523457110I T , I F - O n -S t a t e C u r r e n t , F o r w a r d C u r r e n t - A

1.523457152030405070150200110100TC5LAC

T J - Junction Temperature - °C

-25

0255075100125150

N o r m a l i z e d H o l d i n g C u r r e n t

0.4

0.50.60.70.80.91.5

2.0

1.0TC5XAD

OFF-STATE CURRENT

JUNCTION TEMPERATURE

NORMALIZED BREAKOVER VOLTAGE

JUNCTION TEMPERATURE NORMALIZED HOLDING CURRENT

JUNCTION TEMPERATURE

ON-STATE AND FORWARD CURRENTS

ON-STATE AND FORWARD VOLTAGES

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005Typical Characteristics

TISP5xxxH3BJ Overvoltage Protection Series

Figure 6. Figure 7.

OFF-STATE CAPACITANCE

OFF-STATE VOLTAGE V D - Negative Off-state Voltage - V

23510203050100

C o f f - C a p a c i t a n c e - p F

2030

405060708090150

200

300

100DIFFERENTIAL OFF-STATE CAPACITANCE

RATED REPETITIVE PEAK OFF-STATE VOLTAGE

V DRM - Negative Repetitive Peak Off-State Voltage - V

5865758090120 C - D i f f e r e n t i a l O f f -S t a t e C a p a c i t a n c e - p F

90100110120130140150160170180190

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005

Rating And Thermal Information

TISP5xxxH3BJ Overvoltage Protection Series

Figure 8.

Figure 9.

Figure 10.

t - Current Duration - s

0·1

1101001000

I T S M (t ) - N o n -R e p e t i t i v e P e a k O n -S t a t e C u r r e n t - A

1.52345678915203010

TI5XAD

T AMIN - Minimum Ambient Temperature - °C

-35-25-15-551525

-40-30-20-1001020D e r a t i n g F a c t o r

0.93

0.94

0.950.960.970.980.991.00T A - Ambient Temperature - °C

-40-30-20-100

1020304050607080

I m p u l s e C u r r e n t - A

90100120

150200250300400500600700NON-REPETITIVE PEAK ON-STATE CURRENT

CURRENT DURATION IMPULSE RATING

AMBIENT TEMPERATURE

V DERATING FACTOR vs

MINIMUM AMBIENT TEMPERATURE

DRM

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005Deployment

APPLICATIONS INFORMATION

These devices are two terminal overvoltage protectors. They may be used either singly to limit the voltage between two points (Figure 11) or in multiples to limit the voltage at several points in a circuit (Figure 12).

In Figure 11, the TISP5xxxH3BJ limits the maximum voltage of the negative supply to -V (BO) and +V F . This configuration can be used for protecting circuits where the voltage polarity does not reverse in normal operation. In Figure 12, the two TISP5xxxH3BJ protectors, Th4 and Th5, limit the maximum voltage of the SLIC (Subscriber Line Interface Circuit) outputs to -V (BO) and +V F . Ring and test protection is given by protectors Th1, Th2 and Th3. Protectors Th1 and Th2 limit the maximum tip and ring wire voltages to the ±V (BO) of the individual protector .Protector Th3 limits the maximum voltage between the two conductors to its ±V (BO) value. If the equipment being protected has all its vulnerable components connected between the conductors and ground, then protector Th3 is not required.

TISP5xxxH3BJ Overvoltage Protection Series

Figure 12. Line Card SLIC Protection

AI4XAC

SIGNAL

D.C.

-R1a R1b

TISP5xxxH3BJ Figure 11. Power Supply Protection

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005

The star-connection of three TISP5xxxH3BJ protectors gives a protection circuit which has a low differential capacitance to ground (Figure 13).This example, a -100 V ISDN line is protected. In Figure 13, the circuit illustration A shows that protector Th1 will be forward biased as it is

connected to the most negative potential. The other two protectors, Th2 and Th3 will be reverse biased as protector Th1 will pull their common connection to within 0.5 V of the negative voltage supply.

Illustration B shows the equivalent capacitances of the two reverse biased protectors (Th2 and Th3) as 29 pF each and the capacitance of the forward biased protector (Th1) as 600 pF . Illustration C shows the delta equivalent of the star capacitances of illustration B. The protector circuit differential capacitance will be 26 - 1 = 25 pF . In this circuit, the differential capacitance value cannot exceed the capacitance value of the ground protector (Th3).

A bridge circuit can be used for low capacitance differential. Whatever the potential of the ring and tip conductors are in Figure 14, the array of steering diodes, D1 through to D6, ensure that terminal 1 of protector Th1 is always positive with respect to terminal 2. The protection voltage will be the sum of the protector Th1, V (BO), and the forward voltage of the appropriate series diodes. It is important to select the correct

diodes. Diodes D3 through to D6 divert the currents from the ring and tip lines. Diodes D1 and D2 will carry the sum of the ring and tip currents and so conduct twice the current of the other four diodes. The diodes need to be specified for forward recovery voltage, V FRM , under the expected impulse conditions. (Some conventional a.c. rectifiers can produce as much as 70 V of forward recovery voltage, which would be an extra 140 V added to the V (BO) of Th1). In principle the bridge circuit can be extended to protect more than two conductors by adding extra legs to the bridge.

TISP5xxxH3BJ Overvoltage Protection Series

APPLICATIONS INFORMATION (CONTINUED)

AI4XAB

C -99.5 V Th1

Th2

Th3SIGNAL

C -99.5 V

C 0.5 V 600 pF

29 pF

26 pF

1 pF

26 pF

A) STAR-CONNECTED U-INTERFACE PROTECTOR

B) EQUIVALENT TISP5150H3BJ CAPACITANCES

C) DELTA EQUIVALENT SHOWS 25 pF

LINE UNBALANCE

- 100 V

Figure 13. ISDN Low Capacitance U-Interface Protection

Figure 14. Low Capacitance Bridge Protection Circuit

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.

JANUARY 1998 - REVISED FEBRUARY 2005ISDN Device Selection

The ETSI Technical Report ETR 080:1993 defines several range values in terms of maximum and minimum ISDN feeding voltages. The following table shows that ranges 1 and 2 can use a TISP5110H3BJ protector and ranges 3 to 5 can use a TISP5150H3BJ protector .

Impulse Testing

To verify the withstand capability and safety of the equipment, standards require that the equipment is tested with various impulse wave forms.The table below shows some common values.

If the impulse generator current exceeds the protector’s current rating then a series resistance can be used to reduce the current to the

protector’s rated value and so prevent possible failure. The required value of series resistance for a given waveform is given by the following calculations. First, the minimum total circuit impedance is found by dividing the impulse generator’s peak voltage by the protector’s rated current. The impulse generator’s fictive impedance (generator’s peak voltage divided by peak short circuit current) is then subtracted from the minimum total circuit impedance to give the required value of series resistance. In some cases the equipment will require verification over a temperature range. By using the rated waveform values from Figure 10, the appropriate series resistor value can be calculated for ambient temperatures in the range of -40 °C to 85 °C.

If the devices are used in a star-connection, then the ground return protector, Th3 in Figure 13, will conduct the combined current of protectors Th1 and Th2. Similarly in the bridge connection (Figure 14), the protector Th1 must be rated for the sum of the conductor currents. In these cases, it may be necessary to include some series resistance in the conductor feed to reduce the impulse current to within the protector’s ratings.

TISP5xxxH3BJ Overvoltage Protection Series

APPLICATIONS INFORMATION

Range Feeding Voltage

Standoff Voltage

V DRM V

Device Name Minimum

Maximum

15169-75TISP5095H3BJ 26670 -80

TISP5110H3BJ

39199-120

TISP5150H3BJ

4901105

105

115

Standard

Peak Voltage Setting

Voltage Waveshape

μs

Peak Current

Value A

Current Waveshape

μs

TISP5xxxH3BJ 25°C Rating

Series Resistance

GR-1089-CORE

25002/105002/105000100010/100010010/1000100TIA-968-A

1500

10/16020010/160250080010/56010010/560

160

015009/720?37.55/320? 20001000

9/720?255/320? 2000I312415000.5/70037.50.2/3102000ITU-T K.20/21/45

150040006000

10/700

37.5100150

5/310

200

? TIA-968-A terminology for the waveforms produced by the ITU-T recommendation K.21 10/700 impulse generator.

TISP5xxxH3BJ Overvoltage Protection Series

APPLICATIONS INFORMATION

AC Power Testing

The protector can withstand currents applied for times not exceeding those shown in Figure 8. Currents that exceed these times must be terminated or reduced to avoid protector failure. Fuses, PTC (Positive T emperature Coefficient) resistors and fusible resistors are overcurrent protection devices which can be used to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one ampere. In some cases it may be necessary to add some extra series resistance to prevent the fuse opening during impulse testing. The current versus time characteristic of the overcurrent protector must be below the line shown in Figure 8. In some cases there may be a further time limit imposed by the test standard (e.g. UL 1459 wiring simulator failure).

Capacitance

The protector characteristic off-state capacitance values are given for d.c. bias voltage, V D, values of -1 V, -2 V and -50 V. The TISP5150H3BJ and TISP5190H3BJ are also given for a bias of -100 V. Values for other voltages may be determined from Figure 6. Up to 10 MHz, the capacitance is essentially independent of frequency. Above 10 MHz, the effective capacitance is strongly dependent on connection inductance. In Figure 12, the typical conductor bias voltages will be about -2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance caused by biasing one protector at -2 V and the other at -50 V. For example, the TISP5070H3BJ has a differential capacitance value of 166 pF under these conditions.

Normal System Voltage Levels

The protector should not clip or limit the voltages that occur in normal system operation. Figure 9 allows the calculation of the protector V DRM value at temperatures below 25 °C. The calculated value should not be less than the maximum normal system voltages. The TISP5150H3BJ, with a V DRM of -120 V, can be used to protect ISDN feed voltages having maximum values of -99 V, -110 V and -115 V (range 3 through to range 5). These three range voltages represent 0.83 (99/120), 0.92 (110/120) and 0.96 (115/120) of the -120 V TISP5150H3BJ V DRM. Figure 9 shows that the V DRM will have decreased to 0.944 of its 25 °C value at -40 °C. Thus, the supply feed voltages of -99 V (0.83) and -110 V (0.92) will not be clipped at temperatures down to -40 °C. The -115 V (0.96) feed supply may be clipped if the ambient temperature falls below -21 °C. JESD51 Thermal Measurement Method

T o standardize thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51 standard. Part 2 of the standard (JESD51-2, 1995) describes the test environment. This is a 0.0283 m3 (1 ft3 ) cube which contains the test PCB (Printed Circuit Board) horizontally mounted at the center. Part 3 of the standard (JESD51-3, 1996) defines two test PCBs for surface mount components; one for packages smaller than 27 mm on a side and the other for packages up to 48 mm. The SMB (DO-214AA) measurements used the smaller 76.2 mm x 114.3 mm (3.0 ” x 4.5 ”) PCB. The JESD51-3 PCBs are designed to have low effective thermal conductivity (high thermal resistance) and represent a worse case condition. The PCBs used in the majority of applications will achieve lower values of thermal resistance and so can dissipate higher power levels than indicated by the JESD51 values.

“TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office.

“Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries.

JANUARY 1998 - REVISED FEBRUARY 2005

Specifications are subject to change without notice.

Customers should verify actual device performance in their specific applications.