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LM1262中文资料

LM1262

200MHz I 2C Compatible RGB Video Amplifier System with OSD and DACs

General Description

The LM1262pre-amp is an integrated CMOS CRT pre-amp.The IC is I 2C compatible,and allows control of all the pa-rameters necessary to directly setup and adjust the gain and contrast in the CRT display.Brightness and bias can be controlled through the DAC outputs,and is well matched to the LM2479and LM2480integrated bias clamp IC.

The LM1262pre-amp is designed to work in cooperation with the LM246X high gain driver family.

Black level clamping of the signal is carried out directly on the AC coupled input signal into the high impedance pream-plifier input,thus eliminating the need for additional black level clamp capacitors.

The IC is packaged in an industry standard 24-lead DIP molded plastic package.

Features

n I 2C compatible interface

n 4external 8-bit DACs for bus controlled Bias and Brightness

n Vertical blank from sandcastle or input at pin 13OR’ed with horz.blank signal,option selected by I 2C

n Contrast and brightness updates synchronous with vertical blank,enabled by I 2C

n Video set to black level through I 2C

n Suitable for use with discrete or integrated clamp,with software configurable Brightness mixer

n Power Save (Green)Mode,80%power reduction n Matched to 11-lead LM246X driver

Applications

n High end 19”and 21”bus controlled monitors with OSD n 1600X 1200,85Hz or higher applications

n Low cost and high performance system with LM246X driver

Block and Connection Diagram

DS200404-1

FIGURE 1.Order Number LM1262NA See NS Package Number N24D

March 2002

LM1262200MHz I 2C Compatible RGB Video Amplifier System with OSD and DACs

?2002National Semiconductor Corporation https://www.wendangku.net/doc/7512355093.html,

Absolute Maximum Ratings (Notes 1,3)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage,Pin 9

6.0V

Peak Video Output Source Current (Any One Amp)Pins 18,19,or 2028mA Voltage at Any Input Pin (V IN )

V CC +0.5>V IN >?0.5V

Power Dissipation (P D )

(Above 25?C Derate based on θJA and T J )

2.4W Thermal Resistance to Ambient (θJA )

51?C/W

Thermal Resistance to Case (θJC )32?C/W Junction Temperature (T J )150?C ESD Susceptibility (Note 4) 3.5kV ESD Machine Model (Note 5)350V

Storage Temperature ?65?C to +150?C

Lead Temperature (Soldering,10sec.)

265?C

Operating Ratings (Note 2)

Temperature Range 0?C to 70?C

Supply Voltage (V CC ) 4.75V

0.0V

Active Video Signal Electrical Characteristics

Unless otherwise noted:T A =25?C,V CC =+5V,V IN =0.7V,V ABL =V CC ,C L =5pF,Video Signal Output =2V P-P .Symbol Parameter

Conditions

Min (Note 7)Typ (Note 6)Max (Note 7)Units I S Maximum Supply Current Test Setting 1,R L =∞(Note 8)

170230

mA I S-PS Maximum Supply Current,Power Save Mode Test Setting 1,R L =∞,Bit 1of Reg.9=1(Note 8)45mA LE Linearity Error

Test Setting 4,Triangular signal input source (Note 9)5

V O Blk Typ Typical Video Black Level Output

Test Setting 4,No AC Input Signal

0.9 1.1 1.3VDC V O Blk Step Video Black Level Step Size Test Setting 4,No AC Input Signal

80110140

mV V O White-Max White Level Video Output Voltage

Test Setting 3,Video in =0.7V 4.0 4.3V

V Blank Blanked Output Level Test Setting 4,AC Input Signal 0

0.050.2V t r Rise Time

10%to 90%,Test Setting 4,AC Input Signal (Note 10) 1.9ns OS R Overshoot (Rising Edge)Test Setting 4,AC Input Signal (Note 10)

6%t f Fall Time

90%to 10%,Test Setting 4,AC Input Signal (Note 10) 2.0ns OS F Overshoot (Falling Edge)Test Setting 4,AC Input Signal (Note 10)

8%f(?3dB)Video Amplifier Bandwidth (Note 13)

Test Setting 4,V O =2V P-P 200MHz V sep 10kHz Video Amplifier 10kHz Isolation

Test Setting 8(Note 14)?70dB V sep 10MHz Video Amplifier 10MHz Isolation

Test Setting 8(Note 14)?50

A V Max Maximum Voltage Gain Test Setting 8,AC Input Signal 3.90 4.15 4.40V/V A V 1/2Contrast @50%Level Test Setting 5,AC Input Signal ?10d

B A V Min Maximum Contrast Attenuation Test Setting 2,A

C Input Signal ?20dB A V Gain 1/2Gain @50%Level Test Setting 6,AC Input Signal ?5dB A V Gain Min Maximum Gain Attenuation Test Setting 7,AC Input Signal ?10

dB A V Match Absolute Gain Match @A V Max

Test Setting 3,AC Input Signal ±0.5dB A V Track

Gain Change between Amplifiers

Tracking when changing from Test Setting 8to Test Setting 5(Note 11)

±0.5

L M 1262

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Active Video Signal Electrical Characteristics(Continued)

Unless otherwise noted:T A=25?C,V CC=+5V,V IN=0.7V,V ABL=V CC,C L=5pF,Video Signal Output=2V P-P.

Symbol Parameter Conditions Min

(Note7)

Typ

(Note6)

Max

(Note7)Units

V ABL TH ABL Control Upper Limit Test Setting4,AC Input Signal

(Note12)

V ABL Range ABL Active Range Control

Voltage Test Setting4,AC Input Signal

(Note12)

2.7V

?A ABL ABL Control Range Test Setting4,AC Input Signal

(Note12)

-6?8dB

I ABL Active ABL Input Bias Current during

ABL Test Setting4,AC Input

Signal,V ABL=2V(Note12)

010μA

I ABL Max ABL Input Current Clamp Sink

Capability Test Setting4,AC Input Signal

(Note12)

1mA

V Vert Bnk Off Vertical Blank Gate Low

Input Voltage at pin13Vertical Blank Comparators Off

18)

1.0V

V Vert Bnk On Vertical Blank Gate High

Input Voltage at pin13Vertical Blank Comparators On

18)

2.6V

I Vert Bnk Low Vertical Blank Gate Low

Input Current at pin13V13=0V,Register B set to

0x02(Note18)

-4.0μA

I Vert Bnk High Vertical Blank Gate High

Input Current at pin13V13=V CC,Register B set to

0x02(Note18)

(internal50k resistor to ground)

100μA

V Vert Bnk Off Vertical Blank Gate Low

Input Voltage at pin23Vertical Blank Comparators Off

0.7V

V Vert Bnk On Vertical Blank Gate High

Input Voltage at pin23Vertical Blank Comparators On

16)

1.2 3.2V

V Clamp Min Horizontal Clamp Gate High

Input Voltage Horizontal Clamp Comparators

3.8V

I Clamp Clamp Gate Input Current V23=0V to V CC?1V,

?50.110μA t PW Clamp Back Porch Clamp Pulse Width(Note15)200ns

t Clamp-Video End of Clamp Pulse to Start of

Active Video Limit is guaranteed by design

200ns

t PW SandClamp Sandcastle Clamp Pulse Width Horizontal Clamp Comparators

On Register B set to0x06

(Note16)

0.20 1.20μsec R In-Video Input Resistance Test Setting(4)20M?V Ref Out V Ref Output Voltage10k?,1%Resistor;Pin10to

GND

1.25 1.40 1.55V V Spot Spot Killer Voltage V CC Adjusted to Activate 3.4 4.0 4.25V OSD Electrical Characteristics

Unless otherwise noted:T A=25?C,V CC=+5V,V IN=0.7V,V ABL=V CC,C L=5pF,Video Signal Output=2V P-P,Test Set-ting8.

Symbol Parameter Conditions Min

(Note7)

Typ

(Note6)

Max

(Note7)Units

V OSD-L OSD Input Low Input

Operating Range OSD Inputs are Selected

1.2V

V OSD-H OSD Input High Input

Operating Range OSD Inputs are Selected

2.5V

I OSD OSD Input Current V OSD=0V to V CC?1V?50.110μA

LM1262

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OSD Electrical Characteristics

(Continued)

Unless otherwise noted:T A =25?C,V CC =+5V,V IN =0.7V,V ABL =V CC ,C L =5pF,Video Signal Output =2V P-P ,Test Set-ting 8.Symbol Parameter

Conditions

Min (Note 7)

Typ (Note 6)

Max (Note 7)Units V OSD-Sel-L OSD Select Low Input Operating Range Video Inputs are Selected 1.2

V V OSD-Sel-H OSD Select High Input Operating Range OSD Inputs are Selected 3.5V I OSD-Sel OSD Select Input Current V OSD-Sel =0V to V CC ?1V ?5

0.1

μA ?V O-OSD(Blk)

OSD ?Black Level Output

Voltage,Difference from Video Output

±45±150

V O-OSD(Blk)

Range of OSD Black Level Output Voltage between the 3Channels

?1000+100mV V OSD-out OSD Output Voltage,Percent of Maximum Video Out Register 08=18,Minimum Video Black Level 8595105%?V OSD-out OSD Output V P-P Attenuation Register 08=0852

%V OSD-out (Match)Output Match between Channels

±5.0%

V OSD-out (Track)Output Variation between Channels

±3.0±5.0

%?t OSD/OSD S Output Skew Time between OSD and OSD Select Measured from 50%Point on all Waveforms ±2.0

ns V feed 10kHz Video Feedthrough into OSD OSD Inputs =0V ?70dB V feed 10MHz

Video Feedthrough into OSD

OSD Inputs =0V

?60

External DAC Signals Electrical Characteristics

Unless otherwise noted:T A =25?C,V CC =+5V,V IN =0.7V,V ABL =V CC ,C L =5pF,Video Signal Output =2V P-P .The follow-ing apply for all four external DACs.Symbol Parameter

Conditions

Min (Note 7)

Typ (Note 6)Max (Note 7)Units V Min DAC Min DAC Output Voltage Value =00h

0.50.75

V V Max DAC Mode 00Max DAC Output Voltage Value =FFh,DCF[1:0]=00h (no load)

3.6

4.2V V Max DAC Mode 11Max Output Voltage of DACs 1–3in DCF Mode 11Value =FFh,DCF[1:0]=11h,DAC4Value =00h 2.05 2.40

2.75V ?V Max DAC (Temp)Variation of any DAC output voltage with temperature 0?C

4.75V

5.25V

±50

mV/V Linearity Linearity of DAC Over its Range

%Monotonicity

Monotonicity of the DAC

Excluding dead zones at limits of DAC

±0.5

LSB

External Interface Signals Electrical Characteristics

Unless otherwise noted:T A =25?C,V CC =+5V,V IN =0.7V,V ABL =V CC ,C L =5pF,Video Output =2V P-P .Symbol Parameter

Conditions

Min (Note 7)

Typ (Note 6)

Max (Note 7)Units V l (I 2C)I 2C Low Input Voltage SDA or SCL Inputs 1.5

V V h (I 2C)

I 2C High Input Voltage

SDA or SCL Inputs

3.0V

L M 1262

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External Interface Signals Electrical Characteristics(Continued)

Unless otherwise noted:T A=25?C,V CC=+5V,V IN=0.7V,V ABL=V CC,C L=5pF,Video Output=2V P-P.

Symbol Parameter Conditions Min

(Note7)

Typ

(Note6)

Max

(Note7)Units

t H-Blank on H-Blank Time Delay from Zero

Crossing Point of H Flyback Rising Edge of the Flyback

Signal

50ns

t H-Blank off H-Blank Time Delay from Zero

Crossing Point of H Flyback Falling Edge of the Flyback

Signal

50ns

I In Threshold I In H-Blank Detection

Threshold

?20μA

I In-Operating Minimum—Insure Normal

Operation

Maximum—Should Not

Exceed in Normal Operation Lowest Operating Horizontal

Frequency in Given Application

(Note17)

?30?300μA

I In Flyback Peak Current during Flyback

Period,Recommended Design

Range Operating Range for all

Horizontal Scan Frequencies,

Maximum Current Should Not

Exceed2mA(Note17)

0.5 1.5 2.0mA

Note1:Limits of Absolute Maximum Ratings indicate limits below which damage to the device must not occur.

Note2:Limits of operating ratings indicate required boundaries of conditions for which the device is functional,but may not meet specific performance limits.

Note3:All voltages are measured with respect to GND,unless otherwise specified.

Note4:Human body model,100pF discharged through a1.5k?resistor.

Note5:Machine Model ESD test is covered by specification EIAJ IC-121-1981.A200pF cap is charged to the specified voltage,then discharged directly into the

IC with no external series resistor(resistance of discharge path must be under50?).

Note6:Typical specifications are specified at+25?C and represent the most likely parametric norm.

Note7:Tested limits are guaranteed to National’s AOQL(Average Outgoing Quality Level).

Note8:The supply current specified is the quiescent current for V CC with R L=∞.Load resistors are not required and are not used in the test circuit,therefore all

the supply current is used by the pre-amp.

Note9:Linearity Error is the variation in step height of a16step staircase input signal waveform with0.7V P-P level at the input,subdivided into16equal steps,

with each step approximately100ns in width.

Note10:Input from signal generator:t r,t f<1ns.Scope and generator response used for testing:t r=1.1ns,t f=https://www.wendangku.net/doc/7512355093.html,ing the RSS technique the scope and generator response have been removed from the output rise and fall times.

Note11:?A V track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages.It is the difference in

gain change between any two amplifiers with the contrast set to A V1/2and measured relative to the A V max condition.For example,at A V max the three amplifiers’

gains might be12.1dB,11.9dB,and11.8dB and change to2.2dB,1.9dB and1.7dB respectively for contrast set to A V1/2.This yields a typical gain change of

10.0dB with a tracking change of±0.2dB.

Note12:ABL should provide smooth decrease in gain over the operational range of0dB to–6dB

?A ABL=A(V ABL=V ABL Max Gain)-A(V ABL=V ABL Min Gain)

Beyond–6dB the gain characteristics,linearity,pulse response,and/or behavior may depart from normal values.

Note13:Adjust input frequency from10MHz(A V max reference level)to the?3dB corner frequency(f?3dB).

Note14:Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation.Terminate the undriven amplifier

inputs to simulate generator loading.Repeat test at f IN=10MHz for V sep10MHz.

Note15:A minimum pulse width of200ns is guaranteed for a horizontal line of15kHz.This limit is guaranteed by design.If a lower line rate is used then a longer

clamp pulse may be required.

Note16:The internal circuit detects the vertical blank only when this signal is present in the sandcastle input.There is typically an800nsec delay in detecting the

vertical blank signal.If only the horizontal clamp is present the vertical blank will not be activated.Rise and fall times of the sandcastle input signal should be10nsec

or faster.

Note17:Limits met by matching the external resistor going to pin24to the H Flyback voltage.

Note18:A4.7k?resistor must be in series with pin13when this pin is the input for vertical blanking.When the LM1262is first turned on the default condition for

pin13is for the DAC4output.Under this condition pin13will be damaged by the vertical blanking input if a series resistor is not used.

LM1262

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Typical Performance Characteristics

V CC =5V,T A =25?C unless otherwise specified.Gain Attenuation

DS200404-2Contrast Attenuation

DS200404-3

ABL Attenuation DS200404-4

Rise and Fall

DS200404-5

Contrast vs Frequency DS200404-6Gain vs Frequency

DS200404-7

L M 1262

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Test Circuit

Test Settings

Control

No.of Bits Basic Test Setting 1Basic Test Setting 2Basic Test Setting 3Basic Test Setting 4Basic Test Setting 5Basic Test Setting 6Basic Test Setting 7Basic Test Setting 8Contrast 7Max (Hex 7F)Min (Hex 00)Max (Hex 7F)Max (Hex 7F)50%(Hex 40)Max (Hex 7F)Max (Hex 7F)Max (Hex 7F)R,G,B Gain

Max (Hex 7F)Max (Hex 7F)Max (Hex 7F)Set Video Output to 2V P-P Max (Hex 7F)50%(Hex 40)Min (Hex 00)Max (Hex 7F)Video DC Offset &OSD Cont.5

Min (Hex 18)

Min +0.5V (Hex 1D)

Max (Hex 07)

Min +0.5V (Hex 1D)

Timing Diagrams

DS200404-10

Note:5pF load includes parasitic capacitance.

DS200404-11

FIGURE 2.Blanking Propagation Delay

LM1262

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Timing Diagrams

(Continued)

Pin Descriptions

Pin No.Pin Name Schematic

Description

123

Red OSD Input Green OSD Input Blue OSD Input

These inputs accept standard TTL or CMOS inputs.Each color is either fully on (logic high)or fully off (logic low).Unused pins should be connected to ground with a 47k resistor.

4OSD Select

This input accepts a standard TTL or CMOS input.H =OSD L =Video

Connect to ground with a 47k resistor if not using OSD.

DS200404-12

FIGURE 3.OSD Output Skew

L M 1262

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Pin Descriptions

(Continued)

Pin No.Pin Name Schematic

Description

567

Red Video In Green Video In Blue Video In

Video inputs.These inputs must be AC

coupled with a 4.7nF cap.DC restoration is done at these inputs.A series resistor of about 33?and external ESD protection diodes should also be used for ESD protection.

8Analog Ground Ground Pin for the analog circuits of the LM1262.

9V CC Power supply pin for LM1262.

V ref R ext

Sets the internal current sources through a 10k ?1%external resistor.Resistor value and accuracy is critical for optimum operation of the LM1262.

11SDA

The I 2C data line.A pull-up resistor of about 2k ?should be connected between this pin and +5V.A 300?resistor should be connected in series with the data line for protection against arcing.

12SCL

The I 2C Clock line.A pull-up resistor of about 2k ?should be connected between this pin and +5V.A 300?resistor should be connected in series with the clock line for protection against arcing.

13141516DAC4DAC3DAC2DAC1

DAC outputs for cathode cut-off adjustments and brightness control.DAC 4can be set to change the outputs of the other three DACs,acting as the brightness control.The DACs are set through the I 2C bus.

17Digital Ground

Ground Pin for the digital circuits of the LM1262.

LM1262

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Pin Descriptions

(Continued)

Pin No.Pin Name

Schematic

Description

181920

Blue Video Out Green Video Out Red Video Out

Video outputs of the LM1262.The ideal

driver for this part is the LM246X CRT driver family,which has the necessary gain of 26dB or 20V/V.

V Ref Out

A 0.1μF capacitor must be placed close to this pin for decoupling the internal V Ref .This pin may be used for an external voltage reference with proper buffering.

22ABL

The Auto Beam Limit control reduces the gain of the video amplifier in response to a control voltage proportional to the CRT beam current.The ABL acts identically on all three channels.ABL is required for CRT life and X-ray protection.

23Clamp Pulse

This input accepts a standard TTL or CMOS input.The signal can be either positive or negative going.The polarity is set in register 0Bh bit-3.The signal activates the clamp pulse for DC restoration of the video input.The AC coupling capacitors at the video

inputs are used for holding the DC correction voltage,eliminating the need for additional capacitors.

24H Flyback

H flyback is an analog signal input from the monitor horizontal scan.The LM1262is able to generate an accurate blanking pulse in the video outputs from this input.The

horizontal flyback from the monitor must be a clean signal,with no ringing or other noise on the signal.

L M 1262

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Functional Description

All functions of the LM1262are controlled through the I2C Bus.Details on the internal registers are covered in the

I2C Interface Registers Section.Figure1shows the block diagram of the LM1262.The I2C signals come in on pins 11and12and go to the I2C Interface.Both the internal blocks with an“R”and the four external DACs are con-trolled by the I2C Interface.The video and OSD blocks are shown for the red channel in Figure1.The blocks for both the green and blue channels are not shown;how-ever,they are identical to the red channel.

Proper operation of the LM1262does require a very accurate reference voltage.This voltage is generated in the V Ref block.To insure an accurate voltage over tem-perature,an external resistor is used to set the current in the V Ref stage.The external resistor is connected to pin 10.This resistor should be1%and have a temperature coefficient under100ppm/?C.ALL VIDEO SIGNALS MUST BE KEPT AWAY FROM PIN10.This pin has a very high input impedance and will pick up any high frequency signals routed near it.The board layout shown in Figure 10is a good example of trace routing near pin10.The output of the V Ref stage goes to a number of blocks in the video section and also to pin21.This pin allows capacitor filtering on the V Ref output and offers an accurate external reference.A buffer must be used with this reference,the maximum current loading should be only100μA.

Note:Any noise injected into pin21will appear on the video.The voltage reference must be kept very clean for best performance of the

LM1262.

The video inputs are pins5,6,and7.Looking at the red channel(pin5)note that the“Clamp DC Restore Amp”is connected to this pin.Since the video must be AC coupled to the LM1262,the coupling cap is also used to store the reference voltage for DC restoration.The“Clamp DC Re-store Amp”block charges the input capacitor to the correct voltage when the clamp pulse(pin23)is active.The“Hi Z Input Buffer Amp”buffers the video signal for internal pro-cessing.Input impedance to this stage is typically20M?. With such a high impedance the DC restoration can appear to be working for a number of minutes after the clamp pulse is removed.

The output of the Buffer Amp goes to the Contrast stage.The 7bit contrast register(03h)sets the contrast level through the I2C bus.This register controls the Contrast stage in each video channel.Contrast adjustment range is up to?20dB. Loading all zeros in the contrast register gives?20dB at-tenuation.All ones will give no attenuation.The output of this stage is used as the feedback for the DC restoration loop.“Auto Beam Limit Amp”or ABL is the next block in the video path.This is a voltage controlled gain stage which gives no attenuation with5V at pin22and gives about?10dB attenu-ation with2V at pin2.ABL is covered in more detail later in this section.

Next in the video path is the“OSD Mixer”.The OSD Select signal at pin4controls this stage,selecting OSD with a high at pin4,and video with a low at pin 4.Since the DC restoration feedback is at the Contrast output,the video black level will match the OSD black level.The OSD signal is mixed with the video signal at the output of this stage.

The OSD goes through the“OSD Contrast”stage before entering the“OSD Mixer”block.Bits3and4of register08h control the OSD contrast giving four video levels for the OSD

window.Maximum video level for the OSD window occurs

with both bits set to one.Minimum video level will occur with

both bits set to a zero.

Following the“OSD Mixer”is the“Gain”block.Each video

channel has its own independent control of this block so the

user can balance the color of the CRT display.Registers

00h,01h,02h are used for the gain attenuation.These

registers are7bits with the maximum attenuation of?10dB

occurring when all zeros are loaded.

The final block in the video path is the“Output Buffer Amp”.

This stage provides the drive needed for the inputs of a CRT

driver.The recommended driver for this pre-amp is one of

the LM246X family.Horizontal blanking is also added to the

video signal from the“H Blank”stage.This block is covered

in more detail below.DC offset of the output is set by the“DC

DACs Offset”stage.Bits0through2in register08control

this stage.This gives8different black levels ranging from

0.75V to1.55V.When using one of the LM246X CRT driver

family it is recommended that the black level be set to1.25V.

ABL:The Auto Beam Limit control reduces the gain of the

video amplifiers in response to a control voltage proportional

to the CRT beam current.The ABL acts on all three channels

in an identical manner.This is required for CRT life and X-ray

protection.The beam current limit circuit application is as

shown in Figure4:when no current is being drawn by the

EHT supply,current flows from the supply rail through the

ABL resistor and into the ABL input of the IC.The IC clamps

the input voltage to a low impedance voltage source(the5V

supply rail).

When current is drawn from the EHT supply,some of the

current passing through the ABL resistor goes to the EHT

supply,which reduces the current flowing into the ABL input

of the IC.

When the EHT current is high enough,the current flowing

into the ABL input of the IC drops to zero.This current level

determines the ABL threshold and is given by:

Where:

V S is the external supply(usually the CRT driver supply rail,

about80V)

V ABL TH is the threshold ABL voltage of the IC

R ABL is the ABL resistor value

I ABL is the ABL limit

When the voltage on the ABL input drops below the ABL

threshold of the pre-amp,the gain of the pre-amp reduces,

which reduces the beam current.A feedback loop is thus

established which acts to prevent the average beam current

exceeding I ABL.

LM1262

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Functional Description(Continued)

H Flyback:H Flyback is an analog signal input from the

monitor horizontal scan.The“H Blank”section uses this

signal to add horizontal blanking to the output video signal.

This enables the user to blank at the cathodes during hori-

zontal flyback.An optional capacitor and/or resistor to

ground may be needed if noise interferes with the H Flyback

signal.

This feature gives very accurate timing for the horizontal

blanking;however,the flyback signal must be very clean.

There should be no ringing or other noise on the flyback

signal.

R LIMIT is used to limit the input current into the IC to a typical

value of+1mA during flyback and?100μA during normal

forward scan.For example if an H flyback with a peak of

100V is used,R LIMIT=100k?.The internal input impedance

of pin24is low to limit the maximum voltage swing at the

input to within the supply rail and ground.The IC interface

circuit creates a digital signal from this waveform,which is

used as the blanking signal at the“Output Buffer Amp”.This

signal adds blanking to the video output signal.Figure5

shows the H flyback waveforms and the location of R LIMIT.A

56pF capacitor has been added to the H Flyback pin on the

demo board for filtering noise on the H Flyback signal.

H Blank:Some customers may still prefer to use a standard

logic signal for the horizontal blanking.Pin24can be

adapted to accept a logic input.It is necessary for the current

flow into pin24to reverse for proper operation.Therefore the

logic signal must be AC coupled into pin24.Figure6shows

the recommended circuit for a logic signal input.The blank

signal must be a positive pulse.

V Blank and Sandcastle Pulse:By setting bit1of register

0B to a“1”the vertical blanking function is enabled.In this

mode the vertical blanking is OD’d with the horizontal blank-

ing,setting the outputs of the LM1262to the blank level the

vertical flyback time.Activating vertical blanking also syn-

chronizes the I2C updates being made to the contrast and

DAC4(brightness)registers to occur within the vertical re-

trace period.Therefore each field will have a uniform bright-

ness since all contrast and brightness changes occur only

during the vertical retrace period.

Two different ways are used to input vertical blanking into the

LM1262:

DS200404-26

FIGURE4.ABL

DS200404-27

FIGURE5.H Flyback Input Pulse

DS200404-28

FIGURE6.Standard Logic H Blank

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Functional Description(Continued)

1.A logic level vertical blanking pulse comes in at pin13.

Bit2of register0B is set to a“0”to enable this method.

There is no output for DAC4,but its output is still con-nected to DAC1-3inputs,maintaining the brightness feature.WARNING:A4.7k?resistor must be in series with pin13when it is used for the vertical blanking input, see Note18.

2.A sandcastle pulse comes in at pin2

3.Bit2of register

0B is set to a“1”,the default value.Vertical blanking is detected from the sandcastle pulse.Note that bit1of register0B must also be set to a“1”for proper detection of the sandcastle pulse.The output of DAC4is con-nected to pin13as well as DAC1-3.The sandcastle detection is compatible with the sandcastle pulse gener-ated by the Philips defection controller parts.

Power Save Mode:There are two modes of power save:

1.Blanking the video

2.Turning off most of the power for maximum power sav-

ings.

In the first mode the video is completely blanked.By setting bit-0in register9to a1the video will be completely blanked. This gives some power savings since there is no beam current in the monitor.Maximum power saving is obtained in the second mode.Bits0and1in register9should be set to a1.Bit1in register9turns off the video output stage of the LM1262,giving a high impedance at the output pin.After bits 0and1of register9are set to a1,the power supplies to the CRT driver and CRT can be turned off.

Note:The5V supply must remain on for proper operation.Since the LM1262 is a CMOS device its power consumption will be minimal. External DACs:Four DACs with external outputs are pro-vided in the LM1262.Normally these DACs will be used for color balance and brightness control.If the brightness con-trol is done at G1,then three DACs would be used for color balance and the last DAC would be used for controlling the G1voltage.

There is also a provision to set the brightness at the cath-odes.DAC4can be set to vary the outputs of the other three DACs after the color balance is completed.This is accom-plished by adding the output of DAC4to the other3DACs. Bits3and4of register9are set to a1for brightness control at the cathodes.Bit3sets the output range of DAC1–3to 50%of their full range.Bit4adds50%of DAC4to the other three DACs.These two adjustments keeps the overall output voltage of DAC1–3in the proper range and still allows brightness control.For either mode of brightness control,the DACs are ideally set to work with the LM2479or LM2480for DC restoration at the cathodes of the CRT.

When the brightness control is done at the cathodes and the output of DAC4is not used,then pin13can be used as a vertical input.This function is controlled by bit2in register B. ESD and Arc-Over Protection

The LM1262incorporates full ESD protection with special consideration given to maximizing arc-over robustness.The monitor designer must still use good circuit design and PCB layout techniques.The human body model ESD susceptibil-

ity of the LM1262is3.5kV,however many monitor manu-

facturers are now testing their monitors to the level4of the

IEC801-2specification which requires the monitor to survive

an8kV discharge.External ESD protection is needed to

survive this level of ESD.The LM1262provides excellent

protection against both ESD and arc-over,but this is not a

substitute for good PCB layout.

Figure7shows the recommended input protection for the

LM1262.This provides the best protection against ESD.

When this protection is combined with good PCB layout the

LM1262will easily survive the IEC801-2level4testing(8kV

ESD).It is strongly recommended that the protection diodes

be added as shown in Figure7.The1N4148diode has a

maximum capacitance of4pF,which will have little effect on

the response of the video system due to the low impedance

of the input video.

The ESD cells of the LM1262also provide good protection

against arc-over,however good PCB layout is necessary.

The LM1262should not be exposed directly to the voltages

that may occur during arc-over.The main vulnerability of the

LM1262to arc-over is though the ground traces on the PCB.

For proper protection all ground connections associated with

the LM1262,including the grounds to the bypass capacitors,

must have short returns to the ground pins.A significant

ground plane should be used to connect all the LM1262

grounds.Figure10,which shows the demo board layout,is

an excellent example of an effective ground plane.The list

below should be followed to ensure a PCB with good

grounding:

?All grounds associated with the LM1262should be con-nected together through a large ground plane.

?CRT driver ground is connected to the video pre-amp ground at one point.

?CRT and arc protection grounds are connected directly to the chassis or main ground.There is no arc-over current

flow from these grounds through the LM1262grounds.

?Input signal traces for SDA,SCL,H Flyback,and Clamp should be kept away from the CRT driver and all traces

that could carry the arc current.

?Output signal traces of the LM1262should be kept away from the traces that carry the output signals of the CRT

driver.

If any one of the above suggestions is not followed the

LM1262may become more vulnerable to arc-over.Improper

grounding is by far the most common cause of video pre-

amp failures during arc-over.

DS200404-29

FIGURE7.Recommended Video Input ESD Protection

LM1262

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Schematic

DS200404-35

FIGURE 8.High Speed Low Cost Neck Board Schematic

L M 1262

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LM1262 Schematic(Continued)

DS200404-36

FIGURE9.High Speed Low Cost Neck Board Schematic

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PCB Layout

Micro-Controller Interface

The micro-controller interfaces to the LM1262pre-amp via an I 2C interface.The protocol of the interface begins with the Start Pulse followed by a byte comprised of a seven-bit Slave Device Address and a Read/Write bit as the LSB.Therefore the address of the LM1262for writing is DCh (11011100)and the address for reading is DDh (11011101).Figures 11,12show a write and read sequence across the I 2C interface.

Write Sequence

The write sequence begins with a start condition which consists of the master pulling SDA low while SCL is held high.The slave device address is next sent.The address byte is made up of an address of seven bits (7–1)and the read/write bit (0).Bit 0is low to indicate a write operation.Each byte that is sent is followed by an acknowledge.When SCL is high the master will release the SDA line.The slave must pull SDA low to acknowledge.The address of the register to be written to is sent next.Following the register address and the acknowledge bit the data for the register is sent.If bit 0of register 0Ah is set low (default value)then the LM1262is set for the increment mode.In this mode when more than one data byte is sent it is automatically incre-mented into the next address location.See Figure 11.Note that each data byte is followed by an acknowledge bit.

Read Sequence

Read sequences are comprised of two I 2C transfer se-quences.The first is a write sequence that only transfers the address to be accessed.The second is a read sequence that starts at the address transferred in the previous address write access and incrementing to the next address upon every data byte read.This is shown in Figure 12.

The write sequence consists of the Start Pulse,the Slave Device Address including the Read/Write bit (a zero,indicat-ing a write),then its Acknowledge bit.The next byte is the address to be accessed,followed by its Acknowledge bit and the stop bit indicating the end of the address only write access.

Next the read data access is performed beginning with the Start Pulse,the Slave Device Address including the Read/Write bit (a one,indicating a read)and the Acknowledge bit.The next 8bits will be the data read from the address indicated by the write sequence.Subsequent read data bytes will correspond to the next increment address loca-tions.Each data byte is separated from the other data bytes by an Acknowledge bit.

DS200404-37

FIGURE 10.High Speed Low Cost System Neck Board

L M 1262

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Micro-Controller Interface

(Continued)

DS200404-33

FIGURE 11.I 2C Write Sequence

DS200404-32

FIGURE 12.I 2C Read Sequence

LM1262

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I 2C Interface Registers

I 2C IC ADDRESS

Slave Address of the LM1262is DCh when writing to the registers and DD when reading from the registers.

LM1262Pre-Amp Interface Registers (all numbers in Hex)

R Gain Control 0060h X R Gain [6:0]B Gain Control 0160h X B Gain [6:0]G Gain Control 0260h X G Gain [6:0]Contrast Cont.0360h X

Contrast [6:0]

DAC10480h DAC 1[7:0]DAC20580h DAC 2[7:0]DAC30680h DAC 3[7:0]DAC40780h DAC 4[7:0]DC Offset/OSD Cont.0815h X X X OSD_Cont.

[1:0]DC_Offset [2:0]

Global Control 0900h X X O DCF4DCF1–3

O PS BV Increment Mode 0A 00h X X X X X X O INCR VBL/00R 0B 04h X X X X CLMP DAC4VBL 00R Software Reset

00h

SRST

Pre-Amp Interface Registers

Red Channel Gain Control Register (I 2C address 00h)Register name:R Gain Control (00h)Bit 7Bit 0RSV

RG6

RG5

RG4

RG3

RG2

RG1

RG0

Bits 6–0:Red Channel Gain Control.These seven bits de-termine the gain for the Red Channel.

Bit 7:Reserved.Blue Channel Gain Control Register (I 2C address 01h)Register name:B Gain Control (01h)Bit 7Bit 0RSV

BG6

BG5

BG4

BG3

BG2

BG1

BG0

Bits 6–0:Blue Channel Gain Control.These seven bits

determine the gain for the Blue Channel.

Bit 7:Reserved.Green Channel Gain Control Register (I 2C address 02h)Register name:G Gain Control (02h)Bit 7Bit 0RSV

GG6

GG5

GG4

GG3

GG2

GG1

GG0

Bits 6–0:Green Channel Gain Control.These seven bits

determine the gain for the Green Channel.

Bit 7:Reserved.

Contrast Control Register (I 2C address 03h)Register name:Contrast Control (03h)Bit 7Bit 0RSV

CG6

CG5

CG4

CG3

CG2

CG1

CG0

Bits 6–0:Contrast Control.These seven bits vary the gain

of all three channels.

Bit 7:Reserved.

DAC Interface Register Definitions

DAC 1Register (I 2C address 04h)Register name:DAC 1(04h)Bit 7

Bit 0

D1–7D1–6D1–5D1–4D1–3D1–2D1–1D1–0Bits 7–0:DAC 1.These eight bits determine the output

voltage of DAC 1.DAC 2Register (I 2C address 05h)Register name:DAC 2(05h)Bit 7

Bit 0

D2–7D2–6D2–5D2–4D2–3D2–2D2–1D2–0Bits 7–0:DAC 2.These eight bits determine the output

voltage of DAC 2.

L M 1262

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DAC Interface Register Definitions (Continued)

DAC3Register(I2C address06h)

Bit7Bit0 D3–7D3–6D3–5D3–4D3–3D3–2D3–1D3–0 Bits7–0:DAC3.These eight bits determine the output voltage of DAC3.

DAC4Register(I2C address07h)

Bit7Bit0 D4–7D4–6D4–5D4–4D4–3D4–2D4–1D4–0 Bits7–0:DAC4.These eight bits determine the output voltage of DAC4.

DC Offset and OSD Contrast Control Register(I2C ad-dress08h)

Bit7Bit0 RSV RSV RSV OSDC1OSDC0DC2DC1DC0 Bits2–0:DC Offset Control.These three bits determine the active video DC offset to all three channels.

Bits4–3:OSD Contrast Control.These two bits determine the contrast level of the digital OSD information. Bits7–5:Reserved.

Global Video Control Register(I2C address09h) Register name:Global Control(09h)

Bit7Bit0 RSV RSV0DCF4DCF1–30PS BV Bit0:Blank Video.When this bit is a one,blank the video output.When this bit is a zero allow normal

video out.

Bit1:Power Save.When this bit is a one,shut down the analog circuits to support sleep mode.When

this bit is a zero enable the analog circuits for

normal operation.

Bit2:MUST BE SET TO“0”FOR PROPER OPERA-TION.

Bit3:DAC1–3Configuration.When this bit is a zero the DAC outputs of DAC1–3are full scale

(0V–4.5V).When this bit is1,the range of

DAC1–3are halved(0V–2.25V).

Bit4:DAC4Configuration.When this bit is a zero the DAC4output is not mixed with the other DAC

outputs.When the bit is one,50%of the DAC4

output is added to DAC1–3.

Bit5:MUST BE SET TO“0”FOR PROPER OPERA-TION.

Bits7–6:Reserved.

Increment Mode Register(I2C address0Ah)

Bit7Bit0

RSV RSV RSV RSV RSV RSV0INCR

Bit0:Increment Enable.When set to a“0”,the default

value,the increment mode is enabled.This al-

lows the registers to be updated sequentially by

sending another block of data.

Bit1:MUST BE SET TO“0”FOR PROPER OPERA-

TION.

Bits7–2:Reserved.

Clamp Polarity,Vertical Blanking,and OSD Control(I2C

address0Bh)

Bit7Bit0

RSV RSV RSV RSV CLMP DAC4VBL OOR

Bit0:OSD Only Register:When this bit is0(default)

normal video operation is assumed.When this bit

is1,the video is blanked,only the OSD window is

displayed(used for“out-of-range”condition).

Bit1:Vertical Blank Enable:When this bit is set to1the

vertical blanking pulse is OR’d with the horizontal

blank pulse at the preamplifier output,to blank

the video during both the vertical and horizontal

retrace.I2C changes for contrast and DAC4will

only be updated during vertical retrace period.

When this bit is set to0(default)the internal

vertical blanking is disabled(horizontal blanking

is not affected)and I2C changes for contrast and

DAC4occur anytime in the video field.NOTE:If

there is no vertical signal to the LM1262,this bit

must be set to a0for proper operation.

Bit2:DAC4I/O Switch:When this bit is set to1(de-

fault)DAC4output is enabled.When this bit is set

to a0the DAC4output is disabled and pin13is

used for the vertical blank input.DAC4can still be

connected internally to DAC1-3.When both bits1

and2are set to1vertical blanking will be stripped

from the sandcastle pulse at pin23.For proper

detection of the sandcastle pulse the CLMP bit

(bit3)must be set to a0,positive polarity for the

clamp input.

Bit3:Determines the polarity of the clamp signal used

by the LM1262,“0”(default)is a positive clamp

signal,“1”is a negative going clamp signal.

Bits7–4:Reserved.

Software Reset Register(I2C address0Fh)

Bit7Bit0

RSV RSV RSV RSV RSV RSV RSV SRST

Bit0:Software Reset.Setting this bit causes a software

reset.All registers(except this one)are loaded

with their default values.All operations currently

in progress are aborted(except for I2C transac-

tions).This bit automatically clears itself when the

reset has been completed.

Bits7–1:Reserved.

LM1262

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Physical Dimensions

inches (millimeters)unless otherwise noted

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2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.

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Tel:81-3-5639-7560Fax:81-3-5639-7507

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Order Number LM1262NA NS Package Number N24D

L M 1262200M H z I 2C C o m p a t i b l e R G B V i d e o A m p l i f i e r S y s t e m w i t h O S D a n d D A C s

National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.