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CY7C462A中文资料

Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs

CY7C460A/CY7C462A CY7C464A/CY7C466A

Features

?High-speed, low-power, first-in first-out (FIFO)memories

?8K x 9 FIFO (CY7C460A)?16K x 9 FIFO (CY7C462A)?32K x 9 FIFO (CY7C464A)?64K x 9 FIFO (CY7C466A)

?10-ns access times, 20-ns read/write cycle times ?High-speed 50-MHz read/write independent of depth/width

?Low operating power —I CC = 60 mA —I SB =8 mA

?Asynchronous read/write ?Empty and Full flags

?Half Full flag (in standalone mode)?Retransmit (in standalone mode)?TTL-compatible

?Width and Depth Expansion Capability ?5V ± 10% supply

?PLCC, LCC, 300-mil and 600-mil DIP packaging ?Three-state outputs

?Pin compatible density upgrade to CY7C42X/46X family ?

Pin compatible and functionally equivalent to IDT7205, IDT7206, IDT7207, IDT7208

Functional Description

The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in first-out (FIFO) memories. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent over-run and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another by passing tokens.

The read and write operations may be asynchronous; each can occur at a rate of up to 50 MHz. The write operation occurs when the Write (W) signal is LOW. Read occurs when Read (R) goes LOW. The nine data outputs go to the high-imped-ance state when R is HIGH.

A Half Full (HF) output flag is provided that is valid in the stan-dalone (single device) and width expansion configurations. In the depth expansion configuration, this pin provides the ex-pansion out (XO) information that is used to tell the next FIFO that it will be activated.

In the standalone and width expansion configurations, a LOW on the Retransmit (RT) input causes the FIFOs to retransmit the data. Read Enable (R) and Write Enable (W) must both be HIGH during a retransmit cycle, and then R is used to access the data.

The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are fabricated using Cypress ’s advanced 0.5μ RAM3 CMOS tech-nology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and the use of guard rings.

32K x Logic Block Diagram

Pin Configurations

12345678910111215

161718192024

2221

1314

282726Top View

DIP W D 8D 3D 2D 1D 0XI FF Q 0Q 1Q 2GND

V CC D 4FL/RT MR EF XO/HF Q 7R

PLCC/LCC Top View

Q 3Q 8D 5D 6D 7

Q 6Q 5Q 44321

323130

1415161718192056789101112

1329

2827

2625242322

21FL/RT MR EF XO/HF Q 7D 6Q 6

D 7NC READ CONTROL

WRITE CONTROL

WRITE POINTER

RESET LOGIC

EXPANSION LOGIC

RAM ARRAY 8K x 916K x 99DATAINPUTS (D 0?D 8)

THREE –STATE BUFFERS

DATAOUTPUTS

(Q 0-Q 8)

READ POINTER

FLAG LOGIC R

XI EF FF

XO/HF MR

FL/RT

D 2D 1

D 0XI FF Q 0Q 1

NC Q 2

D D W

N C

V D D 38c c 45Q Q G N D

N C

Q Q 3845

C46XA –1

C46XA –2

C46XA –3

7C460A 7C462A 7C464A 7C460A

7C462A 7C464A 64K x 9

7C466A

DUAL PORT 元器件交易网https://www.wendangku.net/doc/7512384145.html,

Maximum Ratings [1]

(Above which the useful life may be impaired. For user guide-lines, not tested.)

Storage Temperature..................................–65°C to +150°C Ambient Temperature with

Power Applied.............................................–55°C to +125°C Supply Voltage to Ground Potential...............–0.5V to +7.0V DC Voltage Applied to Outputs

in High Z State...............................................–0.5V to +7.0V DC Input Voltage............................................–0.5V to +7.0V Power Dissipation..........................................................1.0W Output Current, into Outputs (LOW)............................20 mA Static Discharge Voltage.. (2001)

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Selection Guide

7C460A-10 7C462A-10 7C464A-10 7C466A-107C460A-15

7C462A-15

7C464A-15

7C466A-15

7C460A-25

7C462A-25

7C464A-25

7C466A-25

Frequency (MHz)504028.5 Maximum Access Time (ns)101525

Operating Range

Range

Ambient

Temperature V CC

Commercial0°C to + 70°C 5V ± 10%

Industrial–40°C to +85°C5V ± 10%

Military[2]–55°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range[3]

Parameter Description Test Conditions 7C460A/462A/464A/466A

(-10,-15,-25)

Unit Min.Max.

V OH Output HIGH Voltage V CC = Min., I OH = ?2.0 mA 2.4V V OL Output LOW Voltage V CC = Min., I OL = 8.0 mA0.4V V IH Input HIGH Voltage 2.2V CC V V IL Input LOW Voltage?0.50.8V I IX Input Leakage Current GND < V I < V CC–10+10μA I OZ Output Leakage Current R > V IH, GND < V O < V CC–10+10μA I CC Operating Current V CC = Max.,

I OUT = 0 mA, Freq. = 20 MHz

60mA I SB Standby Current All Inputs = V IH min.8mA Capacitance[5]

Parameter Description Test Conditions Max.Unit

C IN Input Capacitance T A = 25°C, f = 1 MHz,

V CC = 4.5V 10pF

C OUT Output Capacitance12pF Notes:

1.The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

2.T A is the “instant on” case temperature.

3.See the last page of this specification for Group A subgroup testing information.

4.For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.

5.Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

3.0V

5V OUTPUT

R1 500?

R2333?

30pF INCLUDING JIG AND SCOPE GND

90%10%

≤5ns

5V OUTPUT

R1 500?

R2333?

5pF

INCLUDING JIG AND SCOPE

OUTPUT 2V

Equivalent to:

TH é V ENIN EQUIVALENT

(b)

C460A –4

C460A –5

C460A –6

(a)ALL INPUT PULSES 200?

Switching Characteristics Over the Operating Range [3, 6]

Parameter Description

7C460A-10

7C462A-107C464A-107C466A-10

7C460A-157C462A-157C464A-157C466A-157C460A-257C462A-257C464A-257C466A-25Unit Min.Max.

Min.Max.

t RC Read Cycle Time 20

ns t A Access Time 10

25ns t RR Read Recovery Time 101010ns t PR Read Pulse Width 101525ns t LZR Read LOW to Low Z 333ns t DVR [7]Data Valid After Read HIGH 3

ns t HZR [7]Read HIGH to High Z 15

ns t WC Write Cycle Time 202535ns t PW Write Pulse Width 101525ns t HWZ Write HIGH to Low Z 555ns t WR Write Recovery Time 101010ns t SD Data Set-Up Time 999ns t HD Data Hold Time 000ns t MRSC MR Cycle Time 202535ns t PMR MR Pulse Width 101525ns t RMR MR Recovery Time 101010ns t RPW Read HIGH to MR HIGH 101525ns t WPW Write HIGH to MR HIGH 101525ns t RTC Retransmit Cycle Time 202535ns t PRT Retransmit Pulse Width 101525ns t RTR Retransmit Recovery Time 10

ns t EFL MR to EF LOW 202535ns t HFH MR to HF HIGH 202535ns t FFH MR to FF HIGH 202535ns t REF Read LOW to EF LOW 101525ns t RFF

Read HIGH to FF HIGH

Notes:

6.Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified I OL /I OH and 30-pF load

capacitance, as in part (a) of AC T est Loads, unless otherwise specified.7.t HZR and t DVR use capacitance loading as in part (b) of AC T est Loads.

t WEF Write HIGH to EF HIGH101525ns t WFF Write LOW to FF LOW101525ns t WHF Write LOW to HF LOW101535ns t RHF Read HIGH to HF HIGH101535ns t RAE Effective Read from Write

HIGH

101525ns

t RPE Effective Read Pulse Width

After EF HIGH

101525ns

t WAF Effective Write from Read

HIGH

101525ns

t WPF Effective Write Pulse

Width After FF HIGH

101525ns

t XOL Expansion Out LOW

Delay from Clock

101525ns

t XOH Expansion Out HIGH

Delay from Clock 101525ns

Switching Characteristics Over the Operating Range[3, 6] (continued)

Parameter Description

7C460A-10

7C462A-10

7C464A-10

7C466A-10

7C460A-15

7C462A-15

7C464A-15

7C466A-15

7C460A-25

7C462A-25

7C464A-25

7C466A-25

Unit Min.Max.Min.Max.Min.Max.

Switching Waveforms [7]

Notes:

8. A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe

transition causes a LOW-to-HIGH flag transition.9.W and R = V IH around the rising edge of MR.10.t MSRC = t PMR + t RMR

Asynchronous Read and Write

C460A –7

DATA VALID

DATA VALID DATA VALID DATA VALID t SD

t HD

t RC

t PR

t A

t RR t A

t LZR

t DVR t HZR

t WC

t PW

t WR

Q 0?Q 8

D 0?D 8

t SD

t HD

t PW

Master Reset

MR R,W

t MRSC t PMR

t EFL t HFH

t FFH

t RPW t WPW

t RMR

C460A –8

[10][9]

HALF FULL+1HALF FULL

HALF FULL

t WHF

t RHF

Half Full Flag

C460A –9

Notes:

11.t RTC = t PRT + t RTR .

12.EF, HF, and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at t RTC , except for the

CY7C46x-20 (Military), whose flags will be valid after t RTC + 10 ns.

Switching Waveforms [7] (continued)

Last Write to First ReadFull Flag

C460A –10

LAST WRITE

FIRST READ

ADDITIONAL READS

FIRST WRITE

t WFF

t RFF

Last READ to First WRITE Empty Flag

C460A –11

VALID

LAST READ

FIRST WRITE

ADDITIONAL WRITES

FIRST READ

VALID

t REF

t WEF

t A

W R

DATA OUT

Retransmit

C460A –12

t RTC

t PRT

t RTR

FL/RT

R,W

t RTC

t RTR

[11,12]

Switching Waveforms [7] (continued)

Full Flag and Write Data Flow-Through Mode

C460A –13

FF DATA IN

DATA OUT

DATA VALID

t WAF

t WPF

t WFF

t RFF

t SD

t HD

t A

Empty Flag and Read Data Flow-Through Mode

C460A –14

DATA IN

DATA OUT

DATA VALID

t RAE

t REF

t WEF

t HWZ

t A

t RPE

Architecture

Resetting the FIFO

Upon power-up, the FIFO must be reset with a master reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF), and Full flags (FF) being HIGH. Read (R) and Write (W) must be HIGH t RPW /t WPW before and t RMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. Writing Data to the FIFO

The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D 0?D 8) t SD before and t HD after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs t WEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW t WHF after the falling edge of W following the FIFO actu-ally being half full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing.The LOW-to-HIGH transition of HF occurs t RHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW t WFF after the falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH t RFF after a read from a full FIFO. Reading Data from the FIFO

The falling edge of R initiates a read cycle if the EF is not LOW.Data outputs (Q 0?Q 8) are in a high-impedance condition be-tween read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode.

When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. When the FIFO is empty, the outputs are in a high-impedance state. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read t WEF after a valid write. Retransmit

The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a

Note:

13.Expansion out of device 1 (XO 1) is connected to expansion in of device 2 (XI 2).

Switching Waveforms [7] (continued)

Expansion TimingDiagrams

C460A –15

XO 1(XI 2)

D 0?D 8

DATA VALID DATA DATA VALID

VALID

t XOL

t HD

t SD

t HD

t XOL

t LZR

t A

t DVR t A

t DVR t HZR

XO 1(XI 2)

Q 0?Q 8

C460A –16

t WR

t RR

DATA VALID

t XOH

[13]

number of writes equal-to-or-less-than the depth of the FIFO resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and t RTR after retransmit is LOW. With every read cycle after retransmit, pre-viously accessed data is read and the read pointer increment-ed until equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Standalone/Width Expansion Modes

Standalone and width expansion modes are set by grounding expansion in (XI) and tying first load (FL) to V CC prior to a MR cycle. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expan-sion mode, all control line inputs are common to all devices,and flag outputs from any device can be monitored.

Depth Expansion Mode (see Figure 1)

Depth expansion mode is entered when, during a MR cycle,expansion out (XO) of one device is connected to expansion in (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode, the first load (FL) input, when grounded, indicates that this is the first part to be loaded. All other devices must have this pin HIGH.To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and is pulsed LOW again when the last physical location is read.Only one FIFO is enabled for Read and one is enabled for Write at any given time. All other devices are in standby.FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created with word widths in increments of nine. When expanding in depth, a composite FF is created by ORing the FFs together.Likewise, a composite EF is created by ORing EFs together.mode.

Figure 1.Depth Expansion

CY7C460A CY7C462A CY7C464A W

RS XI

FF XI

FL EF

EMPTY

FULL

D 0-8

Q 0-89

V CC

*FIRSTDEVICE

C460A –17

CY7C460A CY7C462A CY7C464A CY7C460A CY7C462A CY7C464A CY7C466A

CY7C466A

Ordering Information 8K x 9 Asynchronous FIFO

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

10CY7C460A-10JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C460A-10PC P1528-Lead (600-Mil) Molded DIP

CY7C460A-10PTC P2128-Lead (300-Mil) Molded DIP

CY7C460A-10JI J6532-Lead Plastic Leaded Chip Carrier Industrial 15CY7C460A-15JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C460A-15PC P1528-Lead (600-Mil) Molded DIP

CY7C460A-15PTC P2128-Lead (300-Mil) Molded DIP

25CY7C460A-25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C460A-25PC P1528-Lead (600-Mil) Molded DIP

CY7C460A-25PTC P2128-Lead (300-Mil) Molded DIP

16K x 9 Asynchronous FIFO

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

10CY7C462A-10JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C462A-10PC P1528-Lead (600-Mil) Molded DIP

CY7C462A-10PTC P2128-Lead (300-Mil) Molded DIP

CY7C462A-10JI J6532-Lead Plastic Leaded Chip Carrier Industrial 15CY7C462A-15JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C462A-15PC P1528-Lead (600-Mil) Molded DIP

CY7C462A-15PTC P2128-Lead (300-Mil) Molded DIP

25CY7C462A-25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C462A-25PC P1528-Lead (600-Mil) Molded DIP

CY7C462A-25PTC P2128-Lead (300-Mil) Molded DIP

32K x 9 Asynchronous FIFO

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

10CY7C464A-10JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C464A-10PC P1528-Lead (600-Mil) Molded DIP

CY7C464A-10PTC P2128-Lead (300-Mil) Molded DIP

CY7C464A-10JI J6532-Lead Plastic Leaded Chip Carrier Industrial 15CY7C464A-15JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C464A-15PC P1528-Lead (600-Mil) Molded DIP

CY7C464A-15PTC P2128-Lead (300-Mil) Molded DIP

CY7C464A-15LMB L5532-Pin Rectangular Leadless Chip Carrier Military

25CY7C464A-25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C464A-25PC P1528-Lead (600-Mil) Molded DIP

CY7C464A-25PTC P2128-Lead (300-Mil) Molded DIP

Ordering Information (continued) 64K x 9 Asynchronous FIFO

Speed

(ns)Ordering Code Package

Name Package Type

Operating

Range

10CY7C466A-10JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C466A-10PC P1528-Lead (600-Mil) Molded DIP

CY7C466A-10PTC P2128-Lead (300-Mil) Molded DIP

CY7C466A-10JI J6532-Lead Plastic Leaded Chip Carrier Industrial 15CY7C466A-15JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C466A-15PC P1528-Lead (600-Mil) Molded DIP

CY7C466A-15PTC P2128-Lead (300-Mil) Molded DIP

CY7C466A-15LMB L5532-Pin Rectangular Leadless Chip Carrier Military

25CY7C466A-25JC J6532-Lead Plastic Leaded Chip Carrier Commercial CY7C466A-25PC P1528-Lead (600-Mil) Molded DIP

CY7C466A-25PTC P2128-Lead (300-Mil) Molded DIP

MILITARY SPECIFICATIONS Group A Subgroup Testing Document #: 38-00627-A

DC Characteristics

Parameter Subgroups V OH 1, 2, 3V OL 1, 2, 3V IH 1, 2, 3V IL Max.1, 2, 3I IX 1, 2, 3I CC 1, 2, 3I SB11, 2, 3I SB21, 2, 3I OS 1, 2, 3I OZ

1, 2, 3

Switching Characteristics

Parameter

Subgroups t RC 9, 10, 11t A 9, 10, 11t RR 9, 10, 11t PR 9, 10, 11t LZR 9, 10, 11t DVR 9, 10, 11t HZR 9, 10, 11t WC 9, 10, 11t PW 9, 10, 11t HWZ 9, 10, 11t WR 9, 10, 11t SD 9, 10, 11t HD 9, 10, 11t MRSC 9, 10, 11t PMR 9, 10, 11t RMR 9, 10, 11t RPW 9, 10, 11t WPW 9, 10, 11t RTC 9, 10, 11t PRT 9, 10, 11t RTR 9, 10, 11t EFL 9, 10, 11t HFH 9, 10, 11t FFH 9, 10, 11t REF 9, 10, 11t RFF 9, 10, 11t WEF 9, 10, 11t WFF 9, 10, 11t WHF 9, 10, 11t RHF 9, 10, 11t RAE 9, 10, 11t RPE 9, 10, 11t WAF 9, 10, 11t WPF 9, 10, 11t XOL 9, 10, 11t XOH

9, 10, 11

Package Diagrams

32-Lead Plastic Leaded Chip Carrier J65

51-85002-B

32-Pin Rectangular Leadless Chip Carrier L55

MIL-STD-1835 C-12

51-80068

Package Diagrams (continued)

28-Lead(600-Mil)Molded DIP P15

51-85017-A

28-Lead(300-Mil)Molded DIP P21

51-85014-B

Document Title: CY7C460A, CY7C462A, CY7C646A, CY7C466A Asynchronous, Cascadable 8K/16K/32K/64K X 9 FIFOs Document Number: 38-06011

REV.ECN NO.Issue

Date

Orig. of

Change Description of Change

**10647209/10/01SZV Change from Spec number 38-00627 to 38-06011

*A12226312/26/02RBI Power up requirements added to Maximum Ratings Information