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IC datasheet pdf-PCM1744,pdf(SoundPlus_ 24 Bits, 96kHz,Sampling Stereo Audio Digital-to-Analog Conve

SPECIFICATIONS

All specifications at +25°C, +V CC = +5V, f S = 44.1kHz, and 18-bit input data, SYSCLK = 384f S, unless otherwise noted.

NOTES: (1) Pins 1, 2, 3, 12, 13, 14: LRCIN, DIN, BCKIN, DM, FORMAT, SCKI. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

PIN ASSIGNMENTS

PIN NAME I/O FUNCTION

1(1)LRCIN IN Sample Rate Clock Input 2(1)DIN IN Audio Data Input

3(1)BCKIN IN Bit Clock Input for Audio Data.4

NC —No Connection

5CAP —Common Pin of Analog Output Amp 6V OUT R OUT Right-Channel Analog Output 7GND —Ground 8V CC —Power Supply

9V OUT L OUT Left-Channel Analog Output 10NC —No Connection 11NC —No Connection

12(2)

De-Emphasis Control

HIGH:De-emphasis ON LOW:De-emphasis OFF 13(2)TEST —Test Pin. Must be left open.14(1)

SCKI

System Clock Input (256f S or 384f S )

NOTE: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with internal pull-up.

PIN CONFIGURATION

TOP VIEW

SOIC

ABSOLUTE MAXIMUM RATINGS

Power Supply Voltage ......................................................................+6.5V +V CC to +V DD Difference ...................................................................±0.1V Input Logic Voltage ..................................................–0.3V to (V DD + 0.3V)Power Dissipation ..........................................................................290mW Operating Temperature Range .........................................–25°C to +85°C Storage Temperature......................................................–55°C to +125°C Lead Temperature (soldering, 5s)..................................................+260°C Thermal Resistance, θJA ..............................................................+90°C/W

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE SPECIFIED DRAWING TEMPERATURE

PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER (1)

RANGE MARKING NUMBER (2)MEDIA PCM1744

SO-14235–25°C to +85°C

PCM1744U PCM1744U Rails

PCM1744U

PCM1744U/2K

Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book, or visit the Burr-Brown web site at https://www.wendangku.net/doc/7112666639.html,. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1744U/2K” will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

LRCIN DIN BCKIN

NC CAP V OUT R GND

SCKI TEST DM NC NC V OUT L V CC

1234567

141312111098

PCM1744

TYPICAL PERFORMANCE CURVES

At T A = +25°C, +V CC = +5V, f S = 44.1kHz, SYSCLK = 256f S , unless otherwise noted.

DYNAMIC PERFORMANCE

THD+N vs TEMPERATURE

Temperature (°C)

T H D +N a t 0d B (%)

0.0090.0080.007

0.0060.0050.0040.0030.0020.001

0–25

100

T H D +N a t –60d B (%)

3.23.1

3.0

2.92.82.72.62.52.42.3

SNR, DYNAMIC RANGE vs TEMPERATURE

Temperature (°C)

S N R (d B )

9998

9695949399989796959493

–25

100

D y n a m i c R a n g e (d B )

THD+N vs POWER SUPPLY

V CC (V)

T H D +N a t 0d B (%)

0.0090.0080.0070.0060.0050.0040.0030.0020.001

4.5

4.75

5.0 5.25

5.5

T H D +N a t –60d B (%)

3.23.1

3.0

2.92.82.72.62.52.42.3

SNR, DYNAMIC RANGE vs POWER SUPPLY

V CC (V)

S N R (d B )

999897

96959493

9998979695

9493

4.5

4.75

5.0 5.25

5.5

D y n a m i c R a n g e (d B )

THD+N vs SAMPLING RATE

Sampling Rate (kHz)

T H D +N a t 0d B (%)

0.0160.014

0.0120.010.0080.006

0.004

5.24.7

4.23.73.22.72.2

44.1

88.2

T H D +N A T –60d B (%)

SNR, DYNAMIC RANGE vs SAMPLING RATE

Sampling Rate (kHz)

S N R (d B )

9897

969594939291908988

9796959493

9291908988

44.1

88.2

D y n a m i c R a n g e (d B )

TYPICAL PERFORMANCE CURVES

At T A = +25°C, +V CC = +V DD = +5V, f S = 44.1kHz, and 18-bit input data, SYSCLK = 384f S , unless otherwise noted.

DIGITAL FILTER

00.4536f S

1.3605f S

2.2675f S

3.1745f S

4.0815f S

–20

–40

–60

–80

–100

d B

OVERALL FREQUENCY CHARACTERISTIC

Frequency (Hz)

PASSBAND RIPPLE CHARACTERISTIC

–0.2

–0.4–0.6

–0.8

–1

0.1134f S

0.2268f S 0.3402f S

0.4535f S

d B

Frequency (Hz)

DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)Frequency (kHz)

L e v e l (d B

)

0–2–4

–6–8–10–12

DE-EMPHASIS FREQUENCY ERROR (44.1kHz)

Frequency (kHz)

r r o r (d B )

0.60.40.20.0–0.2–0.4–0.6

4999.8375

9999.67514999.5125

19999.35

FIGURE 1. I 2S Data Input Timing.

FIGURE 2. Audio Data Input Timing.

SYSTEM CLOCK

The system clock for PCM1744 must be either 256f S or 384f S , where f S is the audio sampling frequency (LRCIN),typically 32kHz, 44.1kHz, 48kHz, 88.2kHz or 96kHz. The system clock is used to operate the digital filter and the noise shaper. The system clock input (SCKI) is at pin 14. Timing conditions for SCKI are shown in Figure 3.

PCM1744 has a system clock detection circuit which auto-matically detects the frequency, either 256f S or 384f S . The system clock should be synchronized with LRCIN (pin 1),but PCM1744 can compensate for phase differences. If the phase difference between LRCIN and system clock is greater

FIGURE 3. System Clock Timing Requirements.

than ±6 bit clocks (BCKIN), the synchronization is per-formed automatically. The analog outputs are forced to a bipolar zero state (V CC /2) during the synchronization func-tion. Table I shows the typical system clock frequency inputs for the PCM1744.

SYSTEM CLOCK FREQUENCY (MHz)256f S 384f S 32kHz 8.19212.28844.1kHz 11.289616.934048kHz 12.28818.43288.2kHz 22.579233.86896kHz

24.576

36.864

SAMPLING RATE (LRCIN)

TABLE I. System Clock Frequencies vs Sampling Rate.TYPICAL CONNECTION DIAGRAM

Figure 4 illustrates the typical connection diagram for PCM1744 used in a stand-alone application.INPUT DATA FORMAT

PCM1744 can accept input data a 24-bit I 2S format, as shown in Figure 1.

FIGURE 5. Internal Power-On Reset Timing.

RESET

PCM1744 has an internal power-on reset circuit. The internal power-on reset initializes (resets) when the supply voltage V CC > 2.2V (typ). The power-on reset has an initialization period equal to 1024 system clock periods after V CC > 2.2V.During the initialization period, the outputs of the DAC are invalid, and the analog outputs are forced to V CC /2. Figure 5illustrates the power-on reset and reset-pin reset timing.DE-EMPHASIS CONTROL

Pin 12 (DM) enables PCM1744’s de-emphasis function. De-emphasis operates only at 44.1kHz.

DM 0De-emphasis OFF

De-emphasis ON (44.1kHz)

TABLE II. De-emphasis Control Selection.

APPLICATION

CONSIDERATIONS

DELAY TIME

There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1744:

T D = 11.125 x 1/f S

For f S = 44.1kHz, T D = 11.125/44.1kHz = 251.4μs Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc,etc., generally are not affected by delay time. For some professional applications such as broadcast audio for stu-dios, it is important for total delay time to be less than 2ms.OUTPUT FILTERING

For testing purposes all dynamic tests are done on the PCM1744 using a 20kHz low-pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and dynamic range readings than are found in the specifications. The low-pass filter removes out-of-band noise.Although it is not audible, it may affect dynamic specifica-tion numbers.

The performance of the internal low pass filter from DC to 24kHz is shown in Figure 6. The higher frequency roll-off of the filter is shown in Figure 7. If the user’s application has the PCM1744 driving a wideband amplifier, it is recom-mended to use an external low-pass filter. A simple 3rd-order filter is shown in Figure 8. For some applications, a passive RC filter or 2nd-order filter may be adequate.BYPASSING POWER SUPPLIES

The power supplies should be bypassed as close as possible to the unit. It is also recommended to include a 0.1μF ceramic capacitor in parallel with the 10μF tantalum bypass capacitor.

FIGURE 6. Low-Pass Filter Frequency Response.

FIGURE 7. Low-Pass Filter Wideband Frequency Response.

1050–5–10–15–20–25–30–35–40–45–50–5510

100

10k

100k

10M

Frequency (Hz)

d B

–60

INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(10Hz~10MHz)

FIGURE 9. 5-Level ?Σ Modulator Block Diagram.

FIGURE 10. Quantization Noise Spectrum.

THEORY OF OPERATION

The delta-sigma section of PCM1744 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 9. This 5-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modu-lator and the internal 8x interpolation filter is 96f S for a 384f S system clock, and 64f S for a 256f S system clock. The theoretical quantization noise performance of the 5-level

delta-sigma modulator is shown in Figure 10.

5-LEVEL

DELTA SIGMA MODULATOR

Frequency (kHz)

G a i n (–d B )

200–20

–40–60–80–100–120–140–160

PACKAGING INFORMATION

Orderable Device

Status (1)Package Type Package Drawing

Pins Package Qty Eco Plan (2)

Lead/Ball Finish MSL Peak Temp (3)PCM1744U ACTIVE SOIC D 1450

Green (RoHS &no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM PCM1744U/2K ACTIVE SOIC D 142000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCM1744U/2KG4ACTIVE SOIC D 142000Green (RoHS &

no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCM1744UG4

ACTIVE

SOIC

Green (RoHS &no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.

(2)

Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check https://www.wendangku.net/doc/7112666639.html,/productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.

Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)

(3)

MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

https://www.wendangku.net/doc/7112666639.html,

6-May-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Type Package Drawing Pins SPQ

Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)

P1(mm)W (mm)Pin1Quadrant PCM1744U/2K SOIC

2000330.0

16.4

6.59.0 2.1

8.0

16.0

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) PCM1744U/2K SOIC D142000346.0346.033.0

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