当前位置：文档库 › 93LC46B中文资料

93LC46B中文资料

FEATURES

?Single supply with operation down to 2.5V ?Low power CMOS technology - 1 mA active current (typical)

- 1 μ A standby current (maximum)?128 x 8 bit organization (93LC46A)?64 x 16 bit organization (93LC46B)

?Self-timed ERASE and WRITE cycles (including auto-erase)

?Automatic ERAL before WRAL

?Power on/off data protection circuitry ?Industry standard 3-wire serial interface

?Device status signal during ERASE/WRITE cycles ?Sequential READ function

?1,000,000 E/W cycles guaranteed ?Data retention > 200 years

?8-pin PDIP/SOIC and 8-pin TSSOP packages ?Available for the following temperature ranges: DESCRIPTION

The Microchip T echnology Inc. 93LC46AX/BX are 1K-bit, low voltage serial Electrically Erasable PROMs. The device memory is con?gured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BX is available in standard 8-pin DIP , 8-pin surface mount SOIC, and TSSOP packages. The 93LC46AX/BX are offered only in a 150-mil SOIC package.

-Commercial (C):0 ° C to +70 ° C -Industrial (I): -40 ° C to +85 °

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B

1.0ELECTRICAL

CHARACTERISTICS

1.1Maximum Ratings* Vcc...................................................................................7.0V All inputs and outputs w.r.t. Vss ................-0.6V to Vcc +1.0V Storage temperature.....................................-65°C to +150°C Ambient temp. with power applied.................-65°C to +125°C Soldering temperature of leads (10 seconds).............+300°C ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?cation is not implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.TABLE 1-1PIN FUNCTION TABLE Name Function

CS Chip Select

CLK Serial Data Clock

DI Serial Data Input

DO Serial Data Output

V SS Ground

NC No Connect

V CC Power Supply

TABLE 1-2DC AND AC ELECTRICAL CHARACTERISTICS

All parameters apply over the speci?ed operating ranges unless otherwise noted Commercial (C): V CC = +2.5V to +6.0V Tamb = 0°C to +70°C Industrial (I):V CC = +2.5V to +6.0V Tamb = -40°C to +85°C

Parameter Symbol Min.Max.Units Conditions

High level input voltage V IH1 2.0Vcc +1V 2.7V < V CC≤ 5.5V (Note 2) V IH20.7 V CC Vcc +1V V CC < 2.7V

Low level input voltage V IL1-0.30.8V V CC > 2.7V (Note 2) V IL2-0.30.2 Vcc V V CC < 2.7V

Low level output voltage V OL1—0.4V I OL = 2.1 mA; Vcc = 4.5V

V OL2—0.2V I OL =100 μA; Vcc = Vcc Min.

High level output voltage V OH1 2.4—V I OH = -400 μA; Vcc = 4.5V

V OH2V CC-0.2—V I OH = -100 μA; Vcc = Vcc Min.

Input leakage current I LI-1010μA V IN = V SS to Vcc Output leakage current I LO-1010μA V OUT = V SS to Vcc

Pin capacitance (all inputs/outputs)C IN, C OUT—7pF

V IN/V OUT = 0 V (Notes 1 & 2)

Tamb = +25°C, F CLK = 1 MHz

Operating current I CC write— 1.5mA

I CC read

— 1

500

μA

F CLK = 2 MHz; Vcc = 6.0V

F CLK = 1 MHz; Vcc = 3.0V

Standby current I CCS—1μA CS = Vss

Clock frequency F CLK—2

MHz

V CC > 4.5V

V CC < 4.5V

Clock high time T CKH250—ns

Clock low time T CKL250—ns

Chip select setup time T CSS50—ns Relative to CLK Chip select hold time T CSH0—ns Relative to CLK Chip select low time T CSL250—ns

Data input setup time T DIS100—ns Relative to CLK Data input hold time T DIH100—ns Relative to CLK Data output delay time T PD—400ns C L = 100 pF

Data output disable time T CZ—100ns C L = 100 pF (Note 2) Status valid time T SV—500ns C L = 100 pF

Program cycle time T WC—6ms ERASE/WRITE mode T EC—6ms ERAL mode

T WL—15ms WRAL mode

Endurance—1M—cycles25°C, V CC = 5.0V, Block Mode (Note 3)

Note 1:This parameter is tested at T amb = 25°C and Fclk = 1 MHz.

2:This parameter is periodically sampled and not 100% tested.

3:This application is not tested but guaranteed by characterization. For endurance estimates in a speci?c application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or website.

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B

2.0PIN DESCRIPTION

2.1Chip Select (CS)

A high level selects the device; a low level deselects the device and forces it into standby mode. However, a pro-gramming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro-gramming cycle is completed.

CS must be low for 250 ns minimum (T CSL) between consecutive instructions. If CS is low, the internal con-trol logic is held in a RESET status.

2.2Serial Clock (CLK)

The Serial Clock is used to synchronize the communi-cation between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T CKH) and clock low time (T CKL). This gives the controlling master freedom in preparing opcode, address, and data.

CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a ST ART condition).CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.

After detection of a ST ART condition the speci?ed num-ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (T able 2-1 and T able 2-2). CLK and DI then become don't care inputs waiting for a new ST ART condition to be detected.

2.3Data In (DI)

Data In (DI) is used to clock in a ST ART bit, opcode, address, and data synchronously with the CLK input.

2.4Data Out (DO)

Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (T PD after the posi-tive edge of CLK).

This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY sta-tus information is available on the DO pin if CS is brought high after being low for minimum chip select low time (T CSL) and an ERASE or WRITE operation has been initiated.

The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready.

TABLE 2-1INSTRUCTION SET FOR 93LC46A

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE111A6A5A4A3A2A1A0—(RDY/BSY)10

ERAL10010X X X X X—(RDY/BSY)10

EWDS10000X X X X X—HIGH-Z10

EWEN10011X X X X X—HIGH-Z10

READ110A6A5A4A3A2A1A0—D7 - D018

WRITE101A6A5A4A3A2A1A0D7 - D0(RDY/BSY)18

WRAL10001X X X X X D7 - D0(RDY/BSY)18 TABLE 2-2INSTRUCTION SET FOR 93LC46B

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE111A5A4A3A2A1A0—(RDY/BSY)9

ERAL10010X X X X—(RDY/BSY)9

EWDS10000X X X X—HIGH-Z9

EWEN10011X X X X—HIGH-Z9

READ110A5A4A3A2A1A0—D15 - D025

WRITE101A5A4A3A2A1A0D15 - D0(RDY/BSY)25

WRAL10001X X X X D15 - D0(RDY/BSY)25

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B

3.0FUNCTIONAL DESCRIPTION Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be veri?ed during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS.

3.1START Condition

The ST ART bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the ?rst time.

Before a ST ART condition is detected, CS, CLK, and DI may change in any combination (except to that of a ST ART condition), without resulting in any device oper-ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode.

An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new ST ART condition is detected.3.2Data In (DI) and Data Out (DO)

It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this con?guration, if A0 is a logic-high level, it is possible for a “bus con?ict”to occur during the “dummy zero” that precedes the READ operation. Under such a condition the voltage level seen at DO is unde?ned and will depend upon the relative impedances of DO and the signal source driv-ing A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.

3.3Data Protection

During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions.

The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional pro-tection against accidentally programming during nor-mal operation.

After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B

3.4ERASE

The ERASE instruction forces all data bits of the spec-i?ed address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle.

The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL). DO at logical “0” indicates that program-ming is still in progress. DO at logical “1” indicates that the register at the speci?ed address has been erased and the device is ready for another instruction.3.5Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle.

The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire ERAL cycle is com-plete.

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B

3.6ERASE/WRITE Disable and Enable

(EWDS/EWEN)

The 93LC46A/B powers up in the ERASE/WRITE Dis-able (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc-tion is executed or Vcc is removed from the device. T o protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming opera-tions. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.3.7READ

The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93LC46A) or 16-bit (93LC46B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the speci?ed time delay (T PD). Sequential read is possible when CS is held high. The memory data will automati-cally cycle to the next register and output sequentially.

FIGURE 3-6:READ TIMING CS

CLK

DI DO

110An???A0

HIGH-Z

0Dx???D0Dx???D0???

Dx D0

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B

3.8WRITE

The WRITE instruction is followed by 8 bits (93LC46A) or 16 bits (93LC46B) of data which are written into the speci?ed address. After the last data bit is put on the DI pin, the falling edge of CS initiates the self-timed auto-erase and programming cycle.

The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the speci?ed address has been written with the data speci?ed and the device is ready for another instruc-tion.3.9Write All (WRAL)

The Write All (WRAL) instruction will write the entire memory array with the data speci?ed in the command. The WRAL cycle is completely self-timed and com-mences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status.

The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL).

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B Array NOTES:

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B Array NOTES:

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B Array NOTES:

元器件交易网https://www.wendangku.net/doc/821227231.html,

93LC46A/B Array

93LC46A/B PRODUCT IDENTIFICATION SYSTEM

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Y our local Microchip sales of?ce.

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

AMERICAS

Corporate Of?ce

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: https://www.wendangku.net/doc/821227231.html, Atlanta

Microchip T echnology Inc.

500 Sugar Mill Road, Suite 200B Atlanta, GA 30350

Tel: 770-640-0034 Fax: 770-640-0307 Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

T el: 508-480-9990 Fax: 508-480-8575 Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 630-285-0071 Fax: 630-285-0075 Dallas

Microchip T echnology Inc.

14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809

Tel: 972-991-7177 Fax: 972-991-8588 Dayton

Microchip T echnology Inc.

Two Prestige Place, Suite 150 Miamisburg, OH 45342

Tel: 937-291-1654 Fax: 937-291-9175 Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 714-263-1888 Fax: 714-263-1338 New York

Microchip T echnology Inc.

150 Motor Parkway, Suite 416 Hauppauge, NY 11788

T el: 516-273-5305 Fax: 516-273-5335 San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

T el: 408-436-7950 Fax: 408-436-7955 Toronto

Microchip Technology Inc.

5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253ASIA/PACIFIC

Hong Kong

Microchip Asia Paci?c

RM 3801B, Tower T wo

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2-401-1200 Fax: 852-2-401-3431

India

Microchip Technology India

No. 6, Legacy, Convent Road

Bangalore 560 025, India

T el: 91-80-229-0061 Fax: 91-80-229-0062

Korea

Microchip Technology Korea

168-1, Y oungbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip Technology

RM 406 Shanghai Golden Bridge Bldg.

2077 Y an’an Road West, Hongiao District

Shanghai, PRC 200335

T el: 86-21-6275-5700

Fax: 86 21-6275-5060

Singapore

Microchip T echnology Taiwan

Singapore Branch

200 Middle Road

#10-03 Prime Centre

Singapore 188980

T el: 65-334-8870 Fax: 65-334-8850

Taiwan, R.O.C

Microchip Technology Taiwan

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

T el: 886 2-717-7175 Fax: 886-2-545-0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Bourne End, Buckinghamshire SL8 5AJ

Tel: 44-1628-851077 Fax: 44-1628-850259

France

Arizona Microchip Technology SARL

Zone Industrielle de la Bonde

2 Rue du Buisson aux Fraises

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Müchen, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Arizona Microchip Technology SRL

Centro Direzionale Colleone

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-39-6899939 Fax: 39-39-6899883

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Y okohama

Kohoku-Ku, Y okohama

Kanagawa 222 Japan

Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122

5/8/97 Printed on recycled paper.

元器件交易网https://www.wendangku.net/doc/821227231.html,