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ICS8525中文资料

LVCMOS-TO -LVHSTL F ANOUT B UFFER

G ENERAL D ESCRIPTION

The ICS8525 is a low skew, high performance 1-to-4 LVCMOS-to-LVHSTL fanout buffer and a

member of the HiPerClockS? family of High Performance Clock Solutions from ICS. The ICS8525 has two selectable clock inputs that ac-cept LVCMOS or LVTTL input levels and translate them to 1.8V LVHSTL levels. The clock enable is internally synchro-nized to eliminate runt pulses on the outputs during asyn-chronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8525 ideal for those applications demanding well defined performance and repeatability.

F EATURES

?4 differential 1.8V LVHSTL outputs

?Selectable LVCMOS / LVTTL clock inputs for redundant and multiple frequency fanout applications ?Maximum output frequency up to 266MHz ?Translates LVCMOS and LVTTL levels to 1.8V LVHSTL levels

?Output skew: 35ps (maximum)?Part-to-part skew: 150ps (maximum)?Propagation delay: 1.9ns (maximum)?3.3V core, 1.8V operating supply

?0°C to 70°C ambient operating temperature

?Industrial temperature information available upon request

B LOCK D IAGRAM

P IN A SSIGNMENT

ICS8525

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm Package Body

G Package Top View

GND CLK_EN CLK_SEL

CLK0nc CLK1nc nc nc V DD

12345678910

20191817161514131211

Q0nQ0V DDO Q1nQ1Q2nQ2V DDO Q3nQ3

CLK0CLK1

LVCMOS-TO -LVHSTL F ANOUT B UFFER

T ABLE 2. P IN C HARACTERISTICS

T ABLE 1. P IN D ESCRIPTIONS

l o b m y S r

e t e m a r a P s

n o i t i d n o C t s e T m

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a c i p y T m

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K L C ,0K L C 4F p ,

N E _K L C L

E S _K L C 4

F p R P U L L U P r o t s i s e R p u l l u P t u p n I 15K ?R N

W O D L L U P r

o t s i s e R n w o d l l u P t u p n I 1

5K ?

e b m u N e m a N e

p y T n

o i t p i r c s e D 1D N G r e w o P .

d n u o r g o t t c

e n n o C .d n u o r g y l p p u s r e w o P 2N E _K L C t u p n I p u l l u P k

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e c r o

f e r a s t u p t u o Q n ,w o l d e c r o f e r a s t u p t u o Q ,W O L n e h W .t u p n i .

s l e v e l e c a f r e t n i L T T V L /S O M C V L 3L E S _K L C t u p n I n w o d l l u P .

t u p n i 1K L C s t c e l e s ,H G I H n e h W .t u p n i t c e l e s k c o l C .s l e v e l e c a f r e t n i L T T V L /S O M C V L .t u p n i 0K L C s t c e l e s ,W O L n e h W 40K L C t u p n I n w o d l l u P .t u p n i k c o l c L T T V L /S O M C V L 61K L C t u p n I n

w o d l l u P .t u p n i k c o l c L T T V L /S O M C V L 9,8,7,5c n d e s u n U .

t c e n n o c o N 01V D D r e w o P .V 3.3o t t c e n n o C .n i p y l p p u s e v i t i s o P 8

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e w o P .

V 8.1o t t c e c n n o C .s n i p y l p p u s t u p t u O 21,113Q ,3Q n t u p t u O .s l e v e l e c a f r e t n i L T S H V L .r i a p t u p t u o l a i t n e r e f f i D 51,412Q ,2Q n t u p t u O .s l e v e l e c a f r e t n i L T S H V L .r i a p t u p t u o l a i t n e r e f f i D 71,611Q ,1Q n t u p t u O .s l e v e l e c a f r e t n i L T S H V L .r i a p t u p t u o l a i t n e r e f f i D 02,910Q ,0Q n t u p t u O .

s l e v e l e c a f r e t n i L T S H V L .r i a p t u p t u o l a i t n e r e f f i D :E T O N p u l l u P d n a n w o d l l u P .

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LVCMOS-TO -LVHSTL F ANOUT B UFFER

T ABLE 3A. C ONTROL I NPUT F UNCTION T ABLE

T ABLE 3B. C LOCK I NPUT F UNCTION T ABLE

s t u p n I s

t u p t u O 1

K L C

r o 0K L C 3Q u r h t 0Q 3

Q n u r h t 0Q n 0W O L H G I H 1

G I H W

O L CLK0, CLK1

CLK_EN

nQ0 - nQ3Q0 - Q3

t u p n I s

t u p t u O N

E _K L C L

E S _K L C e

c r u o S

e t c e l e S 3Q u r h t 0Q 3Q n u r h t 0Q n 0

K L C W O L ;d e l b a s i D H G I H ;d e l b a s i D 011K L C W

O L ;d e l b a s i D H

G I H ;d e l b a s i D 1

K L C d

e l b a n E d

e l b a n E 111K L C d e l b a n E d

e l b a n E e g d e k c o l c t u p n i g n i l l a

f d n a

g n i s i r a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o o k c o l c e

h t ,s e h c t

i w s N E _K L C r e t f A .

1e r u g i F n i n w o h s s a .

B 3e l b a T n i d e b i r c s e d s a s t u p n i 1K L

C d n a 0K L C e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t ,e d o m e v i t c a e h t n I

LVCMOS-TO -LVHSTL F ANOUT B UFFER

A BSOLUTE M AXIMUM R ATINGS

Supply Voltage, V DDx

4.6V

Inputs, V I -0.5V to V DD + 0.5V Outputs, V O

-0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0lfpm)Storage Temperature, T STG

-65°C to 150°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat-ings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

T ABLE 4B. LVCMOS / LVTTL DC C HARACTERISTICS , V DD = 3.3V±5%, V DDO = 1.8V±0.2V, T A = 0°C TO 70°C

l o b m y S r e t e m a r a P s

n o i t i d n o C t s e T m

u m i n i M l

a c i p y T m u m i x a M s t i n U V H

I e

g a t l o V h g i H t u p n I 1K L C ,0K L C 2567.3V ,N E _K L C L E S _K L C 2567.3V V L

I e

g a t l o V w o L t u p n I 1K L C ,0K L C 3.0-3.1V ,N E _K L C L E S _K L C 3

.0-8.0V I H

I t

n e r r u C h g i H t u p n I ,1K L C ,0K L C L E S _K L C V D D V =N I V 564.3=051A μN E _K L C V D D V =N I V 564.3=5

A μI L

I t

n e r r u C w o L t u p n I ,1K L C ,0K L C L E S _K L C V D D V ,V 564.3=N I V 0=5-A μN

E _K L C V D D V ,V 564.3=N I V

0=0

51-A

μT ABLE 4C. LVHSTL DC C HARACTERISTICS , V DD = 3.3V±5%, V DDO = 1.8V±0.2V, T A = 0°C TO 70°C

l o b m y S r

e t e m a r a P s

n o i t i d n o C t s e T m

u m i n i M l

a c i p y T m

u m i x a M s t i n U V H O ;e g a t l o V h g i H t u p t u O 1

E T O N 12.1V V L O ;e g a t l o V w o L t u p t u O 1

E T O N 0

.0V V X O e

g a t l o V r e v o s s o r C t u p t u O V (x %04H O V -L O V +)L

O V (x %06H O V -L O V +)L

O V V G

N I W S k

a e P -o t -k a e P g

n i w S e g a t l o V t u p t u O 5

7.05

2.1V

05h t i w d e t a n i m r e t s t u p t u O :1E T O N ?.

D N G o t T ABL

E 4A. P OWER S UPPLY DC C HARACTERISTICS , V DD = 3.3V±5%, V DDO = 1.8V±0.2V, T A = 0°C TO 70°C

l o b m y S r

e t e m a r a P s

n o i t i d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s t i n U V D D e g a t l o V y l p p u S e v i t i s o P 531.33.3564.3V V O D D e g a t l o V y l p p u S t u p t u O 6

.18

.10.2V I D

D t

n e r r u C y l p p u S r e w o P 0

LVCMOS-TO -LVHSTL F ANOUT B UFFER

T ABLE 5. AC C HARACTERISTICS , V DD = 3.3V±5%, V DDO = 1.8V±0.2V, T A = 0°C TO 70°C

l o b m y S r

e t e m a r a P s n o i t i d n o C t s e T m u m i n i M l

a c i p y T m u m i x a M s t i n U f X A M y c n e u q e r F t u p t u O m u m i x a M 662z H M t D

P 1E T O N ;y a l e D n o i t a g a p o r P ?≤z

H M 6620

.19.1s n t )o (k s 4,2E T O N ;w e k S t u p t u O 53s p t )p p (k s 4,3E T O N ;w e k S t r a P -o t -t r a P 0

51s p t R e m i T e s i R t u p t u O z H M 05@%08o t %02003007s p t F

m i T l l a F t u p t u O z

H M 05@%08o t %020

030

07s p c d o e l c y C y t u D t u p t u O 540555%

e s i w r e h t o d e t o n s s e l n u z H M 662t a d e r u s a e m s r e t e m a r a p l l A .r e t t i j d d a t o n s e o d t r a p e h T .t u p t u o e h t n o r e t t i j e h t l a u q e l l i w t u p n i e h t n o r e t t i j e l c y c -o t -e l c y c e h T .

t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t u p n i e h t f o t n i o p %05e h t m o r f d e r u s a e M :1E T O N .s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e D :2E T O N .

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s t n i o p s s o r c l a i t n e r e f f i d e h t t a .

56d r a d n a t S C E D E J h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h T :4E T O N

LVCMOS-TO-LVHSTL F ANOUT B UFFER

PARAMETER MEASUREMENT INFORMATION

LVCMOS-TO-LVHSTL F ANOUT B UFFER

LVCMOS-TO -LVHSTL F ANOUT B UFFER

P OWER C ONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8525.Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8525 is the sum of the core power plus the power dissipated in the load(s).The following is the power dissipation for V DD = 3.3V + 5% = 3.465V, which gives worst case results.NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

?Power (core)MAX = V DD_MAX * I DD_MAX = 3.465V * 50mA = 173.25mW ?

Power (outputs)MAX = 32mW/Loaded Output pair

If all outputs are loaded, the total power is 4 x 32mW = 128mW

Total Power _MAX (3.465V, with all outputs switching) = 173.25mW + 128mW = 301.25mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature

θJA = junction-to-ambient thermal resistance

Pd_total = Total device power dissipation (example calculation is in section 1 above)T A = Ambient T emperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used

. Assuming a

moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.301W * 66.6°C/W = 90.05°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,and the type of board (single layer or multi-layer).

q JA by Velocity (Linear Feet per Minute)

200

500Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 6. Thermal Resistance q JA for 20-pin TSSOP , Forced Convection

LVCMOS-TO -LVHSTL F ANOUT B UFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.LVHSTL output driver circuit and termination are shown in Figure 8.

To calculate worst case power dissipation into the load, use the following equations which assume a 50? load, and a termination voltage of V DD

- 2V.

Pd_H is power dissipation when the output drives high.Pd_L is the power dissipation when the output drives low.Pd_H = (V OH_MAX /R L ) * (V

DD_MAX

- V

OH_MAX

)

Pd_L = (V

OL_MAX

/R L

) * (V

DD_MAX

- V

OL_MAX

)

?For logic high, V OUT

= V

OH_MAX

= V

DD_MAX

– 1.2V

For logic low, V

OUT

= V

OL_MAX

= V

DD_MAX

– 0.4V

Pd_H =(1.2V/50?) * (2V - 1.2V) = 19.2mW Pd_L =(0.4V/50?) * (2V - 0.4V) = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW

LVCMOS-TO -LVHSTL F ANOUT B UFFER

R ELIABILITY I NFORMATION

T RANSISTOR C OUNT

The transistor count for ICS8525 is: 484

T ABLE 7. θJA VS . A IR F LOW T ABLE

q JA by Velocity (Linear Feet per Minute)

200

500Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards

73.2°C/W

66.6°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

LVCMOS-TO -LVHSTL F ANOUT B UFFER

P ACKAGE O UTLINE - G S UFFIX

T ABLE 8. P ACKAGE D IMENSIONS

R EFERENCE D OCUMENT : JEDEC P UBLICATION 95, MO-153

O B M Y S s r e t e m i l l i M N

I M X

A M N 0

2A --02.11A 50.051.02A 08.050.1b 91.003.0c 90.002.0D 0

4.606.6E C

I S A B 04.61E 0

3.40

5.4e C

I S A B 56.0L 54.057.0α°0°8a

a a --0

1.0

Integrated Circuit

Systems, Inc.

ICS8525

L OW S KEW , 1-TO -4

LVCMOS-TO -LVHSTL F ANOUT B UFFER

T ABLE 9. O RDERING I NFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.r

e b m u N r e d r O /t r a P g

n i k r a M e g a k c a P t n u o C e r u t a r e p m e T G B 5258S C I G B 5258S C I P

O S S T d a e l 02e b u t r e p 27C °07o t C °0T

-G B 5258S C I G

B 5258S

C I l

e e R d n a e p a T n o P O S S T d a e l 020

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°07o t C °0