ESD Failure Mechanisms of Analog I/O Cells in0.18-μm CMOS Technology
Ming-Dou Ker,Senior Member,IEEE,Shih-Hung Chen,and Che-Hao Chuang
Abstract—Different electrostatic discharge(ESD)protection schemes have been investigated to?nd the optimal ESD protec-tion design for an analog input/output(I/O)buffer in0.18-μm 1.8-and3.3-V CMOS technology.Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to com-pare the protection ef?ciency in analog I/O applications,namely: 1)gate-driven NMOS;2)substrate-triggered?eld-oxide device, and3)substrate-triggered NMOS with dummy gate.From the experimental results,the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the0.18-μm CMOS process.Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins.An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress.The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was triggered to discharge the ESD current and cause damage under ND-mode ESD stress.
Index Terms—Analog I/O,electrostatic discharge(ESD),failure mechanism,input/output(I/O)cell,power-rail ESD clamp device.
I N DEEP submicrometer CMOS technology,electrostatic
discharge(ESD)protection has been an important concern on the reliability of IC products–.Due to the low breakdown voltage(BV)of the thinner gate oxide,an ef?-cient ESD protection circuit must be designed to clamp the overstress voltage across the gate oxide of internal circuits.A conventional ESD protection design for the digital input pin is shown in Fig.1.The gate-grounded NMOS(GGNMOS)and the gate-VDD PMOS(GDPMOS)are often designed with a large device dimension and a wider drain-contact-to-polygate layout spacing to sustain the desired ESD level,.The resistor R in the digital input ESD protection circuit is usually included to effectively protect the gate oxide of the input stage. However,the series resistance between the input pad and the
Manuscript received August24,2005;revised November24,2005.This work was supported by the SoC Technology Center,Industrial Technology Research Institute,Hsinchu,Taiwan,R.O.C.
M.-D.Ker is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics,National Chiao-Tung University,Hsinchu300,Taiwan, R.O.C.(e-mail:mdker@http://m.wendangku.net/doc/8f947efdaef8941ea76e0593.html).
S.-H.Chen is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics,National Chiao-Tung University,Hsinchu300,Taiwan, R.O.C.and also with the Electrostatic Discharge(ESD)and Product Engi-neering Department,SoC Technology Center,Industrial Technology Research Institute,Hsinchu310,Taiwan,R.O.C.(e-mail:SHChen@http://m.wendangku.net/doc/8f947efdaef8941ea76e0593.html.tw).
C.-H.Chuang is with the Electrostatic Discharge(ESD)and Product Engi-neering Department,SoC Technology Center,Industrial Technology Research Institute,Hsinchu310,Taiwan,R.O.C.
Digital Object Identi?er
Fig.1.Conventional ESD protection circuit for a digital input pin.GGNMOS
and GDPMOS are designed with a large device dimension to sustain the
Fig.2.ESD protection circuit for an analog I/O pin.The protection circuit
includes the P-cell,N-cell,and power-rail ESD clamp circuit.
input stage is forbidden for current-mode input signals or high-
frequency applications.Furthermore,the series resistance and
the large junction capacitance of ESD clamp devices cause a
long resistance–capacitance(RC)delay to the input signals;
therefore,such an ESD protection circuit is not suitable for
An ESD protection design for analog pins in0.35-μm CMOS
technology has been reported.The basic ESD protection
scheme for the analog input/output(I/O)pin is shown in Fig.2.
To reduce the input capacitance of the analog pin,N-cell and
P-cell are designed with smaller device dimensions.However, 1530-4388/$20.00?2006IEEE