SD60C32P中文资料

SD60C32/P, SD60C52/P

S e m i c o n d u c t o r

CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER

Description

The AUK 60C32/P 60C52/P is a high-performance micro controller fabricated with AUK high-density CMOS technology. The AUK CMOS technology combines the high speed and density characteristics of MOS with the low power attributes of CMOS.

The 60C52 contains a 8K×8 ROM, a 256×8 RAM, 32 I/O lines, three 16bit counter/timers, a six sourc two-priority level nested interrupt structure, a serial I/O port for either multi-processor communication, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.

In addition, the device has two software selectable modes of power reduction idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning.

The power-down mode saves the RAM contents but freezes the oscillator , causing all other chip function to be inoperative.

Features

?8-bit CPU optimized for control applications. ? MCS-51 fully compatible instruction set ? Pin-to-pin compatible with intel's 80C52/80C32. ? ONCE TM (ON-circuit emulation) mode ? 256 Bytes of on-chip data RAM. ? Power control modes

? 60C52 low power CPU only. -Idle mode

? 32 programmable I/O lines. -Power down mode

? Three 16bit timer/counters. ? 6 interrupt source

? TTL and CMOS compatible logic levels

? 64K external program memory space and data memory space.

Ordering Information

Type NO.Marking Package Code Type NO.Marking Package Code SD60C32SD60C32 PLCC44SD60C32P SD60C32DIP40

SD60C52SD60C52PLCC44SD60C52P SD60C52DIP40

Absolute Maximum Ratings

Characteristic Rating Unit Ambient temperature under bias 0 ~ +70?éStorage temperature- 65 ~ + 150?é

Voltage on any pin to V

SS - 0.5 ~ V

CC

+ 0.5V

Maximum I

OL

per I/O pin 15§ìPower dissipation 1.5W

Pin Configuration

Pin Description

: PIN 40 (DIP40), PIN 44 (PLCC44)

V

CC

Supply voltage during normal, Idle and power down operations.

: PIN 20 (DIP40), PIN 22 (PLCC44)

V

SS

Circuit ground.

Port 0 : PIN 32~39 (DIP40), PIN 36~43 (PLCC44)

Port 0 is an 8bit open drain bi-directional I/O port. As an output

port each pin can sink several LS TTL inputs. Port 0 pins that have 1's

written to them float, and in that state can be used as high impedance inputs.

Port 0 is also the multiplexed low-order address and data bus during accesses

to external program and data memory.

In this application it uses strong internal pullups when emitting 1's and source and sink several LS TTL inputs. Port 0 outputs the code bytes during program verification on the 60C52 external pullups resistors are required during program verification. Port 1 : PIN 1~8 (DIP40), PIN 2~9 (PLCC44)

Port 1 output buffers can drive LSI TTL inputs.

Port 1 is an 8bit bi-directional I/O port with internal pullups.

Port 1 pins that have 1's written to them are pulled high by the internal pullups,

and in that state can be used as inputs. As inputs, Port 1 pins that are externally

being pulled low will source current because of the internal pullups

Pin Description (Continued)

In addition, Port 1 serves the functions of the following special features of the 60C52.

Port Pin Alternate Function

P1.0 T2(External Count Input to Timer / Counter 2)

P1.1 T2EX(Timer / Counter 2 Capture/Reload Trigger and Direction Control)

Port 1 receives the low-order address bytes during ROM verification.

Port 2 : PIN 21~28 (40DIP), PIN 24~31 (44PLCC)

Port 2 is an 8-bit bi-directional I/O port with internal pullups. The port 2 output buffers can drive LS TTL inputs.

Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in

that state can be used as input.

As inputs, port 2 pins that are externally being pulled

low will source current because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external Program Memory

and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to

external data memory that use 8 bit addresses (MOVX @ Ri), port 2 emits the contents

of the P2 special function register

Port 3 : PIN 10~17 (DIP40), PIN 13~19 (PLCC44)

Port 3 is an 8bit bi-directional I/O port with internal pullups. The port 3 output buffers can drive LS TTL input. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current because of the pullups.

Port 3 also serves the function of various special feature of the MCS-51 Family,

as listed below :

RST: PIN 9 (DIP40), PIN 10 (PLCC44)

Reset input. A high on this pin for two machine cycles while the oscillator is running

resets the device. An internal pulldown resistor permits a power-on reset with

.

only a capacitor connected to V

CC

ALE: PIN 30 (DIP40), PIN 33 (PLCC44)

Address latch enable output pulse for latching the low byte of the address

during accesses to external memory.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,

and may be used for external timing or clocking purposes.

Note : However, that one ALE pulse is skipped during each access to external

data memory.

This pin is also the program pulse input PROG during EPROM programming.

PSEN : PIN 29 (DIP40), PIN 32 (PLCC44)

Program store enable is the read strobe to external program memory. When the 60C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external

data memory. PSEN is not activated during fetches from internal program memory.

EA: PIN 31 (DIP40), PIN 35 (PLCC44)

in order to enable the device

External access enable. EA must be strapped to V

SS

to fetch code from external program memory locations starting at 0000H up to FFFFH.

the device executes from internal program memory unless

If EA is strapped to V

CC

the program counter contains an address greater than 0FFFH.

XTAL1: PIN 19 (DIP40), PIN 21 (PLCC44)

Input to the Inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2: PIN 18 (DIP40), PIN 20 (PLCC44)

Output from the inverting oscillator amplifier

0 Crystal Oscillator

NC: PIN1, 12, 23, 34 (PLCC44)

Non connection pins.

Idle Mode

In the Idle mode, the CPU puts itself to sleep while all the on chip peripherals stay active.

The instruction that invokes the Idle mode is the last instruction executed in the normal operating mode before Idle mode is activated.

The content of the on-chip RAM and all the special function registers remain intact during

this mode. The Idle mode can be terminated either by any enabled interrupt, at which time the process is picked up at the interrupt service routine and continued, or by a hardware reset which starts the processor the same as a power on reset.

Power Down Mode

In the power down mode the oscillator is stopped, and the instruction that invokes power

down is the last instruction executed. The on-chip RAM and special function register

retain their values until the power down mode is terminated.

The only exit from power down is a hardware reset. Reset redefines the SFRs but does

not change the on-chip RAM. The reset should not be activated before V

CC

is restored

to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

The control bits for the reduced power modes are in the special function register PCON.

Table. Status of the external pins during Idle and power down modes.

Mode Program

Memory

ALE PSEN PORT 0PORT 1PORT 2PORT 3

Idle Internal11Data Data Data Data Idle External11Float Data Address Data Power

Down

Internal00Data Data Data Data Power

Down

External00Float Data Data Data

(T

= 0?é ~ 70?é or -40?é ~ 85?é, V = 5V ± 20%, V=0V)

(T

a = 0?é ~ 70?é or -40?é ~ 85?é, V

CC

= 5V ± 20%, V

SS

=0V)

12MHz CLOCK VARIABLE

CLOCK

SYSBOL FIGURE PARAMETER

MIN MAX MIN MAX

UNIT

1/t

CLCL Oscillator frequency : Speed Versions

60C32/60C52

3.516MHz

t LHLL 1ALE pulse width1272t

CLCL

-40§à

t AVLL 1Address valid to ALE low43t

CLCL

-40§à

t LLAX 1Address hold after ALE low53t

CLCL

-30§à

t LLIV 1ALE low to valid instruction in2344t

CLCL

-100§à

t LLPL 1ALE low to PSEN low53t

CLCL

-30§à

t PLPH 1PSEN pulse with2053t

CLCL

-45§à

t PLIV 1PSEN low to valid instruction in1453

CLCL

-105§à

t

PXIX

1Input instruction hold after PSEN00§à

t PXIZ 1Input instruction float after PSEN59t

CLCL

-25§à

t AVIV 1Address to valid instruction in3125t

CLCL

-105§à

t

PLAZ

1PSEN low to address float1010§àData Memory

t RLRH 2, 3RD pulse width4006t

CLCL

-100§à

t WLWH 2, 3WR pulse width4006t

CLCL

-100§à

t RLDV 2, 3RD low to valid data in2525t

CLCL

-165§à

t

RHDX

2, 3Data hold after RD00§à

t RHDZ 2, 3Data float after RD1072t

CLCL

-70§à

t LLDV 2, 3ALE low to valid data in5178t

CLCL

-150§à

t AVDV 2, 3Address to valid data in5859t

CLCL

-165§à

t LLWL 2, 3ALE low to RD or WR low2003003t

CLCL

-503t

CLCL

+50§à

t AVWL 2, 3Address valid to WR low or RD low2034t

CLCL

-130§à

t QVWX 2, 3Data valid to WR transition33t

CLCL

-50§à

t WHQX 2, 3Data hold after WR33t

CLCL

-50§à

t QVWH 2, 3Data valid to WR High4337t

CLCL

-150§à

t

RLAZ

2, 3RD low to address float00§à

t WHLH 2, 3RD or WR high to ALE high43123t

CLCL

-40t

CLCL

-40§à

External Clock

t

CHCX

4High time2020§à

t

CLCX

4Low time2020§à

t

CLCH

4Rise time2020§à

t

CHCL

4Fall time2020§à

Electrical Characteristics (Continued)

(T

a = 0?é ~ 70?é or -40?é ~ 85?é, V

CC

= 5V ± 20%, V

SS

=0V)

16MHz

CLOCK

VARIABLE CLOCK

SYMB OL FIGUR

E PARAMETER

MIN MAX MIN MAX

UNI

T

1/t

CLCL Oscillator frequency : Speed Versions

60C52/60C32

3.516MHz

t LHLL 1ALE pulse width852t

CLCL

-40§à

t AVLL 1Address valid to ALE low23t

CLCL

-40§à

t LLAX 1Address hold after ALE low33t

CLCL

-30§à

t LLIV 1ALE low to valid instruction in1504t

CLCL

-100§à

t LLPL 1ALE low to PSEN low23t

CLCL

-40§à

t PLPH 1PSEN pulse with1433t

CLCL

-45§à

t PLIV 1PSEN low to valid instruction in833

CLCL

-105§à

t

PXIX

1Input instruction hold after PSEN00§à

t PXIZ 1Input instruction float after PSEN38t

CLCL

-25§à

t AVTV 1Address to valid instruction in2085t

CLCL

-105§à

t

PLAZ

1PSEN low to address float1010§àData Memory

t RLRH 2, 3RD pulse width2756t

CLCL

-100§à

t WLWH 2, 3WR pulse width2756t

CLCL

-100§à

t RLDV 2, 3RD low to valid data in1485t

CLCL

-165§à

t

RHDX

2, 3Data hold after RD00§à

t RHDZ 2, 3Data float after RD552t

CLCL

-70§à

t LLDV 2, 3ALE low to valid data in3508t

CLCL

-150§à

t AVDV 2, 3Address to valid data in3989t

CLCL

-165§à

t LLWL 2, 3ALE low to RD or WR low1382383t

CLCL

-503t

CLCL

+50§à

t AVWL 2, 3Address valid to WR low or RD low1204t

CLCL

-130§à

t ZVWX 2, 3Data valid to WR transition13t

CLCL

-50§à

t WHQX 2, 3Data hold after WR13t

CLCL

-50§à

t QVWH 2, 3Data valid to WR High 2887t

CLCL

-150§à

t

RLAZ

2, 3RD low to address float00§à

t WHLH 2, 3RD or WR high to ALE high23103t

CLCL

-40t

CLCL

+40§à

External Clock

t

CHCX

4High time2020§à

t

CLCX

4Low time2020§à

t

CLCH

4Rise time2020§à

t CHCL 4Fall time2020§à

SD60C32/P SD60C52/P

Timing Diagram

I CC §ì4MH 8MH 12MHz 454035302520

15105

16MHz

TYP IDLE MODE

MAX IDLE MODE

TYP ACTIV

MAX ACTIVE MODE

FREQ AT XTAL1Figure 7.Icc vs. FREQ

Valid only within frequency specifications

of the device under test