COA参考资料
COA考试资料
前二章作业
1.计算机的四个基本功能（Functions）是什么？(P6带圆点处)
2.在计算机的top-level structure view中，四个structural components是什么？P10Figure1.4
3.谁提出了store-program concept?(P17)你能用汉语简单地描述这个存储程序的概念吗？
4.CPU的英文全称是什么(P9)？汉语意义是什么？P11CPU构造Figure1.5
5.ALU的英文全称是什么？汉语意义是什么？(P9)
6.Von Neumann的IAS机的五大部件都是什么？(P20带圆点处)
7.在第一章中我们认识到的四个结构性部件（第2题）与Von Neumann的IAS机（第6题）中部件
有本质差别吗？
8.Fundamental Computer Elements有哪几个（P28figure2.6）？它们与计算机的四个基本功能的关
系是什么？
9.Moore’s Law在中文翻译为什么？它描述了什么事物的一般规律？(P24double every18months)
10.本书的次标题和第二章第二节标题均为“Designing for Performance”,Performance主要指什么(P37
带圆点处)？Performance Balance的（balance）平衡要平衡什么（P38）？
11.本书作者将他要研究的范围局限在“desktop,workstation,server“中，它们的中文名称是什么(桌
面体、工作站和服务器)？各自的工作范围是什么？(P37)
Chapter3Homework
1.PC means_（P53相关的IR、MAR、MBR、I/O、AR、I/OBR means牢记）
A.personal computer
B.programming controller
C.program counter
D.portable computer
PC——存放下一条指令的地址（address of next instruction）
MAR——存放本条指令的地址(address of the instruction)
MBR——存放取得的内容(comtents)
2.PC holds A
A.address of next instruction
B.next instruction
C.address of operand
D.operand
3.At the end of fetch cycle,MAR holds___(P54fetch cycle的步骤，对应12章的内容P422)
A.address of instruction
B.instruction
C.address of operand
D.operand
4.Interrupt process steps are__P61（相当重要）
A.suspending,resuming,branching&processing
B.branching,suspending,processing&resuming
C.suspending,branching,processing&resuming
D.processing,branching,resuming&suspending
5.A unsigned binary number is n bits,so it is can represent a value in the range between_________.（未带
符号）
A.0to n-1
B.1to n
C.0to2n-1
D.1to2n
6.The length of the address code is32bits,so addressing range(or the range of address)is
________________.(1K=210B1M=210K1G=210M)
A.4G
B.from–2G to2G
C.4G-1
D.from1to4G
7.There are three kinds of BUSes.Which is not belong to them?(P70Figure3.16)
A.address bus
B.system bus
C.data bus
D.control bus
第四章
一：选择题
1.The computer memory system refers to__(P97区分Internal Memory和External memory)_
A.RAM Internal Memory(内部存储器)——register,main memory,ache
B.ROM External memory（外部存储器）——disk
C.Main memory
D.Register,main memory,cache,external memory
2.If the word of memory is16bits,which the following answer is right?
A.The address width is16bits
B.The address width is related with16bits
C.The address width is not related with16bits
D.The address width is not less than16bits
3.The characteristics of internal memory compared to external memory(P100figure
4.1图中从上往下看：速度变
慢，容量增大，单位成本降低)
A.Big capacity,high speed,low cost
B.Big capacity,low speed,high cost
C.small capacity,high speed,high cost
D.small capacity,high speed,low cost
4．On address mapping of cache,any block of main memory can be mapped to
any line of cache,it is（P107~117）
总结映射：Direct Mapping——fixed main memory be mapped to fixed line of cache
Associative Mapping——any block of main memory can be mapped to any line of cache,
Set Associative Mapping——the data in any block of main memory can be mapped to fixed set any l(way)of cache
A)Associative Mapping B)Direct Mapping
C)Set Associative Mapping D)Random Mapping
P118总结写策略：write through——as well as to cache
Write back——when the difference between cache and main memory is found
5.Cache’s write-through polity means write operation to main memory_______.
A)as well as to cache
B)only when the cache is replaced
C)when the difference between cache and main memory is found
D)only when direct mapping is used
6.Cache’s write-back polity means write operation to main memory______________.
a)as well as to cache
b)only when the relative cache is replaced
c)when the difference between cache and main memory is found
d)only when using direct mapping
7.O n address mapping of cache,the data in any block of main memory can be mapped to fixed line of cache,it is _________________.
A)associative mapping B)direct mapping
C)set associative mapping D)random mapping
8.On address mapping of cache,the data in any block of main memory can be mapped to fixed set any line(way) of cache,it is_________________.
B)associative mapping B)direct mapping
D)set associative mapping D)random mapping
二：计算题(from page126)
Problem4.1,Problem4.3,Problem4.4,Problem4.5,,Problem4.7,Problem4.10
第五章作业
1.which type of memory is volatile?(P140Table5.1熟记此表)
A.ROM
B.E2PROM
C.RAM
D.flash memory
2.which type of memory has6-transistor structure?（P141Figure5.2(b)）
DRAM——is made with cells that store data as charge on capacitors(read refresh circuits but slower)
SRAM——binary values are stored using traditional flip-flop logic-gate configurations(faster&does not need refresh circuits)
A.DRAM
B.SRAM
C.ROM
D.EPROM
https://www.wendangku.net/doc/9c8132710.html,ing hamming code,its purpose is of one-bit error.(P150第二段)
A.detecting and correcting
B.detecting
C.correcting
D.none of all
4.Flash memory is（同1）.
A.read-only memory
B.read-mostly memory
C.read-write memory
D.volatile
5.Which answer about internal memory is not true?（P139）
A.RAM can be accessed at any time,but data would be lost when power down..
B.When accessing RAM,access time is non-relation with storage location.
C.In internal memory,data can’t be modified.
D.Each addressable location has a unique address.
Page161Problems: 5.4 5.5 5.6 5.7 5.8
第六章作业
一、选择题
P180~183
RAID0——四个数据盘：不能纠错
RAID1——四个数据盘和四个copy盘：have copy,mirror disk that contains the same data
RAID2——四个数据盘和三个校验盘：make use lf a parallel access technique(have copy)
RAID3——四个数据盘和一个校验盘：(同2)+only a single redundant（只要知道有错误，无需其位置）
RAID4——四个数据盘和一个校验盘：make use of independent access technique
RAID5——distributes the parity strips across all disks
RAID6——two different parity calculations are carried out and stored in separate blocks on different disks
1.RAID levels_________make use of an independent access technique.
A.2
B.3
C.4
D.all
2.In RAID4,to calculate the new parity,involves_reads_P18
3.(two reads&two writes)
A.one
B.two
C.three
D.four
3.During a read/write operation,the head is------P164最后一段
A.moving
B.stationary
C.rotating
D.above all
4.On a movable head system,the time it takes to position the head at the track is know as______.总结：（P171）seek time——the time it takes to position the head at the track
Rotational delay——the time it takes for the beginning of the sector to reach the head
Access time—the time it takes to get into position to read or write
A.seek time
B.rotational delay
C.access time
D.transfer time
5.RAID makes use of stored______information that enable the recovery of data lost due to a disk failure.（P175相关的1，2，3点内容）
A.parity
https://www.wendangku.net/doc/9c8132710.html,er data
C.OS
D.anyone
6.Recording and retrieval via_________called a head（P167）
A.conductive coil
B.aluminium
C.glass
D.Magnetic field
7.In Winchester disk track format,_________is a unique identifier or address used to locate a particular sector.
总结：ID field is a unique identifier or address used to locate a particular sector.
SYNCH byte is a special bit pattern that delimits the beginning of the field
Data field holds data
Disk Data Layout:Sectors,Tracks,Intersector gap(各自的功能P165~166)
A.SYNCH
B.Gap
C.ID field
D.Data field
8.Data are transferred to and from the disk in________.
A.track
B.sector
C.gap
D.cylinder
9.In_________,each logical strip is mapped to two separate physical disk.
A.RAID1
B.RAID2
C.RAID3
D.RAID4
10.With_________,the bits of an error correcting code are stored in the corresponding bit position on multiple parity disk.
A.RAID1
B.RAID2
C.RAID3
D.RAID4
11.The write-once read-many CD,known as___(P184~187)
A.CD-ROM
B.CD-R
C.CD-R/W
D.DVD
总结：CD/CD-ROM——read only,CD-R——write only,CD-RW——write many
DVD——read only
第七章
总结：Programmed I/O（P205）——CPU periodically reads&checks the status of I/O module until it find that the operation is complete
INTERRUPT-DRIVEN I/O——（P20911个步骤）processor to issue an I/O command to a module and then go on to do some other useful work
DMA（direct memory access）——the latter technique is more common and is referred to as cycle stealing,the DMA module in effect steals a bus cycle
1.“When the CPU issues a command to the I/O module,it must wait until the I/O operation is complete”.It is
programmed I/O,the word“wait”means___
a.the CPU stops and does nothing
b.the CPU does something else
c.the CPU periodically reads&checks the status of I/O module
d.the CPU wait the Interrupt Request Signal
2.See Figure7.7.To save(PSW&PC)and remainder onto stack,why the operations of restore them is
reversed?Because the operations of stack are__
a.first in first out
b.random
https://www.wendangku.net/doc/9c8132710.html,st in first out
d.sequenced
https://www.wendangku.net/doc/9c8132710.html,ing stack to save PC and remainder,the reason is_______P209~210figure7.7
a.some information needed for resuming the current program at the point of interrupt
b.when interrupt occurs,the instruction is not executed over,so the instruction at the point of interrupt
must be executed once again
c.the stack must get some information for LIFO
d.the start address of ISR must transfer by stack
4.The signals of interrupt request and acknowledgement exchange between CPU and requesting I/O module.
The reason of CPU’s acknowledgement is_____P210第3步
a.to let the I/O module remove request signal
b.to let CPU get the vector from data bus
c.both a&b
d.other aims
5.In DMA,the DMA module takes over the operations of data transferring from CPU,it means_--P216（抓住
关键词cycle stealing）第一段+带圆点处
a.the DMA module can fetch and execute instructions like CPU does
b.the DMA module can control the bus to transfer data to or from memory using stealing cycle
technique
c.the DMA module and CPU work together(co-operate)to transfer data into or from memory
d.when DMA module get ready,it issues interrupt request signal to CPU for getting interrupt service
6.Transfer data with I/O modules,3types of techniques can be used.Which one is not belong them?P204
a.Interrupt-driven I/O
b.programmed I/O
c.direct I/O access
d.DMA
Programmed I/O——sending a read or write command,and transferring the data
Interrupt-driven I/O——extracting data from main memory for output and storing data in main memory for input DMA——I/O module and main memory exchange data directly,without processor involvement
7.Think2types of different data transferring,to input a word from keyboard and to output a data block of some
sectors to harddisk.The best choice is to use___P204
a.interrupt-driven I/O and DMA
b.DMA and programmed I/O C.both interrupt-driven I/Os d.both DMAs
programmed I/O——read/write one word one time
interrupt-driven I/Os——read/write a block of data
DMA——read/write a block of data
https://www.wendangku.net/doc/9c8132710.html,paring with interrupt-driven I/O,DMA further raises the usage rate of CPU operations,because___P209
P219
a.it isn’t necessary for CPU to save&restore scene
b.it isn’t necessary for CPU to intervene the dada transfer
c.it isn’t necessary for CPU to read&check status repeatedly
d.both a and b
DMA与Programmed I/O比较则选C
第九章
1.Suppose bit long of two’s complement is5bits,which arithmetic operation brings OVERFLOW? P288(-2n-1~2n-1-1)
A.5+8
B.(-8)+(-8)
C.4-(-12)
D.15-7
2.Overflow occurs sometime in______arithmetic operation.P293
A.add
B.subtract
C.add and subtract
D.multiply
3.In twos complement,two positive integers(正整数)are added,when does overflow occurs?(同号相加，如果符号相反则overflow)P293
A.There is a carry
B.Sign bit is1
C.There is a carry,and sign bit is0
D.Can’t determine
4.An8-bit twos complement10010011is changed to a16-bit that equal to____.(n位码变为m位码，只需将原符号位向左重复写（m-n）位)
A.1000000010010011
B.0000000010010011
C.1111111110010011
D.111111110110110111
5.An8-bit twos complement00010011is changed to a16-bit that equal to____.（同4）
A.1000000010010011
B.0000000000010011
C.1111111100010011
D.1111111111101101
6.Booth’s algorithm is used for Twos complement___P301
Block Diagram of Hardware for Addition and Subtraction P296figure9.6
Flowchart for Unsigned Binary Multiplication P298figure9.9
Booth's Algorithm for Twos complement P301figure9.12
Flowchart for Unsigned Binary Division P305figure9.16
A.addition
B.subtraction
C.multiplication
D.division
7.In floating-point arithmetic,addition can divide to4steps:______.
A.load first operand,add second operand,check overflow and store result
https://www.wendangku.net/doc/9c8132710.html,pare exponent,shift significand,add significands and normalize
C.fetch instruction,indirectly address operand,execute instruction and interrupt
D.process scheduling states:create,get ready,is running and is blocked
8.In floating-point arithmetic,multiplication can divide to4steps:______.
A.load first operand,add second operand,check overflow and store result
B.fetch instruction,indirectly address operand,execute instruction and interrupt
C.process scheduling states:create,get ready,is running and is blocked
D.check for zero,add exponents,multiply significands,normalize,and round.
9.The main functions of ALU are?
A.Logic
B.Arithmetic
C.Logic and arithmetic
D.Only addition
10.Which is true?
A.Subtraction can not be finished by adder and complement circuits in ALU
B.Carry and overflow are not same
C.In twos complement,the negation of an integer can be formed with the following rules:
bitwise not(excluding the sign bit),and add1.
D.In twos complement,addition is normal binary addition,but monitor sign bit for overflow Chapter10and Chapter11(寻址方式)
P（383）Table11.1Basic Addressing Modes(disadvatage&advatage)
Immediate——no memory access in execution cycle,very fast,but value range limited and operand no-normal Direct——one times memory access in execution cycle,but address length(range)limited
Indirect——two times memory access(slow),operand normal,value range non-limited,address length(range)non-limited Register——no memory access(fast),operand normal(value no limited),address length limited(address range very litter) Register indirect——one times memory access operand normal(value range non-limited),address length non-limited(address length very large)
Displacement——one times memory access(value non-limited),address calculation complex
1:In instruction,the number of addresses is0,the operand(s)’address is implied,which is(are)in_______.p334 addresses is1——a second address must be implicit to AC
addresses is2——one address does double duty both an operand and a result
addresses is3——one address,two operands
A.accumulator
B.program counter
C.top of stack
D.any register
2:Which the following addressing mode can achieve the target of branch in program?(p387)
A.Direct addressing mode
B.Register addressing mode
C.Base-register addressing mode
D.Relative addressing mode
3:In index-register addressing mode,the address of operand is equal to
A.The content of base-register plus displacement
B.The content of index-register plus displacement
C.The content of program counter plus displacement
D.The content of AC plus displacement
4:The address of operand is in the instruction,it is_________?
A.Direct addressing mode
B.Register indirect addressing mode
C.Stack addressing mode
D.Displacement addressing mode
5:Which the following is not the area that the source and result operands can be stored in?(p331)
A.Main or virtual memory
B.CPU register
C.I/O device
D.Instruction
6:Compared with indirect addressing mode,the advantage of register indirect addressing mode is
https://www.wendangku.net/doc/9c8132710.html,rge address space
B.Multiple memory reference
C.Limit address space
D.Less memory access
7:With base-register ADDRESSING,the______________register can be used.
A.BASE
B.INDEX Relative addressing——PC
C.PC
D.ANY Indexing——Index-Register
8:The disadvantage of INDIRECT ADDRESSING is____________.
https://www.wendangku.net/doc/9c8132710.html,rge addressing range
B.no memory access
C.more memory access
https://www.wendangku.net/doc/9c8132710.html,rge value range
9:Which is not an advantage with REGISTER INDIRECT?
A.just one times of operand’s access
https://www.wendangku.net/doc/9c8132710.html,rge memory space
https://www.wendangku.net/doc/9c8132710.html,rge value range
D.no memory reference
10:The REGISTER ADDRESSING is very fast,but it has_________________.
A.very less value range
B.very less address space
C.more memory access
D.very complex address’calculating
11:The disadvantage of IMMEDIATE ADDRESSING is___________.
A.limited address range
B.more memory access
C.limit value range
D.less memory access
12:In instruction,the number of addresses is2,one address does double duty both_______________.
A.a result and the address of next instruction
B.an operand and a result
C.an operand and the address of next instruction
D.two closed operands
13.In instruction,the number of addresses is3,which are____
A.two operands and one result
B.two operands and an address of next instruction
C.one operand,one result and an address of next instruction
D.two operands and an address of next instruction
14.The address is known as a type of data,because it is represented by___(p337)
Address——unsigned integers
Numbers——integer or fixed point,fleating point,decimal
A.a number of floating point
B.a signed integer
C.an unsigned integer
D.a number of hexadecimal
15.Which is not a feature of Pentium.
https://www.wendangku.net/doc/9c8132710.html,plex and flex addressing
B.abundant instruction set
C.simple format and fixed instruction length
D.strong support to high language
16.Which is not a feature of Power PC.
A.less and simple addressing mode
B.basic and simple instruction set
C.variable instruction length and complex format
D.strong support to high language Chapter12and Chapter18
1.After the information flow of fetch subcycle,the content of MBR is_____________.
A.oprand
B.address of instruction
C.instruction
D.address of operand
2.After the information flow of instruction subcycle,the content of MBR is_____________.
A.oprand
B.address of instruction
C.instruction
D.address of operand
3.The worse factor that limits the performance of instruction pipeline is_________________.
A.conditional branch delaying the operation of target address
B.the stage number of pipeline can’t exceed6
C.two’s complement arithmetic too complex
D.general purpose registers too few
4.The most factor to affect instruction pipeline effectiveness is__________.
A.The number of stages
B.the number of instruction
C.the conditional branch instruction
D.the number of pipelines
5.RISC rejects______.(p463带圆点)
A.few,simple addressing modes
B.a limited and simple instruction set
C.few,simple instruction formats
D.a few number of general purpose registers
6.RISC rejects______.（同上题）
A.a large number of general-purpose registers
B.indirect addressing
C.a single instruction size
D.a small number of addressing mode
7.Which is NOT a characteristic of RISC processor.
A.a highly optimized pipeline.
B.Register to register operations
C.a large number of general-purpose registers
D.a complexed instruction format
8.Control unit use some input signals to produce control signals that open the gates of information paths and
let the micro-operations implement.Which is NOT the input signals of control unit/P585（带圆点）+P594（input signals——instruction register,the clock,flags,and control bus signals——interrupt signals and acknowledgments）
A.clock and flags
B.instruction register
C.interrupt request signal
D.memory read or write
9.Control unit use some output signals to cause some operations.Which is not included in the output signals?
（P585control signals within the processor and control signals to control bus)
A.signals that cause data movement
B.signals that activate specific functions(e.g.add/sub/…)
C.flags
D.read or write or acknowledgement
10.Symmetric Multi-Processor(SMP)system is tightly coupled by_(p646~647
NUMA——interconnect network and distributed memory)
A.high-speed data-link and distributed memory
B.shared RAIDs and high-speed data-link
C.distributed caches and shared memory
D.interconnect network and distributed memory
11.The SMP means__________.（P647）
SISD means single instruction,single data stream
SIMD means single instruction,multiple data stream
MIMD means multiple instruction,multiple data stream
A.Sharing Memory Processes
B.Split Memory to Parts
D.Stack and Memory Pointer D.Symmetric Multi-Processor
12.The“MESI”means states of____________.(P659)
A.Modified,Exclusive,Stored and Inclusive
B.Modified,Expected,Shared and Interrupted
C.Modified,Exclusive,Shared and Invalid
D.Moved,Exchanged,Shared and Invalid
13.The protocol“MESI”is also called____(P659)many readers but only one writer at a time
A.write back policy
B.write-update protocol
C.write-invalidate protocol
D.write through policy
Chapter12
1.Which register is user–visible but is not directly operated in8086?(p419图（b）)
A.DS
B.SP
C.IP
D.BP
2.The indirect sub-cycle is occurred_____________?（P420）Interrupt cycle在Execute cycle之后
A.before fetch sub-cycle
B.after execute sub-cycle
C.after interrupt sub-cycle
D.after fetch sub-cycle and before execute sub-cycle
3.Within indirect sub-cycle,the thing the CPU must do is______________?
A.fetch operand or store result
B.fetch operand’s address from memory
C.fetch next instruction from memory
D.nothing
4.In general,which register is used for relative addressing----the content in this register plus the A
supplied by instruction to make a target address in branch or loop instructions.（P387）
A.SP（stack pointer）
B.IR(inex-register)
C.BR(base register)
D.PC
5.The Memory Address Register connects to____________BUS.(MBR_DATA BUS)
A.system
B.address
C.data
D.control
6.The Memory Buffer Register links to________BUS.
A.system
B.address
C.data
D.control
7.After Indirect cycle,there is a______________cycle.(p420Figure12.4)
A.Fetch
B.Indirect
C.Execute
D.Interrupt
8.The Interrupt cycle is________________Execute cycle.(同上题)
A.always after
B.never after
C.sometime after
D.maybe before
9.The correct cycle sequence is_________________.（同上）
A.Fetch,Indirect,Execute and Interrupt
B.Fetch,Execute,Indirect and Interrupt
C.Fetch,Indirect,Interrupt and Execute
D.Indirect,Fetch,Execute and Interrup
10.The aim of the indirect cycle is to get__________________.
A.an operand
B.an instruction
C.an address of an instruction
D.an address of an operand
11.Which is not in the ALU?（P414figure12.2）
A.shifter
B.adder
https://www.wendangku.net/doc/9c8132710.html,plementer
D.Accumulator
12.The registers in the CPU is divided_____registers and________registers.(P414带圆点)
A.general purpose,user-visible
https://www.wendangku.net/doc/9c8132710.html,er-visible（P415）,control and status（P416）
C.data,address
D.general purpose,control and status
13.The Base register is a(n)__________register in8086.（P419figure12.3）
A.general purpose
B.data
C.address
D.control
14.The Instruction Pointer is a(n)__________register in8086.
A.general purpose
B.data
C.address
D.control