DiB9090M_Datasheet-v1.0

m

C o

n ?

d e

n t i

a l

f o r

D i g i s t r

e a m

Document Status

Version Date Author Modi?cations Version 1.0

Aug 6,2008

https://www.wendangku.net/doc/9517992956.html,ury

Initial Release

C o

n ?

d e

n t i

a l

f o r

D i g i s t r

e a m

Table of contents

Table of contents 3List of Figures 5List of Tables 61Description 72Features 73Applications

84Package

94.1Package Marking ...............

.....................................114.1.11st line:DiBcom logo ..............................................114.1.22nd line:Part Designator ............................................114.1.33rd line:Product version identi?cation .....................................114.1.44th line:Wafer lot traceability ..........................................114.1.55th line:Traceability information ...

..

...................................

115IOs Banks

126Operating conditions

136.1Power supplies characteristics .............................................136.2ESD characteristics ..................................................136.3Thermal information ..................................................136.4Power consumption ........

..........................................146.4.1Switching off the DiB9090M

..........................................

14

7IOs Electrical Speci?cation 157.1DC Speci?cations of Multi-Voltage I/O Buffers Operating under 3.3V .........................157.2DC Speci?cations of Multi-Voltage I/O Buffers Operating under 2.5V .........................157.3DC Speci?cations of Multi-Voltage I/O Buffers Operating under 1.8V . (15)

8Balls Description

179Functional Description

209.1Architecture Overview .................................................209.2Digital and sampling clocks .........

.....................................219.2.1Power-Up or Hardware Reset .........................................219.2.2Implementation dependent constraints .....................................219.2.3PLL .......................................................219.2.4ADC clock generator block ...........................................219.3RF Tuner ...................

.....................................239.3.1RXRF ......................................................239.3.2Mixer ......................................................239.3.3Baseband ....................................................239.3.4LO ........................................................239.3.5Crystal Oscillator ................................................249.3.6Bias ..................

.....................................

24

C o

n ?

d e

n t i

a l

f o r

D i g i s t r

e a m

9.3.7ADC .......................................................249.4Demodulator ....................

..................................259.4.1Analog AGC ..................................................259.4.2IQ Impairment Compensation .........................................259.4.3Surrounding noise compensation ........................................259.4.4Base band frequency offset compensation ...................................259.4.5Interpolation and Filtering ............................................259.4.6Guard time removal ...............................................259.4.7FFT &Phase ..................................................259.4.8Channel estimator ...............................................259.4.9Equalizer &FFT leakage compensation ....................................269.4.10Diversity combiner ...............................................269.4.11Viterbi Decoder .................................................279.4.12FEC .......................................................279.4.13TPS .......................................................279.4.14Synchronization control .............................................289.5DVB-H MAC ....................

..................................289.5.1RISC processors ................................................289.5.2PID ?ltering ...................................................289.5.3Section construction and CRC computation ..................................289.5.4Time slicing and power saving .........................................289.5.5RS decoder ...................................................2810Interfaces

2910.1Host Interface ...............

.......................................2910.1.1Functional description .............................................2910.1.2Physical interface description ..........................................3210.2Diversity connectivity ...........

.......................................4110.2.1Clock distribution ................................................4110.2.2Con?guration interfaces ............................................4210.2.3Diversity data interfaces ............................................4210.2.4Diversity IC enumeration process .......................................4210.3General purpose input/output interface .

.......................................4310.3.1Functional description ......

....

..........

.....

....................

43

C o

n ?

d e

n t i

a l

f o r

D i g i s t r

e a m

List of Figures

4.1DiB9090M BGA ballout ................................................94.2Package information .................................................104.3Re?ow Process ....................................................109.1Functional block diagram ...............................................209.2power up and down sequence ............................................219.3RF T uner Block Diagram ...............................................239.4Diversity Connectivity .....

............................................2710.1Host interfacing functional block diagram .......................................2910.2SRAM-like interface write accesses .........................................3410.3SRAM-like interface read accesses .........................................3510.4Parallel MPEG2output with gated clock using 188bytes output mode .......................3810.5Parallel MPEG2output with gated clock using 204bytes output mode .......................3810.6Parallel MPEG2output with clock enable using 188bytes output mode .......................3910.7Parallel MPEG2output with clock enable using 204bytes output mode .......................3910.8MPEG2serial output mode ..............................................4010.9MPEG2FIFO interface ................................................4010.10FIFO interface ....................................................4110.11

Diversity IC chain clock distribution ...................

(42)

C o

n ?

d e

n t i

a l

f o r

D i g i s t r

e a m

List of Tables

6.2Power Supplies Characteristics ............................................136.4ESD characteristics ..................................................136.6Thermal information .................................................136.8DiB9090M Power Consumption

............

......

.......................

..14

8.2Balls description ...................................................199.2Required Crystal Speci?cation ............................................219.4Demodulator Clock Con?guration ..........................................219.6Digital clock functional range .............................................219.8ADC clock range when derived directly from the external clock ...........................229.10ADC and digital clocks derived from some given references .............................2210.2Host Interface options ................................................3010.4Host interfaces table selection ............................................3210.6Host Bus functions multiplexing ...........................................3410.8SRAM like interface signals ..............................................3410.10SRAM-like interface pins mapping ..........................................3410.12SRAM like interface addresses description ......................................3410.14SPI functional signals .................................................3510.16SDIO 1bit functional signals .............................................3610.18SDIO 4bits functional signals ............................................3610.20JT AG Mapping on HOST_BUS ............................................3710.22I 2C default interface addresses ............................................3710.24DVB-T output mapping on HOST_BUS ........................................3810.26DVB-T output mapping on HOST_BUS ........................................4110.28Diversity outputs mapping ..............................................4210.30

GPIOs functional mapping ........

...

...........

(43)

C o

n ?

d e

n t i

a l

f o r

D i g i s t r

e a m

The package mechanical data are presented in the following ?gures:

Figure 4.2:Package information

The re?ow process of the DiB9090M follows Pb-free process of the IPC/JEDEC J-STD-020C standard as presented below:

Figure 4.3:Re?ow Process