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UCN5801A中文资料

5800AND5801 BiMOS II LATCHED DRIVERS

BiMOS II LATCHED DRIVERS Always order by complete part number, e.g.,UCN5801EP.

The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS

ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data (‘D’ type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry. The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or micropro-cessor I/O. The UCN5800A and UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight latched drivers.

The UCN5800A/L and UCN5801A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These second-generation devices are capable of much higher data input

rates and will typically operate at better than 5 MHz with a 5 V logic supply. Circuit operation at 12 V affords substantial improvement over the 5 MHz figure.

The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resis-tors. The bipolar Darlington outputs are suitable for directly driving

many peripheral/power loads: relays, lamps, solenoids, small dc motors, etc.

All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are

capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simul-taneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled

for higher load current capability.

The UCN5800A is furnished in a standard 14-pin DIP; the

UCN5800L and UCN5801LW in surface-mountable SOICs; the

UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the

UCN5801EP in a 28-lead PLCC.

FEATURES

s To 4.4 MHz Data Input Rate

s High-Voltage,

High-Current Outputs

s CMOS, NMOS,

TTL Compatible Inputs

s Output Transient Protection

s Internal Pull-Down Resistors

s Low-Power CMOS Latches

Automotive Capable

Data Sheet26180.10B 5800 AND

5801

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

5075100125150

2.5

0.5

A L L O W A

B L E P A

C K A G E

P O W E R D I S S I P A T I O N I N W A T T S

AMBIENT TEMPERATURE IN °C

2.0

1.5

1.0

25Dwg. GP-023-1

TYPICAL INPUT CIRCUIT

ELECTRICAL CHARACTERISTICS at T A = +25°C, V DD = 5 V (unless otherwise noted).

Limits Characteristic

Symbol Test Conditions Min.Typ.Max.Units Output Leakage Current

I CEX V CE = 50 V, T A = +25°C ——50μA V CE = 50 V, T A = +70°C

——100μA Collector-Emitter V CE(SAT)

I C = 100 mA —0.9 1.1V I C = 200 mA

— 1.1 1.3V I C = 350 mA, V DD = 7.0 V

— 1.3 1.6V Input Voltage

V IN(0)—— 1.0V V IN(1)

V DD = 12 V 10.5——V V DD = 10 V

8.5——V V DD = 5.0 V (See Note)

3.5——V Input Resistance

r IN

V DD = 12 V 50200—k ?V DD = 10 V 50300—k ?V DD = 5.0 V

50600—k ?Supply Current

I DD(ON)V DD = 12 V, Outputs Open — 1.0 2.0mA V DD = 10 V, Outputs Open —0.9 1.7mA V DD = 5.0 V, Outputs Open

—0.7 1.0mA I DD(OFF)V DD = 12 V, Outputs Open, Inputs = 0 V ——200μA V DD = 5.0 V, Outputs Open, Inputs = 0 V —50100μA Clamp Diode I R V R = 50 V, T A = +25°C ——50μA V R = 50 V, T A = +70°C ——100μA Clamp Diode Forward Voltage

V F

I F = 350 mA

—

1.7

2.0

NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic “1”.

Saturation Voltage

Leakage Current

(Each Stage)(Total)

G R O U N D

U T P U T

N A B L E

T R O B E

Dwg. PP-037

U P P L Y C L A M P D I O D E C O M M O N

L E A R

OUT 1I N 8O U T OUT 2 OUT 3 OUT 4OUT 5 OUT 6 OUT 7

IN 1IN IN IN IN IN IN UCN5801EP

(additional pinout diagrams

are on next page)

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

TRUTH TABLE

OUT N

IN N STROBE

CLEAR ENABLE

t-1t 0100X OFF 1100X ON X X 1X X OFF X X X 1X OFF X 000ON ON X

OFF

X = irrelevant.

t-1 = previous output state.

t = present output state.

OUTPUT

CLEAR

STROBE

OUTPUT ENABLE IN N

OUT N

TIMING CONDITIONS

(Logic Levels are V DD and Ground)

A.Minimum Data Active Time Before Strobe Enabled

(Data Set-Up Time)..........................................................50 ns B.Minimum Data Active Time After Strobe Disabled

(Data Hold Time)..............................................................50 ns C.Minimum Strobe Pulse Width..................................................125 ns

D.Typical Time Between Strobe Activation and

Output On to Off Transition ............................................500 ns E.Minimum Time Between Strobe Activation and

Output Off to On Transition ............................................500 ns

F.Minimum Clear Pulse Width ....................................................300 ns

G.Minimum Data Pulse Width.....................................................225 ns Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or STROBE input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches.

Dwg. No. A-10,895A

UCN5801A

SUPPLY CLEAR OUTPUT ENABLE STROBE

OUT 1OUT 2OUT 3OUT 4IN 1IN 2IN 3IN 4GROUND

OUT 5OUT 6OUT 7Dwg. PP-015

OUT 8COMMON

IN 5IN 6IN 7IN

SUPPLY CLEAR OUTPUT ENABLE STROBE

OUT 1OUT 2OUT 3OUT 4IN 1IN 2IN 3IN 4GROUND OUT 5OUT 6OUT 7Dwg. PP-015-1

OUT 8COMMON IN 5IN 6IN 7IN 8

CONNECTION

UCN5801LW

TYPICAL APPLICATION

UNIPOLAR STEPPER-MOTOR DRIVE

Dwg. No. B-1537

STROBE

IN 1

IN 2

IN 3

IN 4

OUT 1

OUT 2

OUT 3

OUT 4

Dwg. GP-060

STROBE

IN 1

IN 2

IN 3

IN 4

OUT 1

OUT 2

OUT 3

OUT 4

Dwg. GP-060-1 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

UCN5800A

Dimensions in Inches (controlling dimensions)

Dimensions in Millimeters (for reference only)

NOTES: 1.Exact body and lead configuration at vendor’s option within limits shown.

2.Lead spacing tolerance is non-cumulative.

3.Lead thickness is measured at seating plane or below.

Dwg. MA-001-14A in

Dwg. MA-001-14A mm

NOTES:1.

Exact body and lead configuration at vendor’s option within limits shown.2.

Lead spacing tolerance is non-cumulative.

UCN5800L

Dimensions in Inches (for reference only)

Dimensions in Millimeters (controlling dimensions)

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

UCN5801A

Dimensions in Inches (controlling dimensions)

Dimensions in Millimeters (for reference only)

NOTES: 1.Exact body and lead configuration at vendor’s option within limits shown.

2.Lead spacing tolerance is non-cumulative.

3.Lead thickness is measured at seating plane or below.

UCN5801EP

Dimensions in Inches (controlling dimensions)

Dimensions in Millimeters (for reference only)

NOTES: 1.Exact body and lead configuration at vendor’s option within limits shown.

2.Lead spacing tolerance is non-cumulative.

Dwg. MA-005-28A in

Dwg. MA-005-28A mm

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

UCN5801LW

Dimensions in Inches (for reference only)

Dimensions in Millimeters (controlling dimensions)

NOTES:1.

Exact body and lead configuration at vendor’s option within limits shown.2.Lead spacing tolerance is non-cumulative.

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115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

BiMOS II (Series 5800) & DABiC IV (Series 6800)INTELLIGENT POWER INTERFACE DRIVERS

SELECTION GUIDE

Function

Output Ratings *

Part Number ?

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers)-120 mA 50 V?58958-Bit 350 mA 50 V 58218-Bit 350 mA 80 V 58228-Bit 350 mA 50 V?58418-Bit 350 mA 80 V?58429-Bit

1.6 A 50 V 5829

10-Bit (active pull-downs)-25 mA 60 V 5810-F and 6809/1012-Bit (active pull-downs)-25 mA 60 V 5811 and 681120-Bit (active pull-downs)-25 mA 60 V 5812-F and 681232-Bit (active pull-downs)-25 mA 60 V 5818-F and 681832-Bit

100 mA 30 V 583332-Bit (saturated drivers)

100 mA

40 V

5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit 350 mA 50 V?58008-Bit -25 mA 60 V 58158-Bit

350 mA

50 V?

5801

SPECIAL-PURPOSE FUNCTIONS

Unipolar Stepper Motor Translator/Driver 1.25 A 50 V?5804Addressable 28-Line Decoder/Driver

450 mA 30 V 6817

*Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.Negative current is defined as coming out of (sourcing) the output.

?Complete part number includes additional characters to indicate operating temperature range and package style.?

Internal transient-suppression diodes included for inductive-load protection.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.