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ACPL-331J IGBT驱动芯片

ACPL-331J IGBT驱动芯片
ACPL-331J IGBT驱动芯片

ACPL-331J

1.5 Amp Output Current IGBT Gate Driver Optocoupler with Integrated (V CE ) Desaturation Detection, UVLO, Fault Status Feedback and Active Miller Clamping

Description

The ACPL-331J is an advanced 1.5 A output current, easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to implement. Features such as integrated V CE detection, under voltage lockout (UVLO), “soft” IGBT turn-off, isolated open collector fault feedback and active Miller clamping provide maximum design flexibility and circuit protec-tion.

The ACPL-331J contains a GaAsP LED. The LED is optically coupled to an integrated circuit with a power output stage. ACPL-331J is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V and 100 A. For IGBTs with higher ratings, the ACPL-331J can be used to drive a discrete power stage which drives the IGBT gate. The ACPL-331J has an insulation voltage of V IORM = 891 V PEAK .

Block Diagram

Features

? Under Voltage Lock-Out Protection (UVLO) with Hysteresis ? Desaturation Detection ? Miller Clamping

? Open Collector Isolated fault feedback ? “Soft” IGBT Turn-off

? Fault Reset by next LED turn-on (low to high) after fault mute period ? Available in SO-16 package

? Safety approvals: UL approved, 3750 V RMS for 1 minute, CSA approved, IEC/EN/DIN-EN 60747-5-2 approved V IORM = 891 V PEAK

Specifications

? 1.5 A maximum peak output current ? 1.0 A minimum peak output current ? 250 ns maximum propagation delay over temperature range

? 100 ns maximum pulse width distortion (PWD)? 15 kV/μs minimum common mode rejection (CMR) at V CM = 1500 V ? I CC(max) < 5 mA maximum supply current ? Wide V CC operating range: 15 V to 30 V over temperature range ? 1.0 A Miller Clamp. Clamp pin short to V EE if not used ? Wide operating temperature range: –40°C to 100°C

Applications

? Isolated IGBT/Power MOSFET gate drive ? AC and brushless DC motor drives

? Industrial inverters and Uninterruptible Power Supply (UPS)

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

E

CC2

OUT CLAMP EE

LED

Pin Description

Pin

Symbol

Description

1V S Input Ground

2V CC1Positive input supply voltage. (4.5 V to 5.5 V)

3

FAULT

Fault output. FAULT changes from a high impedance state to a logic low output within 5 μs of the voltage on the DESAT pin exceeding an internal reference voltage of 6.5 V. FAULT output is an open collector which allows the FAULT outputs from all ACPL-331J in a circuit to be connected together in a “wired OR” forming a single fault bus for inter-facing directly to the micro-controller.4

V S Input Ground 5CATHODE Cathode 6ANODE Anode 7ANODE Anode 8CATHODE Cathode

9V EE Output supply voltage.10V CLAMP Miller clamp

11V OUT Gate drive voltage output 12V EE Output supply voltage.13V CC2Positive output supply voltage

14

DESAT

Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 6.5 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 μs.

15V LED

LED anode. This pin must be left unconnected for guaran-teed data sheet performance. (For optical coupling testing only)

16V E

Common (IGBT emitter) output supply voltage.

12345678

16151413

1211109

V E V LED DESAT V CC2V EE V OUT V CLAMP

V EE

V S V CC1FAULT V S

CATHODE ANODE ANODE CATHODE

Ordering Information

ACPL-331J is UL Recognized with 3750 Vrms for 1 minute per UL1577.

Part number

Option

Package

Surface Mount

Tape& Reel

IEC/EN/DIN EN 60747-5-2

Quantity

RoHS Compliant

ACPL-331J

-000E SO-16

X X 45 per tube -500E

X

X

X

850 per reel

To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1:

ACPL-331J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.Example 2:

ACPL-331J-000E to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘.

Dimensions in inches (millimeters)

Notes: Initial and continued variation in the color of the ACPL-331J’s white mold compound is normal and does note affect device performance or reliability.

Floating Lead Protrusion is 0.25 mm (10 mils) max.

ACPL-331J 16-Lead Surface Mount Package

Package Outline Drawings

0.050TYPE NUMBER DATE CODE

LAND PATTERN RECOMMENDATION

Solder Reflow Thermal Profile

Recommended Pb-Free IR Profile

Note: Non-halide flux should be used.

TIME (SECONDS)

T E M P E R A T U R E (°C )

ROOM Note: Non-halide flux should be used.

NO TES:

THE TIME FROM 25°C to PEAK TEMPERATURE = 8 MINUTES MAX.T smax = 200 °C, T smin = 150°C

Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*

Description

Symbol Characteristic

Unit

Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 V rms for rated mains voltage ≤ 300 V rms for rated mains voltage ≤ 600 V rms I – IV I – IV I – III Climatic Classification

55/100/21Pollution Degree (DIN VDE 0110/1.89)2Maximum Working Insulation Voltage

V IORM 891V peak Input to Output Test Voltage, Method b**,

V IORM x 1.875=V PR , 100% Production Test with t m =1 sec, Partial discharge < 5 pC

V PR

1670

V peak

Input to Output Test Voltage, Method a**,

V IORM x 1.5=V PR , Type and Sample Test, t m =60 sec, Partial discharge < 5 pC V PR 1336V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 10 sec)V IOTM

6000

V peak

Safety-limiting values – maximum values allowed in the event of a failure Case Temperature T S 175°C Input Current I S, INPUT 400mA Output Power

P S, OUTPUT 1200mW Insulation Resistance at T S , V IO = 500 V

R S

>109

W

* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.

** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.Dependence of Safety Limiting Values on Temperature. (take from DS AV01-0579EN Pg.7)

Regulatory Information

The ACPL-331J is approved by the following organizations:

UL

Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361.

CSA

Approval under CSA Component Acceptance Notice #5, File CA 88324.

IEC/EN/DIN EN 60747-5-2

Approval under:

IEC 60747-5-2 :1997 + A1:2002 EN 60747-5-2:2001 + A1:2002

DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01

S P - P O W E R - m W

0S

T - CASE TEMPERATURE - °C 120080014004002006001000

Table 2. Insulation and Safety Related Specifications

Parameter Symbol ACPL-331J Units Conditions

Minimum External Air Gap (Clearance)L(101)8.3Mm Measured from input terminals to output terminals,

shortest distance through air.

Minimum External Tracking (Creepage)L(102)8.3Mm Measured from input terminals to output terminals,

shortest distance path along body.

Minimum Internal Plastic Gap (Internal Clearance)0.5Mm Through insulation distance conductor to conductor,

usually the straight line distance thickness between the

emitter and detector.

Tracking Resistance

(Comparative Tracking

Index)

CTI>175V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Table 3. Absolute Maximum Ratings

Parameter Symbol Min.Max.Units Note Storage Temperature T S-55125°C

Operating Temperature T A-40100°C2 Output IC Junction Temperature T J125°C2 Average Input Current I F(AVG)25mA1 Peak Transient Input Current

(<1 μs pulse width, 300pps)

I F(TRAN) 1.0A

Reverse Input Voltage V R5V

“High” Peak Output Current I OH(PEAK) 1.5A3“Low” Peak Output Current I OL(PEAK) 1.5A3 Positive Input Supply Voltage V CC1-0.5 5.5V

FAULT Output Current I FAULT8.0mA

FAULT Pin Voltage V FAULT-0.5V CC1V

Total Output Supply Voltage(V CC2 - V EE)-0.533V

Negative Output Supply Voltage(V E - V EE)-0.515V6 Positive Output Supply Voltage(V CC2 - V E)-0.533 - (V E - V EE)V

Gate Drive Output Voltage V O(PEAK)-0.5V CC2V

Peak Clamping Sinking Current I Clamp 1.0A

Miller Clamping Pin Voltage V Clamp-0.5V CC2V

DESAT Voltage V DESAT V E V E + 10V

Output IC Power Dissipation P O600mW2 Input IC Power Dissipation P I150mW2 Solder Reflow Temperature Profile See Package Outline Drawings section

Table 4. Recommended Operating Conditions

Parameter Symbol Min.Max.Units Note Operating Temperature T A- 40100°C2 Total Output Supply Voltage(V CC2 - V EE)1530V7 Negative Output Supply Voltage(V E - V EE)015V4 Positive Output Supply Voltage(V CC2 - V E)1530 - (V E - V EE)V

Input Current (ON)I F(ON)812mA

Input Voltage (OFF)V F(OFF)- 3.60.8V

A CC2EE E EE

all Minimum/Maximum specifications are at Recommended Operating Conditions.

Parameter Symbol Min.Typ.Max.Units Test Conditions Fig.Note

FAULT Logic Low Output Voltage V FAULTL0.1V I FAULT = 1.1 mA, V CC1 = 5.5V

0.1V I FAULT = 1.1 mA, V CC1 = 3.3V

FAULT Logic High Output Current I FAULTH0.003μA V FAULT = 5.5 V, V CC1 = 5.5V

0.003μA V FAULT = 3.3 V, V CC1 = 3.3V

High Level Output Current I OH-0.3-0.75A V O = V CC2 – 44, 185

-1.0A V O = V CC2 – 153

Low Level Output Current I OL0.30.75A V O = V EE + 2.55, 195

1.0A V O = V EE + 153

Low Level Output Current

During Fault Condition

I OLF90140230mA V OUT - V EE = 14 V6

High Level Output Voltage V OH V CC-3.5V CC-2.5V I O = 100 mA2, 4,

20

7, 8,9 V CC-2.9V CC-2.0V I O = -650 μA23

Low Level Output Voltage V OL0.170.5V I O = 100 mA3, 5,

21

Clamp Pin Threshold

Voltage

V tClamp 2.0V

Clamp Low Level

Sinking Current

I CL0.210.7A V O = V EE + 2.5

High Level Supply Current I CC2H 2.55mA I O = 0 mA6, 7,

239

Low Level Supply Current I CC2L 2.55mA I O = 0 mA

Blanking Capacitor

Charging Current

I CHG0.13-0.24-0.33mA V DESAT = 2 V8, 249, 10

Blanking Capacitor

Discharge Current

I DSCHG1030mA V DESAT = 7.0 V25

DESAT Threshold V DESAT6 6.57.5V V CC2 -V E >V UVLO-9, 279 UVLO Threshold V UVLO+10.511.612.5V V O > 5 V7, 9, 11

V UVLO-9.210.311.1V V O < 5 V7, 9, 12 UVLO Hysteresis(V UVLO+

- V UVLO-)

0.4 1.3V

Threshold Input Current

Low to High

I FLH 2.08mA I O = 0 mA, V O > 5 V

Threshold Input Voltage

High to Low

V FHL0.8V

Input Forward Voltage V F 1.2 1.6 1.95V I F = 10 mA

Temperature Coefficient

of Input Forward Voltage

D V F/D T A-1.3mV/°C

Input Reverse Breakdown

Voltage

BV R5V I R = 10 μA

Input Capacitance C IN70pF f = 1 MHz, V F = 0 V

A CC2EE E EE

all Minimum/Maximum specifications are at Recommended Operating Conditions.

Parameter Symbol Min.Typ.Max.Units Test Conditions Fig.Note

Propagation Delay Time to High Output Level t PLH100180250ns Rg = 20 W, Cg = 5 nF,

f = 10 kHz,

Duty Cycle = 50%,

I F = 10 mA, V CC2 = 30 V

1, 10,

11, 12,

13, 26

13, 15

Propagation Delay Time

to Low Output Level

t PHL100180250ns

Pulse Width Distortion PWD-10020100ns14, 17

Propagation Delay Difference Between Any Two Parts or Channels (t PHL - t PLH)

PDD

-350350ns17, 16

Rise Time t R50ns Fall Time t F50ns

DESAT Sense to 90% VO Delay t DESAT(90%)0.150.3μs C DESAT = 100pF, R F=2.1k?,

R g = 20 W, C g = 5 nF,

V CC2 = 30 V 14, 27,

34

19

DESAT Sense to 10% VO Delay t DESAT(10%) 1.1 1.5μs C DESAT = 100pF, R F=2.1k? ,

R g = 20 W, C g = 5 nF,

V CC2 = 30 V 15, 16, 17, 27, 34

DESAT Sense to Low Level FAULT Signal Delay t DESAT(FAULT)0.250.5μs C DESAT = 100pF, R F = 2.1

k W,

R g = 20 W, C g = 5 nF,

V CC2 = 30 V

27, 3418

DESAT Sense to DESAT Low Propagation Delay t DESAT(LOW)0.25μs C DESAT = 100pF, R F = 2.1

k W,

R g = 20 W, C g = 5 nF,

V CC2 = 30 V

27, 3419

DESAT Input Mute t DESAT(MUTE)5μs3420

RESET to High Level FAULT Signal Delay t RESET(FAULT)0.31 2.0μs C DESAT = 100pF,

R F = 2.1 k W,

Rg = 20 W, Cg = 5 nF,

V CC1 = 5.5V, V CC2 = 30 V

0.8 1.5 2.5μs C DESAT = 100pF,

R F = 2.1 k W,

Rg = 20 W, Cg = 5 nF,

V CC1 = 3.3V, V CC2 = 30 V

Output High Level Common Mode Transient Immunity |CM H|1525kV/μs T A = 25°C, I F = 10 mA

V CM = 1500 V, V CC2 = 30 V

28, 29,

30, 31

21

Output Low Level Common Mode Transient Immunity |CM L|1525kV/μs T A = 25°C, V F = 0 V

V CM = 1500 V, V CC2 = 30 V

28, 29,

30, 31

22

Table 7. Package Characteristics

Parameter Symbol Min.Typ.Max.Units Test Conditions Fig.Note

Input-Output Momentary Withstand Voltage V ISO3750V rms RH < 50%, t = 1 min.,

T A = 25°C

6, 7

Input-Output Resistance R I-O> 109W V I-O = 500 V7 Input-Output Capacitance C I-O 1.3pF freq=1 MHz

Output IC-to-Pins 9 &10

Thermal Resistance

q09-1030°C/W T A = 25°C

Notes:

1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C.

2. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require

airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating.

3. Maximum pulse width = 10 μs. This value is intended to allow for component tolerances for designs with IO peak minimum = 1.0 A.

Derate linearly from 2.0 A at +25°C to 1.5 A at +100°C. This compensates for increased I OPEAK due to changes in V OL over temperature.

4. This supply is optional. Required only when negative gate drive is implemented.

5. Maximum pulse width = 50 μs.

6. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.

7. 15 V is the recommended minimum operating positive supply voltage (V CC2 - V E) to ensure adequate margin in excess of the maximum V UVLO+

threshold of 12.5 V. For High Level Output Voltage testing, V OH is measured with a dc load current. When driving capacitive loads, V OH will approach V CC as I OH approaches zero units.

8. Maximum pulse width = 1.0 ms.

9. Once V O of the ACPL-331J is allowed to go high (V CC2 - V E > V UVLO), the DESAT detection feature of the ACPL-331J will be the primary source of

IGBT protection. UVLO is needed to ensure DESAT is functional. Once V UVLO+ > 12.5 V, DESAT will remain functional until V UVLO- < 9.2 V. Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection.

10. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details.

11. This is the “increasing” (i.e. turn-on or “positive going” direction) of V CC2 - V E

12. This is the “decreasing” (i.e. turn-off or “negative going” direction) of V CC2 - V E

13. This load condition approximates the gate load of a 1200 V/75A IGBT.

14. Pulse Width Distortion (PWD) is defined as |t PHL - t PLH| for any given unit.

15. As measured from I F to V O.

16. The difference between t PHL and t PLH between any two ACPL-331J parts under the same test conditions.

17. As measured from ANODE, CATHODE of LED to V OUT

18. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.

19. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. This is supply

voltage dependent.

20. Auto Reset: This is the amount of time when VOUT will be asserted low after DESAT threshold is exceeded. See the Description of Operation

(Auto Reset) topic in the application information section.

21. Common mode transient immunity in the high state is the maximum tolerable dV CM/dt of the common mode pulse, V CM, to assure that the

output will remain in the high state (i.e., V O > 15 V or FAULT > 2 V). A 100 pF and a 2.1 k? pull-up resistor is needed in fault detection mode. 22. Common mode transient immunity in the low state is the maximum tolerable dV CM/dt of the common mode pulse, V CM, to assure that the

output will remain in a low state (i.e., V O < 1.0 V or FAULT < 0.8 V).

23. To clamp the output voltage at V CC - 3 VBE, a pull-down resistor between the output and V EE is recommended to sink a static current of 650 μA

while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used.

Figure 1. Timing Curve

-3-2.5-2-1.5-1-0.50-40

-20

20

40

60

80

100

(V O H - V C C ) - H I G H O U T P U T V O L T A G E D R O P - V

T A - TEMPERATURE -o C

Figure 2. V OH vs. temperature

Figure 3. V OL vs. temperature

Figure 4. V OH vs. IOH Figure 5. V OL vs. I OL

28.0

28.5

29.0

29.5

30.0

I OH - OUTPUT HIGH CURRENT - A

(V O H - V C C ) - H I G H O U T P U T V O L T A G E D R O P - V

1

2

3

4

00.51 1.5

I OL - OUTPUT LOW CURRENT - A

V O L - O U T P U T L O W V O L T A

G E - V

00.050.10.150.20.25

-40

-200204060

80100

V O L - O U T P U T L O W V O L T A G E - V

T A - TEMPERATURE -

o C

Figure 7. I CC2 vs. V CC2

-0.35

-0.30

-0.25

-0.20

-40

-20

20

40

60

80100

T A -TEMPERATURE -

o C

I C H - B L A N K I N G C A P A C I T O R C H A R G I N G C U R R E N T - m A

Figure 8. I CHG

vs. temperature 6.06.5

7.0

7.5

-40

-20

20

40

60

80

100

T A - TEMPERATURE -o C

V D E S A T - D E S A T T H R E S H O L D - V

-40

-20020406080100

T A - TEMPERATURE -o C

T P - P R O P A G A T I O N D E L A Y - n s

Figure 9. DESAT threshold vs. temperature

Figure 10. Propagation delay vs. temperature 100150

200

250

30015

202530

Vcc - SUPPLY VOLTAGE - V

T P - P R O P A G A T I O N D E L A Y - n s

Figure 11. Propagation delay vs. supply voltage

2.00

2.252.502.75

3.003.253.50I C C 2 - O U T P U T S U P P L Y C U R R E N T - m A

T A - TEMPERATURE -o C

Figure 6. I CC2 vs. temperature 2.25

2.35

2.45

2.55

2.65

15

20

25

30

I C C 2 - O U T P U T S U P

P L Y C U R R E N T - m A

V CC2 - SUPPLY VOLTAGE - V

Figure 13. Propagation delay vs. load capacitance

100

200

300

10

20

30

40

50

LOAD CAPACITANCE - nF

T P - P R O P A G A T I O N D

E L A Y - n s

100150

200

250-40

-20020406080100

T A - TEMPERATURE -o C T D E S A T 90% - D E S A T S e n s e t o 90% V o D e l a y - n s

Figure 14. DESAT sense to 90% V OUT delay vs. temperature

-40

-20020406080100

T A - TEMPERATURE -o C

T D E S A T 10% - D E S A T S e n s e t o 10% V o D e l a y - n s

Figure 15. DESAT sense to 10% V OUT

delay vs. temperature

0.01.0

2.0

3.0

4.0

10

20

3040

50

LOAD RESISTANCE-ohm

T D E S A T 10% - D E S A T S e n s e t o 10% V o D e l a y - n s

Figure 16. DESAT sense to 10% V OUT delay vs. load resistance 0.000

0.004

0.008

0.012

010********

LOAD CAPACITANCE-nF

T D E S A T 10% - D E S A T S e n s e t o

10% V o D e l a y - n s

Figure 17. DESAT sense to 10% V OUT

delay vs. load capacitance

100

150

200

250

300010

2030

4050

LOAD RESISTANCE - ohm

T P - P R O P A G A T I O N D E L A Y - n s

Figure 12. Propagation delay vs. load resistance

Figure 18. I OH Pulsed test circuit

Figure 19. I OL Pulsed test circuit

Figure 20. V OH Pulsed test circuit

Figure 21. V OL Pulsed test circuit

Figure 22. I CC2H test circuit

Figure 23. I CC2L test circuit

Figure 24. I CHG Pulsed test circuit

Figure 25. I DSCHG test circuit

Figure 26. t PLH, t PHL, t f, t r, test circuit

Figure 27. tDESAT fault test circuit

Figure 28. CMR Test circuit LED2 off

V

Figure 29. CMR Test Circuit LED2 on

V CM

V CM

V CM Figure 30. CMR Test circuit LED1 off

V CM

Figure 31. CMR Test Circuit LED1 on

Application Information

Product Overview Description

The ACPL-331J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT / MOSFET gate drive circuit with fault protection and feedback into one SO-16 package. Active Miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. An optically isolated power output stage drives IGBTs with power ratings of up to 100 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent

damage during over current, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watchdog” circuit, UVLO monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design.

Two light emitting diodes and two integrated circuits housed in the same SO-16 package provide the input control circuitry, the output power stage, and two optical channels. The output Detector IC is designed manufac-tured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal.

Under normal operation, the LED1 directly controls the IGBT gate through the isolated output detector IC, and LED2 remains off. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shutdown sequence, reducing the IGBT current to zero in a con-trolled manner to avoid potential IGBT damage from inductive over voltages. Simultaneously, this fault status is transmitted back to the input via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller.

During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-331J’s output low. Once the output is in the high state, the DESAT (V CE) detection feature of the ACPL-331J provides IGBT pro-tection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection.Recommended Application Circuit

The ACPL-331J has an LED input gate control, and an open collector fault output suitable for wired ‘OR’ ap-plications. The recommended application circuit shown in Figure 33 illustrates a typical gate drive implementa-tion using the ACPL-331J. The following describes about driving IGBT. However, it is also applicable to MOSFET. Depending upon the MOSFET or IGBT gate threshold re-quirements, designers may want to adjust the VCC supply voltage (Recommended V CC= 17.5V for IGBT and 12.5V for MOSFET).

The two supply bypass capacitors (0.1 μF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5mA) power supply suffices. The desaturation diode D DESAT 600V/1200V fast recovery type, t rr below 75ns (e.g. ERA34-10) and capacitor C BLANK are necessary external components for the fault detection circuitry. The gate resistor R G serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. The open collector fault output has a passive pull-up resistor R F (2.1 k W) and a 330 pF filtering capacitor, C F. A 47 k W pull down resistor R PULL-DOWN on V OUT provides a predictable high level output voltage (V OH). In this application, the IGBT gate driver will shut down when a fault is detected and fault reset by next cycle of IGBT turn on. Application notes are mentioned at the end of this datasheet.

Figure 32. Block Diagram of ACPL-331J

E

CC2

OUT

CLAMP

EE

LED

Figure 33. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp

Description of Operation

Normal Operation

During normal operation, V OUT of the ACPL-331J is con-trolled by input LED current I F(pins 5, 6, 7 and 8), with the IGBT collector-to-emitter voltage being monitored through D DESAT. The FAULT output is high. See Figure 34. Fault Condition

The DESAT pin monitors the IGBT Vce voltage. When the voltage on the DESAT pin exceeds 6.5 V while the IGBT is on, VOUT is slowly brought low in order to “softly” turn-off the IGBT and prevent large di/dt induced voltages. Also Figure 34. Fault Timing diagramactivated is an internal feedback channel which brings the FAULT output low for the purpose of notifying the micro-controller of the fault condition.

Fault Reset

Once fault is detected, the output will be muted for 5 μs (minimum). All input LED signals will be ignored during the mute period to allow the driver to completely soft shut-down the IGBT. The fault mechanism can be reset by the next LED turn-on after the 5us (minimum) mute time. See Figure 34.

+ HVDC -HVDC

AC

Output Control

The outputs (V OUT and FAULT) of the ACPL-331J are con-trolled by the combination of I F , UVLO and a detected IGBT Desat condition. Once UVLO is not active (V CC2 - V E > V UVLO ), V OUT is allowed to go high, and the DESAT (pin 14) detection feature of the ACPL-331J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V UVLO+ > 10.5V, DESAT will remain functional until V UVLO- < 11.1V. Thus, the DESAT detection and UVLO features of the ACPL-331J work in conjunction to ensure constant IGBT protection.

Desaturation Detection and High Current Protection

The ACPL-331J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback signal into a single 16-pin surface mount package.

The fault detection method, which is adopted in the ACPL-331J is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predeter-mined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false ‘fault’ signals.

The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-331J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly conservative over current threshold is not needed to protect the IGBT.

I F

UVLO (V CC2 – V E )

Desat Condition Detected on Pin 14

Pin 3 (FAULT) Output

V OUT

X Active X X Low X X Yes Low Low OFF X X X Low ON

Not Active

No

High

High

Slow IGBT Gate Discharge during Fault Condition

When a desaturation fault is detected, a weak pull-down device in the ACPL-331J output drive stage will turn on to ‘softly’ turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below V EE + 2 Volts, at which time the large pull down device clamps the IGBT gate to V EE .

DESAT Fault Detection Blanking Time

The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. This time period, called the DESAT blanking time is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor.

The nominal blanking time is calculated in terms of external capacitance (C BLANK ), FAULT threshold voltage (V DESAT ), and DESAT charge current (I CHG ) as t BLANK = C BLANK x V DESAT / I CHG . The nominal blanking time with the recommended 100pF capacitor is 100pF * 6.5 V / 240 μA = 2.7 μsec.

The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time represents the longest time it will take for the ACPL-331J to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately 3 μsec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommended 100pF capacitor should provide adequate blanking as well as fault response times for most applications.

(完整word版)教案-驱动力控制系统教案(朱明zhubob)

一.复习(10') ABS系统具有的故障自诊断功能 二教学过程(60') 一、概述 牵引力控制系统(TRC)也称为驱动力控制系统(TCS)或驱动防滑转控制系统(ASR)。 系统作用: (1)在驱动过程中防止驱动车轮发生滑转, (2)并在起步和加速时,根据路面情况给出一个最佳的驱动力。 (3)在湿滑路面上起步、加速或转向时,能提高车辆的稳定性。 TCS和ABS系统的关系: (1)从控制车轮和路面的滑移率来看,采用了相同的技术, (2)但两者所控制的车轮滑移方向是相反的。 (3)TCS系统与ABS系统常合在一起使用,构成行驶安全系统。 (4)TCS和ABS共用许多电子元件,用共同的系统部件来控制车轮的运动。 1.TCS的控制作用 汽车在冰雪路面上急加速或超车时,ASR的控制效果是很明显的。 在均匀的结冰路面上、压实的雪路和深雪路面上使用TCS和不用TCS装置的驱动力的比较, 在左右轮附着系数不同的路面上,使用TCS和不使用TCS装置的汽车加速性比较的结果。 2.滑转率的控制范围 所谓的汽车打“滑”,有两种情况: 一是汽车制动时车轮的滑移,ABS是防止制动时车轮抱死而滑移;

二是汽车驱动时车轮的滑转。TCS防止驱动车轮原地不动而不停地滑转。 驱动轮滑转:当汽车起步时,驱动轮不停地转动,汽车却原地不动。 TCS与ABC起作用时,二者的制动力与驱动力正好相反, TRC防止驱动时车轮滑转的方法: 适当地控制驱动力,是TCS的作用。 将滑转率Vd控制在10%—30%范围之内,防滑效果较为理想。 3.牵引力控制装置的控制方式 1)发动机输出扭矩控制 发动机输出转矩改变:汽油机根据燃料喷射量、点火时间、节气门开度调整。 2)驱动轮制动控制 这种方法是对发生空转的驱动轮直接加以制动,反应时间最短。为使制动过程平稳,应缓慢升高制动压力。 制动控制方式的ASR的液压系统可分为两大类。

动力电池管理系统与整车控制系统匹配的研究

动力电池管理系统与整车控制系统匹配的研究 项目概要: 电池管理系统(BMS)是新能源汽车实用化、商品化的关键技术之一。优化电池管理系统与所搭载的整车控制系统之间的匹配性研究,是武汉纯电动城市客车控制系统中一项有关核心技术的研究,优化电动车控制系统的兼容性可使纯电动客车发挥更大的经济、社会、环境效益。 国内发展现状 国内科研机构已开发出拥有自主知识产权的电动车用动力电池管理系统并与整车控制系统匹配,但是由于缺乏电控产品工程化开发的技术、能力和经验,缺乏有助于技术成果转化的产业化平台,很多研发成果无法进一步转变为可以批量应用的具有高质量、高性价比、良好的一致性、可靠性和耐久性的产品。 目前我司针对动力电池系统与整车匹配提出了具体解决方案 电池与整车控制器的通讯: 武汉纯电动城市客车整车CAN总线网络拓扑结构如下图所示,CAN总线由两条子网络构成,传输速率均为250kbps。电机控制器、电池管理系和故障诊断模块挂接在CAN1上。

通过上图可知整车网络拓扑结构,整车控制器兼用来实现跨子网数据通讯。整车网络由以下子网构成: ☆整车控制网络CAN1 ☆整车信息显示及车身控制网络CAN2

电池管理系统与整车控制器进行通信的具体报文例子如下所示: 整车控制器传与电池管理系统的报文例子如下 HCUScrStatus1:

研究目标及方向 我司建立了电池充放电实验室和电池管理系统匹配性测试平台,通过对我厂基于电池与整车控制器进行匹配的车用动力电池与整车CAN通信等方面进行研究。在延长动力电池使用寿命的基础上提高动力电池的能量效率和运行可靠性,开发适用于新能源纯电动汽车的动力电池管理系统。 在此基础上,建立电池性能检测以及电池管理系统的测试平台,最终达到如下目标: a)CAN通信中电池容量通信优化; b)CAN通信中过流、过压、温度保护通信准确性; c)CAN通信中故障预警通信智能化; d)CAN通信中充电控制通信完整并可储存整个充电过程可查。

最新驱动力控制系统 TCS资料

驱动力控制系统TCS (又称TRC防滑控制系统TRAC循迹控制系统) 第一节概述 一、TCS的作用 在摩擦力限度内自动调节汽车的驱动力,避免车轮打滑、轮胎磨损,使车辆能正常行驶及维持转向的稳定性和操控性。 汽车行驶时,轮胎会受到两个力,即加速时的驱动力和转向时的向心力,两力之和称为轮胎力。 汽车的驱动力超过摩擦力的限度时轮胎因打滑的关系,将无法有效的将驱动力传至路面,使车辆无法操纵而发生不安全。 二、ABS与TCS的区别 1、ABS是在制动时防止车轮抱死,以免发生滑行现象,而TCS 是在湿滑起步或加速时防止驱动轮打滑或在摩擦系数相差很大的非对称路面防止单侧驱动轮打滑。 2、ABS对驱动轮和非驱动轮都可以控制,而TCS则只控制驱动轮 3、ABS控制期间,各车轮之间的影响不大,而TCS控制期间由于差速器的作用,会使驱动车轮之间产生相互影响 三、TCS的控制方式 1、控制发动机 控制燃油喷射量、节气门开度或点火的时间 2、控制制动(驱动轮)

与ABS调节器共用或另设调节器 3、发动机与制动力同时控制 四、TCS的控制范围 控制范围:滑移率0-35%(B范围) 1、以A范围为目标,可发挥最大的驱动力,但轮胎的向心力不足,转向控制性能变差,若以向心力最大为优先条件,则无法获得有效的见加速力。 2、为兼顾驱动力和向心力,以B范围为控制目标,以路面状况、转向盘转角、车身倾斜度等为据,由TCS ECU计算出最小滑移率目标值,由100%至100%向心力作最佳的调配,使车辆在安全状态下充分发挥其操作性与运动性。 五、TCS系统的控制对象 1、起步加速控制 当驾驶员在光滑路面上过多踩油门时,会造成车轮的滑转。驱动控制系统通过自动施加部分制动或减少发动机输出功率的方式,

第 四 章 电控驱动防滑牵引力控制系统(ASRTRC)

第四章电控驱动防滑/牵引力控制系统(ASR/TRC) 一、教学目的和基本要求 通过此章内容的教学,让学生了解ASR的理论基础、ASR控制的方式、ASR 与ABS的区别;掌握ASR的结构与工作原理及典型车型的ASR结构组成和工作过程;了解防滑差速器的作用、形式以及四轮驱动防滑差速器的基本结构和工作原理。 二、教学内容及课时安排 第一节概述、第二节ASR的结构与工作原理理论教学:1学时。 第三节典型ASR 理论教学:2学时。 第四节防滑差速器的结构原理理论教学:1学时。 三、教学重点及难点 重点:ASR的理论基础;ASR的结构与工作原理。 难点:丰田ABS/TRC液压系统的工作情况及控制电路。 四、教学基本方法和教学过程 此内容采用理实一体化教学方法,对ASR及典型车型ABS/TRC的结构原理的授课采用先理论后实践的方法。 五、作业 1.ASR的理论基础 2.ASR与ABS的区别 3.ASR的结构与工作原理 4.防滑差速器的作用 5.典型车型的A BS/TRC液压系统的控制方式 第四章电控驱动防滑/牵引力控制系统(ASR/TRC) 第一节概述 一、ASR系统的理论基础 1.ASR系统的理论基础 汽车驱动防滑控制(Anti Slip Reguliation)系统简称ASR,是应用于车轮防滑的电子控制系统。 汽车打滑是指汽车车轮的滑转,车轮的滑转率又称滑移率。驱动车轮的滑移 率S d=×100%,式中v c是车轮圆周速度;v是车身瞬时速度。滑移率与纵向附着系数的关系如图5-1所示。

2.ASR与ABS的区别 (1)ABS是防止制动时车轮抱死滑移,提高制动效果,确保制动安全;ASR (TRC)则是防止驱动车轮原地不动而不停的滑转,提高汽车起步、加速及滑溜路面行驶时的牵引力,确保行驶稳定性。 (2)ABS对所有车轮起作用,控制其滑移率;而ASR只对驱动车轮起制动控制作用。 (3)ABS是在制动时,车轮出现抱死情况下起控制作用,在车速很低(小于8km/h)时不起作用;而ASR则是在整个行驶过程中都工作,在车轮出现滑转时起作用,当车速很高(80~120 km/h)时不起作用。 二、防滑转控制方式 汽车防滑转电子控制系统常用的控制方式有: 1.发动机输出功率控制 在汽车起步、加速时,ASR控制器输出控制信号,控制发动机输出功率,以抑制驱动轮滑转。常用方法有:辅助节气门控制、燃油喷射量控制和延迟点火控制。 2.驱动轮制动控制 直接对发生空转的驱动轮加以制动,反映时间最短。普遍采用ASR与ABS 组合的液压控制系统,在ABS系统中增加电磁阀和调节器,从而增加了驱动控制功能。 3.同时控制发动机输出功率和驱动轮制动力 控制信号同时起动ASR制动压力调节器和辅助节气门调节器,在对驱动车轮施加制动力的同时减小发动机的输出功率,以达到理想的控制效果。 4.防滑差速锁(LSD:Limited-Slip-Differential)控制 LSD能对差速器锁止装置进行控制,使锁止范围从0%~100%,系统结构如图5-2所示。

电机驱动控制系统

电机驱动控制系统 摘要 由于单片机具有体积小、集成度高、运算速度快、运行可靠、应用灵活、价格低廉以及面向控制等特点,因此在工业控制、数据采集、智能仪器仪表、智能化设备和各种家用电器等领域得到广泛的应用,而且发展非常迅猛。随着单片机应用技术水平不断提高,目前单片机的应用领域已经遍及几乎所有的领域。 与交流电动机相比,直流电机结构复杂、成本高、运行维护困难,但是直流电机具有良好的调速性能、较大的启动转矩和过载能力强等许多优点,因此在许多行业仍大量应用。近年来,直流电动机的机构和控制方式都发生了很大的变化。随着计算机进入控制领域以及新型的电力电子功率元器件的不断出现,采用全控型的开关功率元件进行脉宽调制(Pulse Width Modulation,简称PWM)已成为直流电机新的调速方式。这种调速方法具有开关频率高、低速运行稳定、动态性能良好、效率高等优点,更重要的是这种控速方式很容易在单片机控制系统中实现,因此具有很好的发展前景。 本设计为单片机控制直流电机,以AT89C51单片机为核心,采用了PWM技术对电机进行控制,通过对占空比的计算达到精确调速的目的。由键盘控制电动机执行启停、速度和方向等各种功能,用红外对管测量电机的实际转速,并通过1602液晶显示出控制效果。设计上,键盘输入采用阵列式输入,用4*4的矩阵键盘形式,这样可以有效的减少对单片机I/O口的占用。

关键词:AT89C51 PWM 电机测速 一、硬件设计 1、总体设计

20 929303456781011121314151617318RFB 91112 10k 23

1918 2122232425262728 1.2.2 1602液晶显示模块 本模块实现了转速等显示功能。 D :方向;占空比;预设转速;实测速度; 1.2.3键盘模块 根据实验要求,需由按键完成对直流电机的控制功能,并经分 析得出需要16个按键,为节省I/O 口并配合软件设计,此模块使用了4*4的矩阵模式。并通过P1口与主机相连。 1.2.4 PWM 驱动电路模块设计与比较

电机驱动控制系统

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