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IDT7206L15PG中文资料

CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 98,192 x 9, 16,384 x 9

32,768 x 9 and 65,536 x 9

IDT7203IDT7204IDT7205IDT7206IDT7207IDT7208

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

FEATURES:

?First-In/First-Out Dual-Port memory ?2,048 x 9 organization (IDT7203)?4,096 x 9 organization (IDT7204)?8,192 x 9 organization (IDT7205)?16,384 x 9 organization (IDT7206)?32,768 x 9 organization (IDT7207)?65,636 x 9 organization (IDT7208)?High-speed: 12ns access time ?

Low power consumption — Active: 660mW (max.)— Power-down: 44mW (max.)

?Asynchronous and simultaneous read and write ?Fully expandable in both word depth and width ?Pin and functionally compatible with IDT720X family ?Status Flags: Empty, Half-Full, Full ?Retransmit capability

?High-performance CMOS technology

?Military product compliant to MIL-STD-883, Class B

Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567(IDT7203), and 5962-89568 (IDT7204) are listed on this function

DESCRIPTION:

The IDT7203/7204/7205/7206/7207/7208 are dual-port memory buffers with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion l ogic t o a llow f or u nlimited e xpansion c apability i n b oth w ord s ize a nd depth.

Data is toggled in and out of the device through the use of the Write (W ) and Read (R ) pins.

The device's 9-bit width provides a bit for a control or parity at the user’s option. It also features a Retransmit (RT ) capability that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes.

These FIFOs are fabricated using IDT’s high-speed CMOS technology.They are designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing, rate buffering and other applications.

Military g rade p roduct i s m anufactured i n c ompliance w ith t he l atest r evision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

?Industrial temperature range (–40°C to +85°C) is available (plastic packages only)

DATA INPUTS

Green parts available, see ordering information

PIN CONFIGURATIONS

Symbol Rating Com'l & Ind'l Military Unit V TERM

Terminal –0.5 to +7.0

–0.5 to +7.0

Voltage with Respect to GND T STG Storage –55 to + 125–65 to +155°C Temperature I OUT

DC Output –50 to +50

–50 to +50

+Current

Reference Order Device Package Type Identifier Code Availability PLASTIC DIP

P28-1P All devices

PLASTIC THIN DIP P28-2TP All except IDT7207/7208CERDIP

D28-1D All except IDT7208

THIN CERDIP D28-3TD Only for IDT7203/7204/7205SOIC

SO28-3SO Only for IDT7204

Reference Order Device Package Type Identifier Code Availability PLCC J32-1J All devices LCC (1)

L32-1

All except IDT7208

TOP VIEW

NOTE:

1.This package is only available in the military temperature range.

NOTES:

1.For RT /RS /XI input, V IH =

2.6V (commercial).For RT /RS /XI input, V IH = 2.6V (military).

2.1.5V undershoots are allowed for 10ns once per cycle.

FF XI GND

EF XO /HF Vcc FL /RT RS W D 4Q 7R

2661 drw02a

D 5D 7

D 6Q 6Q 5Q 4Q 8Q 3Q 2Q 1Q 0D 8D 3D 2D 1D 0

Q EF XO /HF D 6NC FL /RT RS C c c G N N C 2661 drw02b

D 745

83D D D Q Q Q 7Q 6

Q 4Q 5

Q 8Q 3ABSOLUTE MAXIMUM RATINGS

NOTE:

1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Symbol

Parameter

Min.Typ.Max. Unit V CC Supply Voltage

4.5

5.0 5.5V Commercial/Industrial/Military GND Supply Voltage 000V V IH (1)Input High Voltage 2.0——V Commercial/Industrial V IH (1)

Input High Voltage Military 2.2——V V IL (2)Input Low Voltage

——0.8V Commercial/Industrial/Military T A Operating T emperature C ommercial 0—70°C T A Operating T emperature I ndustrial –40— 85°C T A

Operating T emperature M ilitary

–55

—

125

°C

IDT7203(1)IDT7203IDT7204(1)

IDT7204Commercial and Industrial Military (3)

t A = 12, 15, 20, 25, 35, 50 ns

t A = 20, 30, 40 ns

Symbol Parameter

Min.Typ.Max.Min.Typ.Max.Unit I LI (6) Input Leakage Current (Any Input)–1—1–1—1μA I LO (7)Output L eakage C urrent

–10—10–10—10μA V OH Output Logic “1” Voltage I OH = –2mA 2.4—— 2.4

——V V OL Output Logic “0” Voltage I OL = 8mA ——0.4——0.4V I CC1(8,9,10)Active Power Supply Current

——120——150mA I CC2(8,10,11)Standby Current (R =W =RS =FL /RT =V IH )——12——25mA I CC3(8,10,12)

Power Down Current

—

—4

AC TEST CONDITIONS

NOTES:

1.Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.

2.Industrial temperature range product for 25ns speed grade only is available as a standard device. All other speed grades are available by special order.

https://www.wendangku.net/doc/a015534199.html,itary temperature range product for the 40ns is only available for 7203.

https://www.wendangku.net/doc/a015534199.html,mercial temperature range product for the 12ns not available.

https://www.wendangku.net/doc/a015534199.html,mercial temperature range product for the 12ns, 15ns and 50ns not available.

IDT7205(2)IDT7205IDT7206(2,4)IDT7206IDT7207(2,4)IDT7207IDT7208(2,5)

Commercial and Industrial Military t A = 12, 15, 20, 25, 35, 50 ns

t A = 20, 30 ns

Symbol Parameter

Min.Typ.Max.

Min.Typ.Max.Unit I LI (6) Input Leakage Current (Any Input)–1—1–1—1μA I LO (7)Output L eakage C urrent

–10—10–10—10μA V OH Output Logic “1” Voltage I OH = –2mA 2.4—— 2.4——V V OL Output Logic “0” Voltage I OL = 8mA ——0.4——0.4V I CC1(8,9,10)Active Power Supply Current ——120——150mA I CC2(8,10,11)Standby Current (RS =FL /RT =V IH )——12——25mA I CC3(8,10,12)

Power Down Current

—

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times

5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output L oad

See Figure 1

30pF*

D.U.T.

or equivalent circuit

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DC ELECTRICAL CHARACTERISTICS

(Commercial: V CC = 5V ± 10%, T A = 0°C to +70°C; Industrial: V CC = 5V ± 10%, T A = –40°C to +85°C; Military: V CC = 5V ± 10%, T A = –55°C to +125°C)

6.Measurements with 0.4 ≤ V IN ≤ V CC .

7.R ≥ V IH , 0.4 ≤ V OUT ≤ V CC .

8.Tested with outputs open (I OUT = 0).

9.R and W toggle at 20 MHz and data inputs switch at 10 MHz.10.I CC measurements are made with outputs open.

11.All Inputs = V CC - 0.2V or GND + 0.2V, except R and W , which toggle at 20MHz.12.All Inputs = V CC - 0.2V or GND + 0.2V, except R and W = V CC -0.2V.

CAPACITANCE (1) (T A = +25°C, f = 1.0 MHz)

NOTES:

1.This parameter is sampled and not 100% tested.

2.With output deselected.

Symbol Parameter Condition Max.Unit C IN (1)Input Capacitance V IN = 0V 10pF C OUT (1,2)

Output C apacitance

V OUT = 0V

Figure 1. Output Load

*Includes jig and scope capacitances.

Commercial Com'l & Ind'l Com'l & Military Commercial Com'l & Ind'l IDT7203L12IDT7203L15(2)IDT7203L20IDT7208L20

IDT7203L25(2)IDT7204L12IDT7204L15(2)IDT7204L20IDT7204L25(2)IDT7205L12

IDT7205L15IDT7205L20IDT7205L25(3)IDT7206L15IDT7206L20IDT7206L25(3)IDT7207L15IDT7207L20IDT7207L25(3)IDT7208L25(3)Symbol Parameters

Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit f S Shift Frequency —50—40—33.3—33.3—28.5MHz t RC Read Cycle Time 20—25—30—30—35—ns t A Access Time

—12—15—20—20—25ns t RR Read Recovery Time 8—10—10—10—10—ns t RPW Read Pulse Width (4)

12—15—20—20—25—ns t RLZ Read LOW to Data Bus LOW (5)3—5—5—5—5—ns t WLZ Write HIGH to Data Bus Low-Z (5,6)3—5—5—5—5—ns t DV Data Valid from Read HIGH 5—5—5—5—5—ns t RHZ Read HIGH to Data Bus High-Z (5)—12—15—15—15—18ns t WC Write Cycle Time 20—25—30—30—35—ns t WPW Write Pulse Width (4)12—15—20—20—25—ns t WR Write Recovery Time 8—10—10—10—10—ns t DS Data Set-up Time 9—11—12—12—15—ns t DH Data Hold Time 0—0—0—0—0—ns t RSC Reset Cycle Time 20—25—30—30—35—ns t RS Reset Pulse Width (4)12—15—20—20—25—ns t RSS Reset Set-up Time (5)12—15—20—20—25—ns t RTR Reset Recovery Time 8—10—10—10—10—ns t RTC Retransmit Cycle Time 20—25—30—30—35—ns t RT Retransmit Pulse Width (4)12—15—20—20—25—ns t RTS Retransmit Set-up Time (5)12—15—20—20—25—ns t RTR Retransmit Recovery Time 8—10—10—10—10—ns t EFL

Reset to EF

LOW

—12—25—30—30—35ns t HFH , t FFH Reset to HF and FF HIGH —17—25—30—30—35ns t RTF Retransmit LOW to Flags Valid —20—25—30—30—35ns t REF Read LOW to EF LOW —12—15—20—20—25ns t RFF Read HIGH to FF HIGH

—14—15—20—20—25ns t RPE Read Pulse Width after EF HIGH 12—15—20—20—25—ns t WEF Write HIGH to EF HIGH —12—15—20—20—25ns t WFF Write LOW to FF

LOW —14—15—20—20—25ns t WHF Write LOW to HF Flag LOW —17—25—30—30—35ns t RHF Read HIGH to HF Flag HIGH —17—25—30—30—35ns t WPF Write Pulse Width after FF HIGH 12—15—20—20—25—ns t XOL Read/Write LOW to XO

LOW —12—15—20—20—25ns t XOH Read/Write HIGH to XO HIGH —12—15—20—20—25ns t XI XI Pulse Width (4)12—15—20—20—25—ns t XIR XI Recovery Time 8—10—10—10—10—ns t XIS XI Set-up Time 8—10

—

10—

—

AC ELECTRICAL CHARACTERISTICS (1)

(Commercial: V CC = 5V ± 10%, T A = 0°C to +70°C; Industrial: V CC = 5V ± 10%, T A = –40°C to +85°C; Military: V CC = 5V ± 10%, T A = –55°C to +125°C)

NOTES:

1.Timings referenced as in AC Test Conditions.

2.Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.

3.Industrial temperature range product for 25ns speed grade only is available as a standard device. All other speed grades are available by special order.

4.Pulse widths less than minimum are not allowed.

5.Values guaranteed by design, not currently tested.

6.Only applies to read data flow-through mode.

AC ELECTRICAL CHARACTERISTICS(1) (CONTINUED)

(Commercial: V CC = 5V ± 10%, T A = 0°C to +70°C; Industrial: V CC = 5V ± 10%, T A = –40°C to +85°C; Military: V CC = 5V ± 10%, T A = –55°C to +125°C)

NOTES:

1.Timings referenced as in AC Test Conditions.

2.Pulse widths less than minimum are not allowed.

3.Values guaranteed by design, not currently tested.

4.Only applies to read data flow-through mode.

Military Commercial Military Commercial IDT7203L30IDT7203L35IDT7203L40IDT7203L50 IDT7204L30IDT7204L35IDT7204L50 IDT7205L30IDT7205L35IDT7205L50 IDT7206L30IDT7206L35IDT7206L50 IDT7207L30IDT7207L35IDT7207L50

IDT7208L35

Symbol Parameters Min.Max.Min.Max.Min.Max.Min.Max.Unit f S Shift Frequency—25—22.22—20—15MHz t RC Read Cycle Time40—45—50—65—ns t A Access Time—30—35—40—50ns t RR Read Recovery Time10—10—10—15—ns t RPW Read Pulse Width(2)30—35—40—50—ns t RLZ Read LOW to Data Bus LOW(3)5—5—5—10—ns t WLZ Write HIGH to Data Bus Low-Z(3,4)5—10—10—15—ns t DV Data Valid from Read HIGH5—5—5—5—ns t RHZ Read HIGH to Data Bus High-Z(3)—20—20—25—30ns t WC Write Cycle Time40—45—50—65—ns t WPW Write Pulse Width(2)30—35—40—50—ns t WR Write Recovery Time10—10—10—15—ns t DS Data Set-up Time18—18—20—30—ns t DH Data Hold Time0—0—0—5—ns t RSC Reset Cycle Time40—45—50—65—ns t RS Reset Pulse Width(2)30—35—40—50—ns t RSS Reset Set-up Time(3)30—35—40—50—ns t RTR Reset Recovery Time10—10—10—15—ns t RTC Retransmit Cycle Time40—45—50—65—ns t RT Retransmit Pulse Width(2)30—35—40—50—ns t RTS Retransmit Set-up Time(3)30—35—40—50—ns t RTR Retransmit Recovery Time10—10—10—15—ns t EFL Reset to EF LOW—40—45—50—65ns t HFH, t FFH Reset to HF and FF HIGH—40—45—50—65ns t RTF Retransmit LOW to Flags Valid—40—45—50—65ns t REF Read LOW to EF LOW—30—30—35—45ns t RFF Read HIGH to FF HIGH—30—30—35—45ns t RPE Read Pulse Width after EF HIGH30—35—40—50—ns t WEF Write HIGH to EF HIGH—30—30—35—45ns t WFF Write LOW to FF LOW—30—30—35—45ns t WHF Write LOW to HF Flag LOW—40—45—50—65ns t RHF Read HIGH to HF Flag HIGH—40—45—50—65ns t WPF Write Pulse Width after FF HIGH30—35—40—50—ns t XOL Read/Write LOW to XO LOW—30—35—40—50ns t XOH Read/Write HIGH to XO HIGH—30—35—40—50ns t XI XI Pulse Width(2)30—35—40—50—ns t XIR XI Recovery Time10—10—10—10—ns t XIS XI Set-up Time10—15—15—15—ns

loaded (see O perating M odes). T he S ingle D evice M ode i s i nitiated b y g rounding the Expansion In (XI ).

The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data when the Retransmit Enable Control (RT ) input is pulsed LOW. A retransmit operation w ill s et t he i nternal r ead p ointer t o t he f irst l ocation a nd w ill n ot a ffect t he write p ointer. T he s tatus o f t he F lags w ill c hange d epending o n t he r elative l ocations of the read and write pointers. Read Enable (R ) and Write Enable (W ) must be in t he H IGH s tate d uring r etransmit. T his f eature i s u seful w hen l ess t han 2,048/4,096/8,192/16,384/32,768/65,536 w rites a re p erformed b etween r esets. T he retransmit f eature i s n ot c ompatible w ith t he D epth E xpansion M ode.EXPANSION IN ( XI ) — This input is a dual-purpose pin. Expansion In (XI )is g rounded t o i ndicate a n o peration i n t he s ingle d evice m ode. E xpansion I n (XI )is c onnected t o E xpansion O ut (XO ) o f t he p revious d evice i n t he D epth E xpansion or Daisy-Chain Mode.

OUTPUTS:

FULL FLAG ( FF ) — The Full Flag (FF ) will go LOW, inhibiting further write operations, w hen t he d evice i s f ull. I f t he r ead p ointer i s n ot m oved a fter R eset (RS ),the Full Flag (FF ) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536writes.

EMPTY FLAG ( EF ) — The Empty Flag (EF ) will go LOW, inhibiting further read o perations, w hen t he r ead p ointer i s e qual t o t he w rite p ointer, i ndicating t hat the device is empty.

EXPANSION O UT/HALF-FULL F LAG ( X O /HF ) — This i s a d ual-purpose output. I n t he s ingle d evice m ode, w hen E xpansion I n (XI ) i s g rounded, t his o utput acts a s a n i ndication o f a h alf-full m emory.

After h alf o f t he m emory i s f illed, a nd a t t he f alling e dge o f t he n ext w rite o peration,the Half-Full Flag (HF ) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total m emory o f t he d evice. T he H alf-Full F lag (HF ) i s t hen r eset b y t he r ising e dge of the read operation.

In t he D epth E xpansion M ode, E xpansion I n (XI ) i s c onnected t o E xpansion Out (XO ) of the previous device. This output acts as a signal to the next device in t he D aisy C hain b y p roviding a p ulse t o t he n ext d evice w hen t he p revious d evice reaches the last location of memory. There will be an XO pulse when the Write pointer r eaches t he l ast l ocation o f m emory, a nd a n a dditional X O p ulse w hen t he Read pointer reaches the last location of memory.

DATA OUTPUTS (Q 0-Q 8) — Q 0-Q 8 are data outputs for 9-bit wide data.These o utputs a re i n a h igh-impedance c ondition w henever R ead (R ) i s i n a H IGH state.

SIGNAL DESCRIPTIONS INPUTS:

DATA IN (D 0–D 8) — Data inputs for 9-bit wide data.

CONTROLS:

RESET ( RS ) — Reset is accomplished whenever the Reset (RS ) input is taken to a LOW state. During reset, both internal read and write pointers are set to t he f irst l ocation. A r eset i s r equired a fter p ower-up b efore a w rite o peration c an take place. Both the Read Enable (R ) and Write Enable (W ) inputs must be in the HIGH state during the window shown in Figure 2 (i.e. t RSS before the rising edge of RS ) and should not change until t RSR after the rising edge of RS .

WRITE ENABLE ( W ) — A write cycle is initiated on the falling edge of this input i f t he F ull F lag (FF ) i s n ot s et. D ata s et-up a nd h old t imes m ust b e a dhered-to, w ith r espect t o t he r ising e dge o f t he W rite E nable (W ). D ata i s s tored i n t he R AM array sequentially and independently of any on-going read operation.

After h alf o f t he m emory i s f illed, a nd a t t he f alling e dge o f t he n ext w rite o peration,the Half-Full Flag (HF ) will be set to LOW, and will remain set until the difference between t he w rite p ointer a nd r ead p ointer i s l ess-than o r e qual t o o ne-half o f t he total m emory o f t he d evice. T he H alf-Full F lag (HF ) i s t hen r eset b y t he r ising e dge of the read operation.

To prevent data overflow, the Full Flag (FF ) will go LOW on the falling edge of t he l ast w rite s ignal, w hich i nhibits f urther w rite o perations. U pon t he c ompletion of a valid read operation, the Full Flag (FF ) will go HIGH after t RFF , allowing a new v alid w rite t o b egin. W hen t he F IFO i s f ull, t he i nternal w rite p ointer i s b locked from W , so external changes in W will not affect the FIFO when it is full.READ E NABLE ( R ) — A r ead c ycle i s i nitiated o n t he f alling e dge o f t he R ead Enable (R ), provided the Empty Flag (EF ) is not set. The data is accessed on a F irst-In/First-Out b asis, i ndependent o f a ny o ngoing w rite o perations. A fter R ead Enable (R ) goes HIGH, the Data Outputs (Q 0 through Q 8) will return to a high-impedance c ondition u ntil t he n ext R ead o peration. W hen a ll t he d ata h as b een read from the FIFO, the Empty Flag (EF ) will go LOW, allowing the “final” read cycle b ut i nhibiting f urther r ead o perations, w ith t he d ata o utputs r emaining i n a h igh-impedance s tate. O nce a v alid w rite o peration h as b een a ccomplished, t he E mpty Flag (EF ) will go HIGH after t WEF and a valid Read can then begin. When the FIFO i s e mpty, t he i nternal r ead p ointer i s b locked f rom R s o e xternal c hanges w ill not affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT ( FL /RT ) — This is a dual-purpose input. In the D epth E xpansion M ode, t his p in i s g rounded t o i ndicate t hat i t i s t he f irst d evice

Figure 4. Full Flag Timing From Last Write to First Read

NOTE:

1. W and R = V IH around the rising edge of RS .

Figure 2. Reset

Figure 3. Asynchronous Write and Read Operation

RS R

HF , FF

D 0-D 8

Q 0-Q 8

R W

NOTE:

1. EF , FF and HF may change status during Retransmit, but flags will be valid at t RTC .

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.

Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse.

DATA OUT

W,R

HF, EF, FF

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Figure 6. Retransmit

Figure 9. Half-Full Flag Timing Figure 10. Expansion Out

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag is monitored by each s ystem (i.e. F F i s m onitored o n t he d evice w here W i s u sed; E F i s m onitored on t he d evice w here R i s u sed). F or a dditional i nformation o n t he I DT7203/7204/ 7205/7206/7207, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs.

Single Device Mode

A single IDT7203/7204/7205/7206/7207/7208 may be used when the application requirements are for 2,048/4,096/8,192/16,384/32,768/65,536 words or less. These FIFOs are in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12).

Depth Expansion

These FIFOs can easily be adapted to applications when the require-ments are for greater than 2,048/4,096/8,192/16,384/32,768/65,536 words. Figure 14 demonstrates Depth Expansion using three IDT7203/7204/7205/ 7206/7207/7208s. Any depth can be attained by adding additional IDT7203/7204/7205/7206/7207/7208s. These devices operate in the Depth Expansion mode when the following conditions are met:

1.The f irst d evice m ust b e d esignated b y g rounding t he F irst L oad (FL) c ontrol

input.

2.All other devices must have FL in the HIGH state.

3.The Expansion Out (XO) pin of each device must be tied to the Expansion

In (XI) pin of the next device. See Figure 14.

4.External logic is needed to generate a composite Full Flag (FF) and Empty

Flag (EF). This requires the ORing of all EF s and ORing of all FF s (i.e. all must be set to generate the correct composite FF or EF). See Figure 14.

5.The Retransmit (RT) function and Half-Full Flag (HF) are not available in

the Depth Expansion Mode.

For additional information on the IDT7203/7204/7205/7206/7207, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.

W R HF

W R XO

W R

WRITE (W )FULL FLAG (FF )

RESET (RS )

DATA (D)IN READ (R )

EMPTY FLAG (EF )RETRANSMIT (RT )

DATA

(Q)

OUT 2661 drw15

USAGE MODES:

Width Expansion

Word w idth m ay b e i ncreased s imply b y c onnecting t he c orresponding i nput control s ignals o f m ultiple d evices. S tatus f lags (EF , F F a nd H F ) c an b e d etected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT7203/7204/7205/7206/7207/7208s. Any word width can be attained by adding additional IDT7203/7204/7205/7206/7207/7208s (Figure 13).Bidirectional Operation

Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7203/7204/7205/7206/7207/7208s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), the

FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (t WEF + t A ) ns after the rising edge of W , called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after t RHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted.

In the write flow-through mode (Figure 18), the FIFO permits the writing of a s ingle w ord o f d ata i mmediately a fter r eading o ne w ord o f d ata f rom a f ull F IFO.The R line causes the FF to be deasserted but the W line being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W , the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write https://www.wendangku.net/doc/a015534199.html,pound Expansion

The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15).

NOTE:

1.Flag detection is accomplished by monitoring the FF

, EF and HF signals on either (any) device used in the width expansion configuration.

Do not connect any output signals together.

Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode

WRITE (W FULL FLAG (FF RESET (RS READ (R )

DATA OUT (Q)EMPTY FLAG (EF )RETRANSMIT (RT )

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Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode

TRUTH TABLES

TABLE 1 – RESET AND RETRANSMIT

SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE

NOTE:

1. Pointer will Increment if flag is HIGH.

TABLE 2 – RESET AND FIRST LOAD

DEPTH EXPANSION/COMPOUND EXPANSION MODE

NOTES:

1. XI is connected to XO of previous device. See Figure 14.

2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output

Figure 14. Block Diagram of 6,144 x 9, 12,288 x 9, 24,576 x 9, 49,152 x 9, 98,304 x 9, 196,608 x 9 FIFO Memory (Depth Expansion)

EMPTY

V CC

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Inputs Internal Status

Outputs

Mode

RS FL /RT XI Read Pointer Write Pointer EF FF

HF Reset 0X 0Location Z ero Location Z ero 011Retransmit 100Location Z ero Unchanged X X X Read/Write

Increment (1)

Inputs Internal Status

Outputs Mode

RS FL /RT XI Read Pointer Write Pointer EF FF Reset First Device

00(1)Location Z ero Location Z ero 01Reset All Other Devices 01(1)Location Z ero

Location Z ero

01Read/Write

(1)

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 1

3..

Figure 16. Bidirectional FIFO Operation

SYSTEM A SYSTEM B

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R , W , RS

D 0-D N

D 9-D N

D 18-D N

D (N-8)-D N

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Q (N-8)-Q N Figure 15. Compound FIFO Expansion

Figure 17. Read Data Flow-Through Mode

DATA R

DATA OUT

Figure 18. Write Data Flow-Through Mode

DATA IN

DATA

OUT

CORPORATE HEADQUARTERS for SALES:

for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200408-360-1753

San Jose, CA 95138

fax: 408-284-2775email: F IFOhelp@https://www.wendangku.net/doc/a015534199.html,

https://www.wendangku.net/doc/a015534199.html,

ORDERING INFORMATION

NOTES:

1.Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device for IDT7203/7204, and 25ns speed grade only is available as a standard device for IDT7205/7206/7207/7208. All other speed grades are available by special order.

2.The LCC is only available in the military temperature range.

3.The IDT7208 is only available in commercial speed grades of 20, 25 and 35 ns.

4.Green parts are available. For specific speeds and packages contact your local sales office.

5.For "P", Plastic Dip, when ordering green package, the suffix is "PDG".

Power

XX Speed

X Package

Process/Temperature Range

Blank Commercial (0°C to +70°C) I (1)B Industrial (?40° to +85°C)Military (?55°C to +125°C)

Compliant to MIL-STD-883, Class B P (5)TP D TD J L (2)SO Plastic DIP P28-1Plastic Thin DIP P28-2(all except 7207/7208)CERDIP D28-1 (all except 7208)

Thin CERDIP D28-3 (only for 7203/7204/7205)Plastic Leaded Chip Carrier PLCC J32-1Leadless Chip Carrier LCC L32-1 (all except 7208)Small Outline IC SOIC SO28-3 (only 7204)

121520(3)25(3)3035(3)4050 Commercial 7203/04/05 Only

Commercial and (Industrial only 7203/04)Commercial and Military Commercial and Industrial Military Only

Commercial Only Military 7203 Only Commercial Only XXXX

Device Type 7203 ?7204 ?7205 ?7206 ?7207 ?7208(3)

IDT

L Low Power Access Time (t A )Speed in

Nanoseconds

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2,048 x9 FIFO 4,096 x 9 FIFO 8,192 x 9 FIFO 16,384 x 9 FIFO 32,768 x 9 FIFO 65,536 x 9 FIFO

Green

(4)

DATA SHEET HISTORY

05/10/2001pgs. 2, 3, 4, 5, 11 and 14.05/30/2001pg. 2.

04/03/2006

pgs. 1 and 14.