IC datasheet pdf-PCA9545A,pdf(4-CHANNEL I2C AND SMBus SWITCH)

https://www.wendangku.net/doc/ae18841277.html, FEATURES

RGY PACKAGE (TOP VIEW)2A119SDA 3RESET 18SCL 4INT017INT 5SD016SC36SC015SD37INT114INT38SD113SC29SC112SD2110A 0G N D 2011I N T 2

V C C

RESET INT0SD0SC0INT1INT SC3SD3INT3SC2RGW PACKAGE (TOP VIEW)

S D A S C L A 1

A 0

V C C

DGV ,DW,OR PW PACKAGE

(TOP VIEW)

DESCRIPTION/ORDERING INFORMATION PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006

?

1-of-4Bidirectional Translating Switches ?No Glitch on Power Up ?

I 2C Bus and SMBus Compatible ?Supports Hot Insertion ?

Four Active-Low Interrupt Inputs ?Low Standby Current ?

Active-Low Interrupt Output ?Operating Power-Supply Voltage Range of 2.3V to 5.5V ?

Active-Low Reset Input ? 5.5-V Tolerant Inputs ?

Two Address Pins,Allowing up to Four Devices on the I 2C Bus ?0to 400-kHz Clock Frequency ?

Channel Selection Via I 2C Bus,In Any ?Latch-Up Performance Exceeds 100mA Per Combination JESD 78?

Power Up With All Switch Channels ?ESD Protection Exceeds JESD 22Deselected –2000-V Human-Body Model (A114-A)?

Low R ON Switches

–200-V Machine Model (A115-A)?Allows Voltage-Level Translation Between

–1000-V Charged-Device Model (C101)1.8-V,2.5-V,3.3-V,and 5-V Buses

The PCA9545A is a quad bidirectional translating switch controlled via the I 2C bus.The SCL/SDA upstream pair fans out to four downstream pairs,or channels.Any individual SCn/SDn channel or combination of channels can be selected,determined by the contents of the programmable control register.Four interrupt inputs (INT3–INT0),one for each of the downstream pairs,are provided.One interrupt (INT)output acts as an AND of the four interrupt inputs.

An active-low reset (RESET)input allows the PCA9545A to recover from a situation in which one of the downstream I 2C buses is stuck in a low state.Pulling RESET low resets the I 2C state machine and causes all the channels to be deselected,as does the internal power-on reset function.

The pass gates of the switches are constructed such that the V CC pin can be used to limit the maximum high voltage,which will be passed by the PCA9545A.This allows the use of different bus voltages on each pair,so that 1.8-V,2.5-V,or 3.3-V parts can communicate with 5-V parts,without any additional protection.External pullup resistors pull the bus up to the desired voltage level for each channel.All I/O pins are 5.5-V tolerant.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

https://www.wendangku.net/doc/ae18841277.html, DESCRIPTION/ORDERING INFORMATION (CONTINUED)

GQN OR ZQN PACKAGE

(TOP VIEW)1234A

B

C

D

E PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006ORDERING INFORMATION

T A

PACKAGE (1)ORDERABLE PART NUMBER TOP-SIDE MARKING QFN –RGW

Reel of 3000PCA9545ARGWR PD545A QFN –RGY

Reel of 1000PCA9545ARGYR PD545A Tube of 25PCA9545ADW PCA9545A SOIC –DW Reel of 2000

PCA9545ADWR Reel of 250

PCA9545ADWT PCA9545A PCA9545APW PD545A Tube of 70

PCA9545APWE4–40°C to 85°C PCA9545APWR PD545A TSSOP –PW Reel of 2000

PCA9545APWRE4PCA9545APWT PD545A Reel of 250

PCA9545APWTE4Reel of 2000PCA9545ADGVR TVSOP –DGV

PD545A Reel of 250PCA9545ADGVT VFBGA –GQN

Reel of 1000PCA9545AGQNR PD545A VFBGA –ZQN (Pb-free)

Reel of 1000PCA9545AZQNR PD545A (1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at https://www.wendangku.net/doc/ae18841277.html,/sc/package.

TERMINAL ASSIGNMENTS 1234A A1A0V CC SDA B INT0INT RESET SCL C SC0SD0SD3SC3D SD1SC2INT1INT3E GND SC1INT2SD2

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PCA9545A

4-CHANNEL I2C AND SMBus SWITCH

WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER2005–REVISED OCTOBER2006 TERMINAL FUNCTIONS

NO.

NAME DESCRIPTION

DGV,DW,PW,GQN AND

RGW

AND RGY ZQN

119A2A0Address input0.Connect directly to V CC or ground.

220A1A1Address input1.Connect directly to V CC or ground.

Active-low reset input.Connect to V CC through a pullup 31B3RESET

resistor,if not used.

Active-low interrupt input0.Connect to V CC through a 42B1INT0

pullup resistor.

53C2SD0Serial data0.Connect to V CC through a pullup resistor.

64C1SC0Serial clock0.Connect to V CC through a pullup resistor.

Active-low interrupt input1.Connect to V CC through a 75D3INT1

pullup resistor.

86D1SD1Serial data1.Connect to V CC through a pullup resistor.

97E2SC1Serial clock1.Connect to V CC through a pullup resistor.

108E1GND Ground

Active-low interrupt input2.Connect to V CC through a 119E3INT2

pullup resistor.

1210E4SD2Serial data2.Connect to V CC through a pullup resistor.

1311D2SC2Serial clock2.Connect to V CC through a pullup resistor.

Active-low interrupt input3.Connect to V CC through a 1412D4INT3

pullup resistor.

1513C3SD3Serial data3.Connect to V CC through a pullup resistor.

1614C4SC3Serial clock3.Connect to V CC through a pullup resistor.

Active-low interrupt output.Connect to V CC through a pullup 1715B2INT

resistor.

1816B4SCL Serial clock line.Connect to V CC through a pullup resistor.

1917A4SDA Serial data line.Connect to V CC through a pullup resistor.

2018A3V CC Supply power

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Pin numbers shown are for DGV, DW, PW, and RGY packages.

PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006BLOCK DIAGRAM

https://www.wendangku.net/doc/ae18841277.html, Device Address

Fixed Hardware

Selectable

Control Register

Interrupt Bits

(Read Only)

Channel-Selection Bits

(Read/Write)Channel 0

Channel 1

Channel 2Channel 3

INT0

INT1

INT2

INT3Control Register Definition PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Following a start condition,the bus master must output the address of the slave it is accessing.The address of the PCA9545A is shown in Figure 1.To conserve power,no internal pullup resistors are incorporated on the hardware-selectable address they must be pulled high or low.

Figure 1.PCA9545A Address

The last bit of the slave address defines the operation to be performed.When set to a logic 1,a read is selected,while a logic 0selects a write operation.

Following the successful acknowledgment of the slave address,the bus master sends a byte to the PCA9545A,which is stored in the control register (see Figure 2).If multiple bytes are received by the PCA9545A,it saves the last byte received.This register can be written and read via the I 2C bus.

Figure 2.Control Register

One or several SCn/SDn downstream pairs,or channels,are selected by the contents of the control register (see Table 1).After the PCA9545A has been addressed,the control register is written.The four LSBs of the used to determine which channel or channels are to be selected.When a channel is selected,the channel becomes active after a stop condition has been placed on the I 2C bus.This ensures that all SCn/SDn lines are in a high state when the channel is made active,so that no false conditions are generated at the time of connection.A stop condition must occur always right after the acknowledge cycle.

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Interrupt Handling PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Table 1.Control Register Write (Channel Selection),Control Register Read (Channel Status)(1)INT3

INT2INT1INT0D3B2B1B0COMMAND 0Channel 0disabled X

X X X X X X 1Channel 0enabled 0Channel 1disabled X

X X X X X X 1Channel 1enabled 0Channel 2disabled X

X X X X X X 1Channel 2enabled 0Channel 3disabled X

X X X X X X 1Channel 3enabled No channel selected,0

00000X 0power-up/reset default state (1)Several channels can be enabled at the same time.For example,B3=0,B2=1,B1=1,B0=0means that channels 0and 3are disabled,and channels 1are 2and enabled.Care should be taken not to exceed the maximum bus capacity.

The PCA9545A provides four interrupt inputs (one for each channel)and one open-drain interrupt output (see Table 2).When an interrupt is generated by any device,it is detected by the PCA9545A and the interrupt output low.The channel does not need to be active for detection of the interrupt.A bit also is set in the control register.

Bits 4–7of the control register correspond to channels 0–3of the PCA9545A,respectively.Therefore,if an interrupt is generated by any device connected to channel 1,the state of the interrupt inputs is loaded into the control register when a read is accomplished.Likewise,an interrupt on any device connected to channel 0would cause bit 4of the control register to be set on the read.The master then can address the PCA9545A and read the contents of the control register to determine which channel contains the device generating the interrupt.The master then can reconfigure the PCA9545A to select this channel and locate the device generating the interrupt and clear it.

It should be noted that more than one device can provide an interrupt on a channel,so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt.

The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.

If unused,interrupt input(s)must be connected to V CC .

Table 2.Control Register Read (Interrupt)(1)

INT3

INT2INT1INT0D3B2B1B0COMMAND 0No interrupt on channel 0X

X X X X X X 1Interrupt on channel 00No interrupt on channel 1X

X X X X X X 1Interrupt on channel 10No interrupt on channel 2X

X X X X X X 1Interrupt on channel 20

No interrupt on channel 3X X X X X X X 1

Interrupt on channel 3(1)Several interrupts can be active at the same time.For example,INT3=0,INT2=1,INT1=1,INT0=0means that there is no interrupt on channels 0and 3,and there is interrupt on channels 1and 2.

https://www.wendangku.net/doc/ae18841277.html, RESET Input

Power-On Reset

Voltage Translation

V CC (V)

3

2.5

2

V p a s s (V )I 2C Interface PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006The RESET input can be used to recover the PCA9545A from a bus-fault condition.The registers and the I 2C state machine within this device initialize to their default states if this signal is asserted low for a minimum of t WL .All channels also are deselected in this case.RESET must be connected to V CC through a pullup resistor.

When power is applied to V CC ,an internal power-on reset holds the PCA9545A in a reset condition until V CC has reached V POR .At this point,the reset condition is released and the PCA9545A registers and I 2C state machine are initialized to their default states,all zeroes,causing all the channels to be deselected.Thereafter,V CC must be lowered below 0.2V to reset the device.

The pass-gate transistors of the PCA9545A are constructed such that the V CC voltage can be used to limit the maximum voltage that is passed from one I 2C bus to another.

Figure 3shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using in the electrical characteristics section of this data sheet).In order for the PCA9545A to act as a voltage translator,the V pass voltage must be equal to or lower than the lowest bus voltage.For example,if the main bus is running at 5V and the downstream buses are 3.3V and 2.7V,V pass must be equal to or below 2.7V to effectively clamp the downstream bus voltages.As shown in Figure 3,V pass (max)is at 2.7V when the PCA9545A supply voltage is 3.5V or lower,so the PCA9545A could be set to 3.3V.Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 13).

Figure 3.V pass Voltage vs V CC

The I 2C bus is for two-way two-line communication between different ICs or modules.The two lines are a serial data line (SDA)and a serial clock line (SCL).Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device.Data transfer can be initiated only when the bus is not busy.

One data bit is transferred during each clock pulse.The data on the SDA line must remain stable during the high period of the clock pulse,as changes in the data line at this time are interpreted as control signals (see Figure 4).

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SDA SCL

Data Line

Stable;

Data Valid Change of Data Allowed

SDA

SCL Start Condition S

Stop Condition

P SCL

SDA PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Figure 4.Bit Transfer

Both data and clock lines remain high when the bus is not busy.A high-to-low transition of the data line while the clock is high is defined as the start condition (S).A low-to-high transition of the data line while the clock is high is defined as the stop condition (P)(see Figure 5).

Figure 5.Definition of Start and Stop Conditions

A device generating a message is a transmitter;a device receiving a message is the receiver.The device that controls the message is the master,and the devices that are controlled by the master are the slaves (see Figure 6).

Figure 6.System Configuration

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited.Each byte of eight bits is followed by one acknowlege (ACK)bit.The transmitter must release the SDA line before the receiver can send an ACK bit.

When a slave receiver is addressed,it must generate an ACK after the reception of each byte.Also,a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter.The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7).Setup and hold times must be taken into account.

https://www.wendangku.net/doc/ae18841277.html, Data Output

by Transmitter

SCL From

Master

Start

Condition

Data Output

by Receiver

Clock Pulse for ACK

SDA

SDA Start Condition R/W ACK From Slave NACK From Master Stop Condition

PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Figure 7.Acknowledgment on the I 2C Bus

A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK)after the last byte has been clocked out of the slave.This is done by the master receiver by holding the SDA line high.In this event,the transmitter must release the data line to enable the master to generate a stop condition.Data is transmitted to the PCA9545A control register using the write mode shown in Figure 8.

Figure 8.Write Control Register

Data is read from the PCA9545A control register using the read mode shown in Figure 9.

Figure 9.Read Control Register

https://www.wendangku.net/doc/ae18841277.html, Absolute Maximum Ratings (1)

Recommended Operating Conditions (1)PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT V CC

Supply voltage range –0.57V V I

Input voltage range (2)–0.57V I I

Input current ±20mA I O Output current

±25mA Continuous current through V CC

±100mA Continuous current through GND

±100mA DGV package

92DW package

58GQN/ZQN package

78θJA Package thermal impedance (3)°C/W PW package

83RGW package

TBD RGY package

47P tot

Total power dissipation 400mW T stg

Storage temperature range –65150°C T A

Operating free-air temperature range –4085°C (1)

Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3)The package thermal impedance is calculated in accordance with JESD 51-7.

MIN

MAX UNIT V CC

Supply voltage 2.3 5.5V SCL,SDA 0.7×V CC 6V IH

High-level input voltage V A1,A0,INT3–INT0,RESET 0.7×V CC V CC +0.5SCL,SDA –0.50.3×V CC V IL

Low-level input voltage V A1,A0,INT3–INT0,RESET –0.50.3×V CC T A

Operating free-air temperature –4085°C (1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.

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Electrical Characteristics

PCA9545A

4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER2005–REVISED OCTOBER2006

over recommended operating free-air temperature range(unless otherwise noted)

PARAMETER TEST CONDITIONS V CC MIN TYP(1)MAX UNIT V POR Power-on reset voltage(2)No load,V I=V CC or GND V POR 1.6 2.1V

5V 3.6

4.5V to

5.5V 2.6 4.5

3.3V 1.9

V pass Switch output voltage V SWin=V CC,I SWout=–100μA V

3V to3.6V 1.6 2.8

2.5V 1.5

2.3V to2.7V 1.12

I OH INT V O=V CC 2.3V to5.5V10μA

V OL=0.4V37 SCL,SDA

I OL V OL=0.6V 2.3V to5.5V610mA

INT V OL=0.4V3

SCL,SDA±1

SC3–SC0,SD3–SD0±1

I I A1,A0V I=V CC or GND 2.3V to5.5V±1μA

INT3–INT0±1

RESET±1

5.5V312

Operating mode f SCL=100kHz V I=V CC or GND,I O=0 3.6V311

2.7V310

5.5V0.31

I CC Low inputs V I=GND,I O=0 3.6V0.11μA

2.7V0.11

Standby mode

5.5V0.31

High inputs V I=V CC,I O=0 3.6V0.11

2.7V0.11

One INT3–INT0input at0.6V,

815

Other inputs at V CC or GND

INT3–INT0

One INT3–INT0input at V CC–0.6V,

815

Other inputs at V CC or GND

Supply-current

?I CC 2.3V to5.5VμA change SCL or SDA input at0.6V,

815

Other inputs at V CC or GND

SCL,SDA

SCL or SDA input at V CC–0.6V,

815

Other inputs at V CC or GND

A1,A0 4.56

C i INT3–INT0V I=V CC or GN

D 2.3V to5.5V 4.56pF

RESET 4.5 5.5

SCL,SDA1519

C io(OFF)(3)V I=V CC or GND,Switch OFF 2.3V to5.5V pF

SC3–SC0,SD3–SD068

4.5V to

5.5V4916

V O=0.4V,I O=15mA

R ON Switch on-state resistance3V to3.6V51120?

V O=0.4V,I O=10mA 2.3V to2.7V71645

(1)All typical values are at nominal supply voltage(2.5-V,3.3-V,or5-V V CC),T A=25°C.

(2)The power-on reset circuit resets the I2C bus logic with V CC

(3)C io(ON)depends on the device capacitance and load that is downstream from the device.

https://www.wendangku.net/doc/ae18841277.html, I 2C Interface Timing Requirements

Switching Characteristics PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006over recommended operating free-air temperature range (unless otherwise noted)(see Figure 10)

STANDARD MODE

FAST MODE I 2C BUS

I 2C BUS UNIT MIN

MAX MIN MAX f scl

I 2C clock frequency 01000400kHz t sch

I 2C clock high time 40.6μs t scl

I 2C clock low time 4.7 1.3μs t sp

I 2C spike time 5050ns t sds

I 2C serial-data setup time 250100ns t sdh

I 2C serial-data hold time 0(1)0(1)μs t icr

I 2C input rise time 100020+0.1C b (2)300ns t icf

I 2C input fall time 30020+0.1C b (2)300ns t ocf

I 2C output fall time 10-pF to 400-pF bus 30020+0.1C b (2)300ns t buf

I 2C bus free time between stop and start 4.7 1.3μs t sts

I 2C start or repeated start condition setup 4.70.6μs t sth

I 2C start or repeated start condition hold 40.6μs t sps

I 2C stop condition setup 40.6μs SCL low to SDA output low t vdL(Data)

Valid-data time (high to low)(3)11μs valid SCL low to SDA output high t vdH(Data)

Valid-data time (low to high)(3)0.60.6μs valid ACK signal from SCL low t vd(ack)

Valid-data time of ACK condition 11μs to SDA output low C b

I 2C bus capacitive load 400400pF (1)

A device internally must provide a hold time of at least 300ns for the SDA signal (referred to as the V IH min of the SCL signal),in order to bridge the undefined region of the falling edge of SCL.(2)

C b =total bus capacitance of one bus line in pF

(3)Data taken using a 1-k ?pullup resistor and 50-pF load (see Figure 10)

over recommended operating free-air temperature range,C L ≤100pF (unless otherwise noted)(see Figure 12)

FROM TO PARAMETER

MIN MAX UNIT (INPUT)(OUTPUT)R ON =20?,C L =15pF 0.3t pd (1)

Propagation delay time SDA or SCL SDn or SCn ns R ON =20?,C L =50pF 1t iv

Interrupt valid time (2)INTn INT 4μs t ir

Interrupt reset delay time (2)INTn INT 2μs (1)

The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,when driven by an ideal voltage source (zero output impedance).(2)Data taken using a 4.7-k ?pullup resistor and 100-pF load (see Figure 12)

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Interrupt and Reset Timing Requirements

PCA9545A

4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER2005–REVISED OCTOBER2006

over recommended operating free-air temperature range(unless otherwise noted)(see Figure12)

PARAMETER MIN MAX UNIT t PWRL Low-level pulse duration rejection of INTn inputs1μs t PWRH High-level pulse duration rejection of INTn inputs0.5μs t WL Pulse duration,RESET low6ns t rst(1)RESET time(SDA clear)500ns t REC(STA)Recovery time from RESET to start0ns

(1)t rst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,

signaling a stop condition.It must be a minimum of t WL.

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PARAMETER MEASUREMENT INFORMATION

= 1 k ?

L = 50 pF

0.3 × V CC Condition Condition Start Condition

SCL

SDA

I 2C PORT LOAD CONFIGURATION

VOLTAGE WAVEFORMS 0.7 × V CC

0.3 × V CC

0.7 × V CC PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006A.

C L includes probe and jig capacitance.B.

All input pulses are supplied by generators having the following characteristics:PRR ≤10MHz,Z O =50?,t r /t f =30ns.C.The outputs are measured one at a time,with one transition per measurement.

Figure 10.I 2C Interface Load Circuit,Byte Descriptions,and Voltage Waveforms

https://www.wendangku.net/doc/ae18841277.html, SCL SDA

LEDx RESET

Start

ACK or Read Cycle

L = 4.7 k ?

L = 100 pF

INTERRUPT LOAD CONFIGURATION

V CC

INTn (input)VOLTAGE WAVEFORMS (t iv )VOLTAGE WAVEFORMS (t ir )INT

(output)

0.5 × V CC INTn (input)INT (output)× V CC 0.5 × V CC

PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 11.Reset Timing

A.

C L includes probe and jig capacitance.B.All input pulses are supplied by generators having the following characteristics:PRR ≤10MHz,Z O =50?,

t r /t f =30ns.

Figure 12.Interrupt Load Circuit and Voltage Waveforms

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APPLICATION INFORMATION

Channel 0Channel 1Channel 2Channel 3PCA9545A 4-CHANNEL I 2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS

SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Figure 13shows an application in which the PCA9545A can be used.

A.If the device generating the interrupt has an open-drain output structure or can be 3-stated,a pullup resistor is

required.If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated,a pullup

resistor is not required.The interrupt inputs should not be left floating.

B.

Pin numbers shown are for DGV,DW,PW,and RGY packages.Figure 13.Typical Application

PACKAGING INFORMATION

Orderable Device Status(1)Package

Type Package

Drawing

Pins Package

Qty

Eco Plan(2)Lead/Ball Finish MSL Peak Temp(3)

PCA9545ADGVR ACTIVE TVSOP DGV202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545ADGVRG4ACTIVE TVSOP DGV202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545ADW ACTIVE SOIC DW2025Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545ADWG4ACTIVE SOIC DW2025Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545ADWR ACTIVE SOIC DW202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545ADWRG4ACTIVE SOIC DW202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545AGQNR NRND BGA MI

CROSTA

R JUNI

OR

GQN201000TBD SNPB Level-1-240C-UNLIM

PCA9545APW ACTIVE TSSOP PW2070Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWE4ACTIVE TSSOP PW2070Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWG4ACTIVE TSSOP PW2070Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWR ACTIVE TSSOP PW202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWRE4ACTIVE TSSOP PW202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWRG4ACTIVE TSSOP PW202000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWT ACTIVE TSSOP PW20250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWTE4ACTIVE TSSOP PW20250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545APWTG4ACTIVE TSSOP PW20250Green(RoHS&

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

PCA9545ARGYR ACTIVE VQFN RGY203000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-2-260C-1YEAR

PCA9545ARGYRG4ACTIVE VQFN RGY203000Green(RoHS&

no Sb/Br)

CU NIPDAU Level-2-260C-1YEAR

PCA9545AZQNR ACTIVE BGA MI

CROSTA

R JUNI

OR ZQN201000Green(RoHS&

no Sb/Br)

SNAGCU Level-1-260C-UNLIM

(1)The marketing status values are defined as follows:

ACTIVE:Product device recommended for new designs.

LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.

NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.

PREVIEW:Device has been announced but is not in production.Samples may or may not be available.

OBSOLETE:TI has discontinued the production of the device.

(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check

https://www.wendangku.net/doc/ae18841277.html,/productcontent for the latest availability information and additional product content details.

TBD:The Pb-Free/Green conversion plan has not been defined.

Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.

Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)

(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL

INFORMATION *All dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant PCA9545ADGVR TVSOP

DGV 202000330.012.4 6.9 5.6 1.68.012.0Q1PCA9545ADWR SOIC

DW 202000330.024.410.813.0 2.712.024.0Q1PCA9545AGQNR BGA MI

CROSTA

R JUNI

OR

GQN 201000330.012.4 3.3 4.3 1.68.012.0Q1PCA9545APWR TSSOP

PW 202000330.016.4 6.957.1 1.68.016.0Q1PCA9545ARGYR VQFN

RGY 203000330.012.4 3.8 4.8 1.68.012.0Q1PCA9545AZQNR BGA MI

CROSTA

R JUNI

OR ZQN 201000330.012.4 3.3 4.3 1.68.012.0Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) PCA9545ADGVR TVSOP DGV202000346.0346.029.0 PCA9545ADWR SOIC DW202000346.0346.041.0 PCA9545AGQNR BGA MICROSTAR

JUNIOR

GQN201000340.5338.120.6 PCA9545APWR TSSOP PW202000346.0346.033.0 PCA9545ARGYR VQFN RGY203000346.0346.029.0

PCA9545AZQNR BGA MICROSTAR

JUNIOR ZQN201000340.5338.120.6