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MC74HC595A 规格书推荐

MC74HC595A 规格书推荐
MC74HC595A 规格书推荐

MC74HC595A

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs

High?Performance Silicon?Gate CMOS

The MC74HC595A consists of an 8?bit shift register and an 8?bit D?type latch with three?state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8?bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.

The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

Features

?Output Drive Capability: 15 LSTTL Loads

?Outputs Directly Interface to CMOS, NMOS, and TTL ?Operating V oltage Range: 2.0 to 6.0 V ?Low Input Current: 1.0 m A

?High Noise Immunity Characteristic of CMOS Devices ?In Compliance with the Requirements Defined by JEDEC Standard No. 7A

?Chip Complexity: 328 FETs or 82 Equivalent Gates ?

Improvements over HC595

?Improved Propagation Delays ?50% Lower Quiescent Power

?Improved Input Noise and Latchup Immunity

?NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC?Q100

Qualified and PPAP Capable

?

These Devices are Pb?Free, Halogen Free and are RoHS Compliant

https://www.wendangku.net/doc/b92529082.html,

MARKING DIAGRAMS

A =Assembly Location WL, L =Wafer Lot YY , Y =Year

WW, W =Work Week

G, G

= Pb?Free Package

See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

SOIC?16

TSSOP?161

16

HC595AG

AWLYWW HC 595A ALYW G G

1

16

(Note: Microdot may be in either location)

SOIC?16D SUFFIX CASE 751B TSSOP?16DT SUFFIX CASE 948F

QFN16MN SUFFIX CASE 485AW

QFN16*

*V595A marking used for NLV74HC595AMN1TWG

Figure 1. Pin Assignments

116

2153144135126117

1089

GND V CC SQ H

GND

LATCH CLOCK OUTPUT ENABLE A

Q A V CC SQ H

RESET SHIFT CLOCK Q E Q D Q C Q B GND

Q H Q G Q

F Q B

Q E Q D Q C Q H

Q G Q F LATCH CLOCK OUTPUT ENABLE A

Q

A RESET

SHIFT CLOCK SOIC, TSSOP

QFN

LOGIC DIAGRAM

SERIAL DATA INPUT

SHIFT CLOCK

RESET LATCH CLOCK OUTPUT ENABLE

Q A Q B Q C Q D Q E Q F Q G Q H

SQ H

A PARALLEL DATA OUTPUTS

SERIAL DATA OUTPUT

MAXIMUM RATINGS

Symbol Parameter

Value Unit V CC DC Supply Voltage (Referenced to GND)–0.5 to +7.0V V in DC Input Voltage (Referenced to GND)–0.5 to V CC +0.5V V out DC Output Voltage (Referenced to GND)–0.5 to V CC +0.5

V I in DC Input Current, per Pin ±20mA I out DC Output Current, per Pin

±35mA I CC DC Supply Current, V CC and GND Pins ±75mA P D Power Dissipation in Still Air,SOIC Package?TSSOP Package?

500450mW T stg Storage Temperature

–65 to +150

_C T L Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP , SOIC or TSSOP Package)260_C

V ESD

ESD Withstand Voltage Human Body Model (Note 1)

Machine Model (Note 2)

Charged Device Model (Note 3)

> 3000> 400N/A

V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

?Derating:SOIC Package: –7 mW/_C from 65_ to 125_C

TSSOP Package: ?6.1 mW/_C from 65_ to 125_C

1.Tested to EIA/JESD22?A114?A.

2.Tested to EIA/JESD22?A115?A.

3.Tested to JESD22?C101?A.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter

Min Max Unit V CC DC Supply Voltage (Referenced to GND) 2.0 6.0V V in , V out

DC Input Voltage, Output Voltage (Referenced to GND)

0V CC V T A Operating Temperature, All Package Types –55+125_C t r , t f

Input Rise and Fall Time V CC = 2.0 V (Figure 1)

V CC = 4.5 V V CC = 6.0 V

000

1000500400

ns

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir-cuit. For proper operation, V in and V out should be constrained to the range GND v (V in or V out ) v V CC .Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ).Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol Parameter Test Conditions V CC

V

Guaranteed Limit

Unit –55 to 25_C≤ 85_C≤ 125_C

V IH Minimum High?Level Input Voltage V out = 0.1 V or V CC – 0.1 V

|I out| ≤ 20 m A

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

V

V IL Maximum Low?Level Input Voltage V out = 0.1 V or V CC – 0.1 V

|I out| ≤ 20 m A

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

V

V OH Minimum High?Level Output Voltage, Q A ? Q H V in = V IH or V IL

|I out| ≤ 20 m A

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

V in = V IH or V IL|I out| ≤ 2.4 mA

|I out| ≤ 6.0 mA

|I out| ≤ 7.8 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.2

3.7

5.2

V OL Maximum Low?Level Output Voltage, Q A ? Q H V in = V IH or V IL

|I out| ≤ 20 m A

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

V in = V IH or V IL|I out| ≤ 2.4 mA

|I out| ≤ 6.0 mA

|I out| ≤ 7.8 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.4

0.4

0.4

V OH Minimum High?Level Output Voltage, SQ H V in = V IH or V IL

II out I ≤ 20 m A

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

V in = V IH or V IL|I out| ≤ 2.4 mA

II out I≤ 4.0 mA

Ii out I ≤ 5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.2

3.7

5.2

V OL Maximum Low?Level Output Voltage, SQ H V in = V IH or V IL

II out I ≤ 20 m A

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

V in = V IH or V IL|I out| ≤ 2.4 mA

II out I≤ 4.0 mA

Ii out I ≤ 5.2 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.4

0.4

0.4

I in Maximum Input Leakage

Current

V in = V CC or GND 6.0±0.1±1.0±1.0m A

I OZ Maximum Three?State

Leakage

Current, Q A? Q H Output in High?Impedance State

V in = V IL or V IH

V out = V CC or GND

6.0±0.5±5.0±10m A

I CC Maximum Quiescent Supply

Current (per Package)V in = V CC or GND

l out = 0 m A

6.0 4.040160m A

AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6.0 ns)

Symbol Parameter V CC

V

Guaranteed Limit

Unit –55 to 25_C≤ 85_C≤ 125_C

f max Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 7)2.0

3.0

4.5

6.0

6.0

15

30

35

4.8

10

24

28

4.0

8.0

20

24

MHz

t PLH, t PHL Maximum Propagation Delay, Shift Clock to SQ H

(Figures 1 and 7)

2.0

3.0

4.5

6.0

140

100

28

24

175

125

35

30

210

150

42

36

ns

t PHL Maximum Propagation Delay, Reset to SQ H (Figures 2 and 7)2.0

3.0

4.5

6.0

145

100

29

25

180

125

36

31

220

150

44

38

ns

t PLH, t PHL Maximum Propagation Delay, Latch Clock to Q A? Q H

(Figures 3 and 7)

2.0

3.0

4.5

6.0

140

100

28

24

175

125

35

30

210

150

42

36

ns

t PLZ, t PHZ Maximum Propagation Delay, Output Enable to Q A? Q H

(Figures 4 and 8)

2.0

3.0

4.5

6.0

150

100

30

26

190

125

38

33

225

150

45

38

ns

t PZL, t PZH Maximum Propagation Delay, Output Enable to Q A? Q H

(Figures 4 and 8)

2.0

3.0

4.5

6.0

135

90

27

23

170

110

34

29

205

130

41

35

ns

t TLH, t THL Maximum Output Transition Time, Q A? Q H

(Figures 3 and 7)

2.0

3.0

4.5

6.0

60

23

12

10

75

27

15

13

90

31

18

15

ns

t TLH, t THL Maximum Output Transition Time, SQ H

(Figures 1 and 7)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

16

110

36

22

19

ns

C in Maximum Input Capacitance?101010pF C out Maximum Three?State Output Capacitance (Output in

High?Impedance State), Q A? Q H

?151515pF

C P

D Power Dissipation Capacitance (Per Package)*Typical @ 25°C, V CC = 5.0 V

pF

300

TIMING REQUIREMENTS (Input t r = t f = 6.0 ns)

Symbol Parameter V CC

V

Guaranteed Limit

Unit 25_C to –55_C≤ 85_C≤ 125_C

t su Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5)2.0

3.0

4.5

6.0

50

40

10

9.0

65

50

13

11

75

60

15

13

ns

t su Minimum Setup Time, Shift Clock to Latch Clock (Figure 6)2.0

3.0

4.5

6.0

75

60

15

13

95

70

19

16

110

80

22

19

ns

t h Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5)2.0

3.0

4.5

6.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

5.0

ns

t rec Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2)2.0

3.0

4.5

6.0

50

40

10

9.0

65

50

13

11

75

60

15

13

ns

t w Minimum Pulse Width, Reset

(Figure 2)2.0

3.0

4.5

6.0

60

45

12

10

75

60

15

13

90

70

18

15

ns

t w Minimum Pulse Width, Shift Clock (Figure 1)2.0

3.0

4.5

6.0

50

40

10

9.0

65

50

13

11

75

60

15

13

ns

t w Minimum Pulse Width, Latch Clock (Figure 6)2.0

3.0

4.5

6.0

50

40

10

9.0

65

50

13

11

75

60

15

13

ns

t r, t f Maximum Input Rise and Fall Times (Figure 1)2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

ns

FUNCTION TABLE

Operation

Inputs Resulting Function

Reset

Serial

Input

A

Shift

Clock

Latch

Clock

Output

Enable

Shift

Register

Contents

Latch

Register

Contents

Serial

Output

SQ H

Parallel

Outputs

Q A ? Q H

Reset shift register L X X L, H, ↓L L U L U

Shift data into shift register H D↑L, H, ↓L D→SR A;

SR N→SR N+1

U SR G→SR H U

Shift register remains

unchanged

H X L, H, ↓L, H, ↓L U U U U

Transfer shift register

contents to latch

register

H X L, H, ↓↑L U SR N→LR N U SR N

Latch register remains

unchanged

X X X L, H, ↓L*U*U Enable parallel outputs X X X X L****Enabled Force outputs into high

impedance state

X X X X H****Z

SR = shift register contents D = data (L, H) logic level↑ = Low?to?High* = depends on Reset and Shift Clock inputs LR = latch register contents U = remains unchanged↓ = High?to?Low** = depends on Latch Clock input

PIN DESCRIPTIONS

INPUTS

A (Pin 14)

Serial Data Input. The data on this pin is shifted into the 8?bit serial shift register.

CONTROL INPUTS

Shift Clock (Pin 11)

Shift Register Clock Input. A low? to?high transition on this input causes the data at the Serial Input pin to be shifted into the 8?bit shift register.

Reset (Pin 10)

Active?low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8?bit latch is not affected.

Latch Clock (Pin 12)

Storage Latch Clock Input. A low?to?high transition on this input latches the shift register data.Output Enable (Pin 13)

Active?low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (Q A?Q H) into the high?impedance state. The serial output is not affected by this control unit.

OUTPUTS

Q A? Q H (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Noninverted, 3?state, latch outputs.

SQ H (Pin 9)

Noninverted, Serial Data Output. This is the output of the eighth stage of the 8?bit shift register. This output does not have three?state capability.

SWITCHING WAVEFORMS

SERIAL INPUT A

SWITCH CLOCK

V CC

GND

Figure 5.SHIFT CLOCK

OUTPUT

SQ H

CC

RESET

OUTPUT

SQ H SHIFT CLOCK CC CC V CC

GND

LATCH CLOCK

Q A -Q H OUTPUTS V CC GND

V CC

GND SHIFT CLOCK

LATCH CLOCK

Figure 3.

V CC GND

Figure 1.

Figure 2.

Figure 4.

Figure 6.

OUTPUT Q

OUTPUT Q

V CC GND

HIGH

IMPEDANCE V OL V OH

HIGH

IMPEDANCE

OUTPUT ENABLE

TEST CIRCUITS

*Includes all probe and jig capacitance C L *

TEST POINT *Includes all probe and jig capacitance

TEST POINT CONNECT TO V CC WHEN TESTING t PLZ AND t PZL .CONNECT TO GND WHEN TESTING t PHZ AND t PZH .

Figure 7.Figure 8.

EXPANDED LOGIC DIAGRAM OUTPUT

ENABLE

LATCH

CLOCK

SERIAL

DATA INPUT A SHIFT

CLOCK RESET Q A

Q B

Q C

Q D

Q E

Q F

Q G

Q H

SERIAL

DATA OUTPUT SQ H

PARALLEL

DATA

OUTPUTS

TIMING DIAGRAM

SHIFT CLOCK SERIAL DATA

INPUT A

RESET LATCH CLOCK OUTPUT ENABLE

Q A Q B Q C Q D Q E Q F Q G Q H

SERIAL DATA OUTPUT SQ H

NOTE:

implies that the output is in a high?impedance

state.

ORDERING INFORMATION

Device

Package

Shipping ?MC74HC595ADG SOIC?16(Pb?Free)48 Units / Rail NLV74HC595ADG*48 Units / Rail MC74HC595ADR2G 2500 / Tape & Reel NLV74HC595ADR2G*2500 / Tape & Reel MC74HC595ADTG TSSOP?16(Pb?Free)96 Units / Tube NLV74HC595ADTG*96 Units / Tube MC74HC595ADTR2G 2500 / Tape & Reel NLV74HC595ADTR2G*2500 / Tape & Reel MC74HC595AMNTWG#QFN16(Pb?Free)3000 / Tape & Reel NLV74HC595AMNTWG*#3000 / Tape & Reel NLV74HC595AMN1TWG*#

3000 / Tape & Reel

?For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC?Q100 Qualified and PPAP Capable.

#MN suffix is with pull?back lead, MN1 is without pull?back lead. Refer to ’Detail A’ of case outline on page 13.

TSSOP?16CASE 948F ISSUE B

DIM MIN MAX MIN MAX INCHES

MILLIMETERS A 4.90 5.100.1930.200B 4.30 4.500.169

0.177C ??? 1.20???0.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.180.280.0070.011J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSC M

0 8 0 8 NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .

7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE ?W?.

__

__

16X REF K

16X

0.36

0.65PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb?Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOIC?16CASE 751B?05

NOTES:

1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 198

2.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

S

B

M

0.25 (0.010)A

S

T DIM MIN MAX MIN MAX INCHES

MILLIMETERS A 9.8010.000.386

0.393B 3.80 4.000.1500.157C 1.35 1.750.0540.068D 0.350.490.0140.019F 0.40 1.250.0160.049G 1.27 BSC 0.050 BSC J 0.190.250.0080.009K 0.100.250.0040.009M 0 7 0 7 P 5.80 6.200.2290.244R

0.250.50

0.0100.019

____16X

0.58

SOLDERING FOOTPRINT*

*For additional information on our Pb?Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

QFN16, 2.5x3.5, 0.5P

CASE 485AW ISSUE O

16X

Mounting Techniques Reference Manual, SOLDERRM/D.

BOTTOM VIEW

PITCH

PUBLICATION ORDERING INFORMATION

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

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E12 SERIES SPECIFICATION 1/5

E12 SERIES SPECIFICATION 2/5

E12 SERIES SPECIFICATION

项目ITEM 7-1.Rotational life 回转寿命 在无负荷条件下轴以600~1000周/小时速度回转30000周。7-2.Damp heat 耐湿性 7-3、Dry heat 耐热性 7-4. Cold 低温特性 7-5. Solder ability 焊锡性 7-6.Resistance to Soldering heat 耐焊接热 Soldering:Solder temperature:260±5℃ or less Immersion time:within 3S 焊接:温度260±5℃或以下,时间3秒以内. 2.Preheating time:within 1 min.接触无异常. 预热:基板表面温度100℃以下,时间1分钟以内.使用基板:t=1.6mm的单面覆铜板. mechanical abnormality.Preheating:1.Surface temperature of board:100℃ or less.不得有绝缘体的破损、变形、Printed wiring board:single-sided copper clad laminate Electrical characteristics board with thickness of 1.6mm.shall be satisfied No 温度300℃以下,时间3秒以内.Dip soldering.槽焊 Manual soldering 手工焊接 Bit temperature of soldering iron:300℃ less than Application time of soldering iron:within 3s 端子在260℃±5℃温度的焊锡槽内浸锡3秒±0.5秒.surface being immersed. 浸渍面须有75%以上焊锡附着 The terminals shall be immersed into solder bath at 260℃ A new uniform coating of solder for 3s±0.5s in the same manner as para.shall cover 75% minimum of the 温度-25±3℃的恒温箱中放置96±4小时,常温、常湿放置1.5小时后测试. shall be subjected to standard atmospheric conditions for 所有项应满足初期规格 1.5H.After which measurements shall be made. The encoder shall be stored at a temperature of -25±3℃ Specifications in clause all for 96±4H in a thermostatic chamber.And then the encoder items is shall be satisfied.温度80±3℃的恒温箱中放置96±4小时,常温、常湿放置1.5小时后测试. shall be subjected to standard atmospheric conditions for 所有项应满足初期规格 1.5H,After which measurements shall be made. E12 SERIES SPECIFICATION E E121212系列规格书 系列规格书 4/5 7 7 耐久性能 耐久性能 耐久性能 ENDURANCE CHARACTERISTICS ENDURANCE CHARACTERISTICS 条件规格CONDITIONS SPECIFICATIONS The shaft of encoder shall be rotated to 30000 cycles at a ≤5mS Bounce t2≤3mS 突跳 t2≤Chattiring t1,t3≤5mS 振荡t1,t3speed of 600~1000 cycles/H without electrical load,after 3mSDetent feeling has to with measurements shall be made. remains 尚余有轻微定位感Specifications in clause all relative humidity of 90% to95% for96±4H in a thermostatic items is shall be satisfied.Contact resistance 200Ω Max 端子间接触阻抗200Ω以下The encoder shall be stored at temperature of 40±2℃ with shall be made.温度40±2℃,湿度90~95%的恒温恒湿槽中放置96±4小时后,在常温、常湿中放置1.5小时后测试. The encoder shall be stored at a temperature of 80±3℃ Specifications in clause all for 96±4H in a thermostatic chamber.And then the encoder items is shall be satisfied.chamber.And the encoder shall be subjected to standard at- 所有项应满足初期规格 mospheric conditions for 1.5H,After which measurements

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SRLT系列产品规格书

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NON-POLARIZED, WIDE TEMPERATURE 無極性寬溫品 Non-polarized with wide temperature range -55°C~+105°C 無極性和適用於 -55°C~+105°C的寬溫範圍 Load life of 1000 hours 負荷壽命1000小時 Comply with the RoHS directive 符合RoHS指令 SPECIFICATIONS 特性表 Items 項目Characteristics 主要特性 Operation Temperature Range 使用温度範圍-55 ~ +105°C Voltage Range 額定工作電壓範圍 6.3 ~ 50V Capacitance Range 靜電容量範圍0.1 ~ 47μF Capacitance Tolerance 靜電容量允許偏差±20% at 120Hz, 20°C Leakage Current 漏電流 Leakage current ≤0.05CV or 10μA, whichever is greater (after 2 minutes application of rated voltage) 漏電流≤0.05CV或10μA,取較大值(施加額定工作電壓2分鐘後) Dissipation Factor (tan δ) 損耗角正切 Measurement frequency 測試頻率: 120Hz, Temperature 温度 : 20°C Rated Voltage (V) 額定工作電壓 6.3 10 16, 25 35, 50 tan δ (max.) 最大損耗角正切0.24 0.20 0.17 0.15 Stability at Low Temperature 低溫特性 Measurement frequency 測試頻率 : 120Hz Rated Voltage (V) 額定工作電壓 6.3 10 16, 25 35, 50 Impedance Ratio 阻抗比 ZT/Z20 (max.) Z(-25°C) / Z(20°C) 4 3 2 2 Z(-55°C) / Z(20°C)8 6 4 3 Load Life 高溫負荷特性 After 1000 hours application of the rated voltage at 105°C (the polarity needs to exchange every 250 hours), they meet the characteristics listed below. 在105°C環境中施加額定工作電壓1000小時(每250小時必須轉換一次極性)後,電容器的特性符合下表的要求。 Capacitance Change 靜電容量變化率 Within ±20% of initial value 初始值的±20%以內 Dissipation Factor 損耗角正切200% or less of initial specified value 不大於規範值的200% Leakage Current 漏電流initial specified value or less 不大於規範值 Shelf Life 高溫貯存特性 After leaving capacitors under no load at 105°C for 1000 hours, they meet the specified value for load life characteristics listed above. 在105°C環境中無負荷放置1000小時後,電容器的特性符合高溫負荷特性中所列的規定值。 Resistance to Soldering Heat 耐焊接熱特性 After reflow soldering and restored at room temperature, they meet the characteristics listed below. 經過回流焊並冷卻至室溫後,電容器的特性符合下表的要求。 Capacitance Change 靜電容量變化率Within ±10% of initial value 初始值的±10%以内 Dissipation Factor 損耗角正切initial specified value or less 不大於規範值 Leakage Current 漏電流initial specified value or less 不大於規範值 Marking 標識Black print on the case top. 鋁殼頂部黑字印刷。 DRAWING (Unit: mm) 外形圖 DIMENSIONS (Unit: mm) 尺寸表 ?D x L 4 x 5.4 5 x 5.4 6.3 x 5.4 A 2.0 2.2 2.6 B 4.3 5.3 6.6 C 4.3 5.3 6.6 E ± 0.2 1.0 1.4 1.9 L 5.4 5.4 5.4 *1. Voltage mark for 6.3V is [6V] 6.3V的產品標識為 [6V] SeriesSMD aluminum electrolytic capacitor

压敏电阻07D系列型号参数规格书_图文(精)

Specifications 规格说明:□Varistor Voltage Range 压敏电阻动作电压范围 18V~1800V(dc□Peak Current For 8/20us Current Wave 在8/20us 电流波形最大通流量 100A~1800A □Energy Range For 10/1000us Current Wave 在10/1000us 电流波形的能量范围0.4J~1092J □Storage Temperature Range 储存温度范围 -40℃~125℃□Operat ion Ambient Temperature Range 作业环境温度范围储存温度范围-40℃~85℃□Typical Response Time 反应时间 〈25ns □Insulation Resistance 绝缘电阻 ≧1000MΩ D K 05,07.10142025 Chip Diameter 芯片直径Φ5mm Φ7mm Φ10mm Φ14mm Φ20mm Φ25mm

Chip .Shape 芯片形状Varistor Voltage 压敏电阻动作电压例如Examples:47×100=47V 47×101=470V 11×102=1100V 4704 7 1 1 1 2

Tolerance 误差K .±10%L .±15%M .±20%Or Customer Special Requirem ent 圆形 Disc HighSurge/Lead Style 高焦/脚型 □空白常规□J 高能品□S 直脚□O 外弯脚□I 内弯脚□H 高低脚Part Number Code 7 471

GRM系列规格书

Chip Monolithic Ceramic Capacitors r Elements (GNM Only) Continued on the following page. o Part Numbering

Continued on the following page. t Temperature Characteristics *1 Please refer to table for Capacitance Change under reference temperature. *2 Capacitance change is specified with 50% rated voltage applied.*3 Murata Temperature Characteristic Code.*4 Apply DC350V bias.*5 No DC bias. *6 Rated Voltage 100Vdc max : 25 to 85°C

EIA Code o Capacitance Change from each temperature JIS Code u Capacitance Expressed by three-digit alphanumerics. The unit is picofarad (pF). The first and second figures are significant digits, and the third figure expresses the number of zeros which follow the two numbers.If there is a decimal point, it is expressed by the capital letter "R ." In this case, all figures are significant digits.Ex.) Continued on the following page.

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