TC1796_info_package_V1[1].0

Product Info Package V1.0
AUDO-NG TC1796
Infineon Technologies AG 02.2005
Never stop thinking.

Fast. Innovative. TriCore. AUDO Next Generation TC1796
+ Extension of the award winning AUDO Architecture + 150 MHz high performance 32-bit TriCore? + 2 MByte embedded Flash + 192 KByte SRAM + Triple Bus Structure + Saving efforts in software and system costs + Speeding up software development with complete toolchain + Ground-breaking peripherals e.g. MSC: save I/O pins = system costs FADC: waive external DSP ASICs GPTA: realize scalable eMotor control MLI: build up multi processor systems and eliminate expensive DPRAM
Infineon Technologies AG 02.2005
Never stop thinking.

AUDO Next Generation TC1796 Info Package Overview
Content TC1796 – at first sight Block Diagram Feature Overview misc. 'going into detail..' - Core Concept - Code Size - Key Peripherals - Tool Support
Infineon Technologies AG 02.2005

AUDO Next Generation TC1796 Block Diagram
Infineon Technologies AG 02.2005

AUDO Next Generation TC1796 Feature Overview (1/5)
High Performance 32-Bit CPU - 32-bit architecture with 4 GBytes unified data, program, and input/output address space - Fast automatic context-switch - Multiply-accumulate unit - Single-precision Floating point unit - Saturating integer arithmetic - Two high performance on-chip peripheral buses (FPI Bus) - Register based design with multiple variable register banks - Bit handling - Packed data operations - Zero overhead loop - Precise exceptions - Flexible power management Instruction Set with High Efficiency - 16/32-bit instructions for reduced code size - Data types include: Boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double word integers, and IEEE-754 single precision floating-point - Data formats include: Bit, 8-bit byte, 16-bit half word, 32-bit word, and 64-bit double word data formats - Powerful instruction set - Flexible and efficient addressing mode for high code density
Infineon Technologies AG 02.2005

AUDO Next Generation TC1796 Feature Overview (2/5)
External Bus Interface - Programmable external bus interface for low cost system implementation - Glueless interface to a wide selection of external memories - 8-/16-/32-bit data transfers - Intel-style and Motorola-style peripheral/device support. - Burst flash memory support - Flexible address generation and access timing Integrated On-Chip Memories - Code memory: - 2 MByte on-chip Program Flash (PFLASH) - 48 KByte Scratch-pad RAM (SPRAM) - 16 KByte Instruction Cache (ICACHE) - 16 KByte Boot ROM (BROM) - Data memory - 64 KByte Data Memory (SRAM) - 16 KByte data memory (SBRAM) for standby operation during power-down - 56 KByte Local Data RAM (LDRAM) - 8 KByte Dual-port RAM (DPRAM) - 128 KByte on-chip Data Flash (DFLASH) - PCP memory -32 KByte PCP Code Memory (CMEM), 16 KByte PCP Data Memory (PRAM)
Infineon Technologies AG 02.2005

AUDO Next Generation TC1796 Feature Overview (3/5)
Interrupt System - In total 181 Service Request Nodes (SRNs) - Flexible interrupt prioritizing scheme with 256 interrupt priority levels - Fast interrupt response - Service requests are serviced by CPU or PCP2 Peripheral Control Processor (PCP2) - Data move between any two memory or I/O locations - Data move until predefined limit reached supported - Read-Modify-Write capabilities - Full computation capabilities including basic MUL/DIV - Read/move data and accumulate it to previously read data - Read two data values and perform arithmetic or logically operation and store result - Bit handling capabilities (testing, setting, clearing) - Flow control instructions (conditional/unconditional jumps, breakpoint)
Infineon Technologies AG 02.2005

AUDO Next Generation TC1796 Feature Overview (4/5)
DMA Controller - 16 independent DMA channels - Programmable priority of the DMA sub-blocks on the bus interfaces - Buffer capability for move actions on the buses (min. 1 move per bus is buffered). - Individually programmable operation modes for each DMA channel - Full 32-bit addressing capability of each DMA channel - Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit - Micro Link bus interface support - One register set for each DMA channel - Flexible interrupt generation - DMA Controller operates as bus bridge between System Peripheral Bus and Remote Peripheral Bus Parallel I/O Ports - 127 digital general purpose input/output (GPIO) port lines - Input/output functionality individually programmable for each port line - Programmable input characteristics (pull-up, pull-down, no pull device) - Programmable output driver strength for EMI minimization (weak, medium, strong) - Programmable output characteristics (push-pull, open drain) - Programmable alternate output functions - Output lines of each port can be updated port-wise or set/reset/toggled bit-wise
Infineon Technologies AG 02.2005

AUDO Next Generation TC1796 Feature Overview (5/5)
On-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASC) with baud-rate generator, parity, framing and overrun error detection - Two Synchronous Serial Channels (SSC) with programmable data length and shift direction - Two Micro Second Channel Interfaces (MSC) for serial communication - One CAN Module with four CAN nodes (MultiCAN) for high efficiency data handling via FIFO buffering and gateway data transfer - Two Micro Link Serial Bus Interfaces (MLI) for serial multiprocessor communication - Two General Purpose Timer Arrays (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management - One Local Timer Cell Array (LTCA) for signal generation purposes - Two medium speed Analog-to-Digital Converter Units (ADC) with 8-bit, 10-bit, or 12-bit resolution and sixteen analog input each - One fast Analog-to-Digital Converter Unit (FADC) Package - P-BGA-416 package, 1 mm pitch Clock Frequencies - Maximum CPU Clock Frequency: 150 MHz - Maximum System Clock Frequency: 75 MHz
Infineon Technologies AG 02.2005
Temperature Rnage - Ambient temperature: -40 ° to +125 °C

AUDO Next Generation TC1796 Starter Kit Details
Infineon TC1796 Starter Kit includes: – TC1796 TriBoard – StarterKit CD with all device and board information as PDF as well Getting Started Software and a Hands-On-Training for self-study – DAvE (e.g. for generating peripheral initialization code) – Demo CD of third party compiler and debugger vendors – GNU C-Compiler full version – Parallel cable for direct connection to the PCs LPT interface – Extension Board for easy measurement of HW signals with a scope or a logic-analyzer Order Information: https://www.wendangku.net/doc/be3180719.html,/mc-starterkits – Order Number: B158-H8537-X-0-7600, SK-TC1796 Starter Kit
Infineon Technologies AG 02.2005 TC1796 Starter Kit

going into detail..
TC1796 – Core Concept
Infineon Technologies AG 02.2005
Never stop thinking.

AUDO-NG – Outperforming Core Concept TriCore Architecture – Key Features and Benefits (1/2)
Program Memory Program Memory Unit 64 LMB Bus - split in PLMB and DLMB 64
Combining the the best of three worlds: RISC (MCU), DSP and μ-Controller together in a single core - TriCore offers maximum system performance for embedded real-time applications Key Features
High Performance 32-bit TriCore CPU (TC v1.3) with 4-stage pipeline and triple issue super-scalar implementation (fCPU = 150 MHz) * Register sets
– – 2x16 address/data 32 bits registers Switch upper shadowed half context in 2/4 cycles (the lower half in 4 cycles)
Key Benefits
Optimized chip-size to performance ratio for real-time critical embedded systems.
16 Address 32 bits Registers
16 Data 32 bits Registers
64
64
Data Memory Unit Data Memory
64
Local Memory Bus (LMB)
– – 64 bits data separated busses used for program and data (PLMB and DLMB)
Separated instruction and data busses speed up the system performance due avoided arbitration conflict on a common bus compressed Code-Density optimized for embedded FLASH memory usage
Infineon Technologies AG 02.2005
mixed 16/32 bit instruction format
* referring to TC1796

The Infineon 32-bit
Microcontroller Features/Highlights ? ? ? ? ? ? fast interrupt response fast context switch (2-4 cycle -> ? context) 16-bit and 32-bit instruction formats bit manipulation unit accumulated logical/ compare integrated peripheral support RISC Processor Feature/Highlights ? ? ? ? ? ? DSP Features/Highlights ? sustainable single-cycle dual-MAC ? ? ? ? ? DSP addressing modes zero overhead loop saturation and Q-Math overflow detection rounding 32-bit load/store Harvard architecture 16 address & 16 data registers super-scalar execution (4 stage pipeline) single data-memory model memory protection C/C++ and RTOS support
Infineon Technologies AG 02.2005

AUDO-NG – Outperforming Core Concept TriCore Architecture – Key Features and Benefits (1/2)
Program Memory Program Memory Unit 64 LMB Bus - split in PLMB and DLMB 64
Combining the the best of three worlds: RISC (MCU), DSP and μ-Controller together in a single core - TriCore offers maximum system performance for embedded real-time applications Key Features
High Performance 32-bit TriCore CPU (TC v1.3) with 4-stage pipeline and triple issue super-scalar implementation (fCPU = 150 MHz) Register sets
– – 2x16 address/data 32 bits registers Switch upper shadowed half context in 2/4 cycles (the lower half in 4 cycles)
Key Benefits
Optimized chip-size to performance ratio for real-time critical embedded systems.
16 Address 32 bits Registers
16 Data 32 bits Registers
64
64
Data Memory Unit Data Memory
64
Local Memory Bus (LMB)
– – 64 bits data separated busses used for program and data (PLMB and DLMB)
Separated instruction and data busses speed up the system performance due avoided arbitration conflict on a common bus compressed Code-Density optimized for embedded FLASH memory usage
Infineon Technologies AG 02.2005
mixed 16/32 bit instruction format

AUDO-NG – Outperforming Core Concept TriCore Architecture – Key Features and Benefits (2/2)
Key Features
Program Memory Program Memory Unit 64 LMB Bus - split in PLMB and DLMB 64
Key Benefits
sophisticated interrupt system with up to 255 HW arbitrated sources and very fast response times is optimized for realtime sensitive embedded applications
Interrupt System
– Flexible multi-master interrupt system (interrupts serviced by CPU, PCP or DMA) Hardware controlled context switch Hardware Interrupt Priority arbitration with 255 priority levels very fast interrupt response time resp. < 180 ns @ 150 MHz)
16 Address 32 bits Registers
16 Data 32 bits Registers
– – –
64
64
Data Memory Unit Data Memory
64
powerful MAC unit supports circular buffer, No data overflow faults due to saturating arithmetic and bit-reverse addressing modes for DSP algorithms
given scalability approach due to MCU and DSP function merged in one core. Only one tool set for development and emulation
single precision Floating Point Unit (FPU) with integrated interrupt capability for exception handling
Infineon Technologies AG 02.2005
tightly coupled coprocessor FPU support with single precision IEEE-754 data format compromises acceptable physical precision demands with increased real time behaviour (unaltered fast 2 cycle context switch) and reduced storage memory for FPU variables

TriCore Architecture – Super-scalar Execution
Triple / Dual / Single Issue
Triple Issue Dual Issue Dual Issue Dual Issue Single Issue Single Issue Single Issue Arithmetic Load / Store Loop Arithmetic Arithmetic Arithmetic Load / Store Load / Store Load / Store Loop Loop
~1.3 instr/cycle
Loop
Infineon Technologies AG 02.2005

TriCore Architecture – Powerful Interrupt Service System
Features
Up to 4 x 255 request nodes (SRN), concurrently supported Parallel Arbiter HW to select highest interrupt & clear when accepted Automatic context save during branch to interrupt routine Interrupt table - no jumps needed 7 6 5 4 3 2 1 0
TC1796 @ 150 Mhz ? ≥ 200 ns interrupt response time until execution of first instruction within Interrupt Service Routine (depending Interrupt Code Location and priority selection)
Int. Ack. Infineon Technologies AG 02.2005 Int. Req. Interrupt Control Unit (ICU) Peripheral SRN SRC Peripheral SRN SRC Peripheral SRN SRC Peripheral SRN SRC Peripheral SRN SRC Peripheral SRN SRC
Benefits
Meets real-time requirements Zero Software overhead Ease of programming, High flexibility Large Number of SRNs Flexible grouping of request into priority groups
Arbitration Bus FPI Bus

TriCore Architecture – DSP Some Results
MUL MADD MSUB 32 +/- 16x16 48 +/- 16x16
16 32 32/64
MUL MADD MSUB 32 +/- 16x32 64 +/- 16x32
16 16 32/48
MUL MADD MSUB 32 +/- 32x32 64 +/- 32x32
32 32 32/64
MUL MADD MSUB 32 +/- 16x16 || 32 +/- 16x16
16 16 32 16 16 32
mul
mul
mul
mul add/sub 32/64 add/sub 32
mul add/sub 32
add/sub 32/64
add/sub 32/48
Choice of register half Left-alignment 8000*8000 -> 7FFF FFFF Rounding Sat
choice of register half Left-alignment Sat
Left-alignment Sat
choice in register half left-alignment 8000*8000 -> 7FFF FFFF add/sub or sub/add Rounding Sat Packing 2 32bit into 1 32bit thru-put = 1 cycle
thru-put = 1 cycle Infineon Technologies AG 02.2005
thru-put = 1 cycle
thru-put = 2 cycles

TriCore Architecture – Reducing Cost and Complexity by merging MCU and DSP
Program Memory Program Memory Unit 64 LMB Bus - split in PLMB and DLMB 64
Control and DSP development and integration/debug can all be done with the same development tools Optimized DSP library algorithms can be used out of the box Easy adaptation of DSP functions integrated in Automatic Code Generation tool package Devices can quickly be adapted to new market requirements smaller silicon
RTOS + DSP + App TriCore Memory I/O
16 Address 32 bits Registers
16 Data 32 bits Registers
64
64
Data Memory Unit Data Memory
64
TriCore?
Infineon Technologies AG 02.2005
one CPU one Tool one RTOS
Fast Time to Market New Features Lower Cost

TriCore Architecture – Supported DSP Operations
Two MACs per cycle:
Matrix calculus ld k0,k1 ld x0,x1,x2,x3
Sensors signal processing:
FIR, IIR, DFT, FFT,
setup
+
+
+
1 cycle
a1
+
a2 z-1 z-1
a3 z-1
a4
mac x0 k0 mac x1 k1 loop ld k2,k3,k4,k5 ld x4,x5,x6,x7 mac x2,k2 mac x3,k3 1 cycle
z-1
b0
b1
+
b2
+
b3
+
b4
+
Infineon Technologies AG 02.2005
Dual 16x16 hardware MAC Packed data Parallel load Mac-load-(loop) per cycle
Zero overhead loop Bit reverse addressing