TMC22152A中文资料
and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. Preliminary Information
https://www.wendangku.net/doc/b210884112.html,
TMC22x5yA
PRODUCT SPECIFICATION
2
P r e l i m i n a r y I n f o r m a t i o n
Table of Contents
Features......................................................................1Applications ...............................................................1Description.................................................................1Block Diagram............................................................1Contents .....................................................................2List of Tables and Figures ........................................3General Description (4)
Input Processor...............................................................4Adaptive Comb Filter.....................................................4Output Processor............................................................5Parallel and Serial Microprocessor Interfaces................5Pin Assignments........................................................5Pin Descriptions.........................................................6Control Register Map.................................................8Control Register Definitions...................................11Decoder Introduction.. (40)
YC Separation..............................................................40Comb Filter Architecture for YC Separation...............41YC Line-Based Comb Filters.......................................42D1 Line-Based Comb Filters.......................................42NTSC Frame and Field Based Decoders (42)
Composite Frame-Based Comb Filters........................42Composite Field-Based Comb Filters..........................42PAL Field Comb Decoders.. (42)
Composite PAL Field Comb Filters.............................42The TMC22x5yA Comb Filter Architecture............43TMC22x5yA Functional Description.. (44)
Input Processor.............................................................44Bandsplit Filter (BSF)..................................................44Comb Filter Input.........................................................45Adaptive Comb Filter...................................................47Comb Fails. (49)
Comb Fail Detection....................................................49Generation of the Comb Fail Signals (50)
Luma Error Signals......................................................50Hue and Saturation Error Signals.................................50Picture Correlation.......................................................50Adapting the Comb Filter ............................................50XLUT...........................................................................51Digital Burst Locked Loop ..........................................53Color Kill Counter .......................................................53PAL Color Frame Bit...................................................55Hue Control..................................................................55System Monitoring of the Burst Loop Error. (55)
Clamp Circuit..............................................................55Pedestal Removal........................................................55Clamp Generator.........................................................55Luma Notch Filter.......................................................56Matrix..........................................................................56Programmable U Scalar...............................................56Programmable V Scalar...............................................56Programmable Y Scalar...............................................56Programmable MS Scalar............................................56Fixed (B-Y) and (R-Y) Scalars ...................................56Y Offset.......................................................................57Matrix Limiters............................................................57Examples of Output Matrix Operation........................57Simple Luma Color Correction...................................58C B C R MSB Inversion.................................................58Output Rounding.........................................................58Output Formats............................................................58Decimating C B C R Data...............................................58Multiplexed YC B C R Output (TRS Words Inserted)...58YC Outputs..................................................................58The LDV Clock...........................................................58Sync Pulse Generator (59)
Internal Field and Line Numbering Scheme...............59Timing Parameters .. (61)
Subcarrier Programming.............................................61Horizontal Timing.......................................................61Horizontal and Vertical Timing Parameters................61Vertical Blanking........................................................62VINDO Operation.......................................................65Video Measurement. (65)
Pixel Grab....................................................................65Composite Line Grab..................................................67Parallel Microprocessor Interface ...............................67Serial Control Port (R-Bus).........................................68Equivalent Circuits and Threshold Levels............71Absolute Maximum Ratings....................................72Operating Conditions..............................................73Electrical Characteristics........................................75Switching Characteristics.......................................76System Performance Characteristics....................76Programming Examples..........................................77Programming Worksheet........................................81Related Products.....................................................82Ordering Information.. (84)
PRODUCT SPECIFICATION TMC22x5yA
3 Preliminary Information
List of Tables and Figures
Table 1.TMC22x5yA Decoder Family (4)
Table 2.Normalized Subcarrier Frequency
as a Function of Pixel Data Rates (45)
Table https://www.wendangku.net/doc/b210884112.html,b Filter Architecture (48)
Table 4.Simple Example of an Adaptive
Comb Filter Architecture (48)
Table 5.Adaption Modes (51)
Table 6.XLUT Input Selection (52)
Table 7.XLUT Output Function (52)
Table 8.XLUT Special Function Definitions (52)
Table 9.PAL-B,G,H,I Bruch
Blanking Sequence (53)
Table 10.PAL-M Bruch Blanking Sequence (54)
Table 11. Blanking Level Selection (55)
Table 12.Adaptive Notch Threshold Control (55)
Table 13.Matrix Limiters (57)
Table 14.Output Format (58)
Table 15.NTSC Field and Line Numbering (59)
Table 16.PAL B,G,H,I Field and
Line Numbering (59)
Table 17.PAL M Field and Line Numbering (59)
Table 18.Vertical Blanking Period (60)
Table 19.Vertical Burst Blanking Period (60)
Table 20.Table of Line Idents, LID[4:0] (60)
Table 21.Timing Offsets (61)
Table 22.PAL VINDO operation (63)
Table 23.Pixel Grab Control (66)
Table 24.Parallel Port Control (67)
Table 25.Serial Port Addresses (69)
Figure 1.Logic Symbol (4)
Figure 2.Pixel Data Format (4)
Figure 3.Fundamental Decoder
Block Diagram (40)
Figure https://www.wendangku.net/doc/b210884112.html,parison of the Frequency
Spectrum of NTSC and PAL
Composite Video Signals (40)
Figure 5.Examples of Notch and Bandpass
Filters (41)
Figure 6 (41)
Figure 7.Chrominance Vector Rotation in
PAL and NTSC (42)
Figure 8.Chrominance Vector Rotation Over
4 Fields in NTSC (42)
Figure 9.Chrominance Vector Rotation Over
4 Fields in PAL (42)
Figure 10.TMC22x5yA Line Based Comb
Filter Architecture................................43Figure 11.Input Processor (44)
Figure https://www.wendangku.net/doc/b210884112.html,plementary Bandsplit Filter (44)
Figure 13.Bandsplit Filter, Full Frequency
Response (45)
Figure 14.Bandsplit Filter, Passband
Response (45)
Figure 15.Block Diagram of Comb Filter Input (46)
Figure 16.Signal Flow Around the Adaptive
Comb Filter (47)
Figure 17.Example of a Comb Fail Using a NTSC Two Line Comb Filter (49)
Figure 18.Generation of Upper and Lower Comb
Fail Signals (50)
Figure https://www.wendangku.net/doc/b210884112.html,b Filter Selection (51)
Figure 20.XLUT Input Selection (52)
Figure 21.Block Diagram of Digital Burst
Locked Loop (53)
Figure 22.Gaussian Low Pass Filters (54)
Figure 23.Gaussian LPF Passband Detail (54)
Figure 24.Output Processor Block Diagram (55)
Figure 25.Adaptive Notch Filters (56)
Figure 26.Luminance Notch Filter (56)
Figure 27.Horizontal Timing (61)
Figure 28.External HSYNC and VSYNC Timing
for Field 1(3, 5, or 7) (62)
Figure 29.NTSC Vertical Interval (62)
Figure 30.PAL-B,G,H,I,N Vertical Interval (62)
Figure 31.PAL-M Vertical Interval (63)
Figure 32.Pixel Grab Locations (64)
Figure 33.Relationship Between Pixel Count
and Pixel Grab Value (65)
Figure 34.Microprocessor Parallel Port –
Write Timing (66)
Figure 35.Microprocessor Parallel Port –
Read Timing (68)
Figure 36.Serial Port Read/Write Timing (69)
Figure 37.Serial Interface –
Typical Byte Transfer (70)
Figure 38.Equivalent Digital Input Circuit (71)
Figure 39.Equivalent Digital Output (71)
Figure 40.Threshold Levels for Three-state (71)
Figure 41.Input Timing Parameters (72)
Figure 42.Functional Block Diagram of the
TMC22x5yA G/Y, B/U, and R/V Output
Stage (73)
Figure 43.Output Timing Parameters (74)
TMC22x5yA
PRODUCT SPECIFICATION
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P r e l i m i n a r y I n f o r m a t i o n
PRODUCT SPECIFICATION TMC22x5yA
5 Preliminary Information
TMC22x5yA
PRODUCT SPECIFICATION
6
P r e l i m i n a r y I n f o r m a t i o n
Pin Descriptions
Pin Name Pin Number
Value
Pin Function Description
Inputs VIDEOA 9-0
86, 85, 84, 83, 82, 81, 80, 79,
78, 77TTL
Video input A. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA 9-2).VIDEOB 9-075, 74, 73, 72, 71, 70, 69, 68,
67, 66
TTL
Video input B. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB 9-2).VSYNC 49
TTL
Vertical sync input. A vertical sync signal (active low) occurring at the start of the first vertical sync pulse in a vertical field group. A falling edge of VSYNC which is coincident with a falling edge of HSYNC indicates field 1. This signal is active only when SPGIP 1-0 = 00.
HSYNC 48TTL
Horizontal sync input. A horizontal sync signal (active low) occurring at the falling edge of the video sync. This signal is active only when SPGIP 1-0 = 00.
MASTER 1-088, 87TTL
Master decoder control. 00Adaptive comb decoder 01Simple bandsplit decoder 10Reserved
11
Flat notched luma and simple bandsplit chroma
BUFFER
50
TTL
Control register select. This signal switches between two sets of registers which control the gain or hue values in the output matrix. When BUFFER = 0, registers 17-1F are active. When BUFFER = 1, registers 27-2F take control.
CLOCK 89TTL
Master processing clock. The clock signal can either be at twice the pixel data rate in the line locked modes, or at four times the subcarrier frequency in the subcarrier mode. The interpretation of the CLOCK signal is set by the CKSEL register bit.
SET 52TTL
Programmable function pin. The function specified by the SET
register is active when SET is low. The decoder returns to its previous operation when SET goes high.
Outputs G/Y 9-0
93, 94, 95, 96, 97, 98, 99, 100,
1, 2TTL
Green or Luminance digital output. For 8-bit versions (TMC2205yA) the data are left-justified (G/Y 9-2).
B/C B9-06, 7, 8, 9, 10, 11, 12, 13, 14,
15TTL
Blue or C B digital output. For 8-bit versions (TMC2205y) the data are left-justified (B/C B 9-2).
R/C R9-018, 19, 20, 21, 22, 23, 24, 25,
26, 27
TTL
Red or C R digital output. For 8-bit versions (TMC2205yA) the data are left-justified (R/C R 9-2).
DVSYNC 35TTL Vertical sync output. The DVSYNC signal occurs once per field and lasts for 1 video line.
DHSYNC 34TTL Horizontal sync output. The DHSYNC signal occurs once per line and lasts for 64 clock periods.
LDV
3
TTL
Data synchronization output. LDV can be an internally or externally generated clock signal. The internal LDV signal is produced when the CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data rate clock phase locked to the falling edge of the HSYNC. The external LDV can be selected under software control, and must be at the CLOCK, or a sub multiple of the CLOCK, frequency.
PRODUCT SPECIFICATION TMC22x5yA
7 Preliminary Information
DREF30TTL Decoder reference signal. This is a dual function pin, controlled by
register 24, that can function as an active video output indicator or
output as a clamp pulse. When set to the active video output function,
the DREF pin is HIGH during the video portion of each line and LOW
during the horizontal and vertical blanking levels. When set to output a
clamp pulse, the clamp pulse is controlled by register 24 and 25
allowing a user to program when a 0.5 m Sec pulse is output relative to
HSYNC.
FID2-033, 32, 31TTL Field identification output. A 3 bit field ident from the DRS signal.
m P Interface
D7-045, 44, 43, 42,
41, 38, 37, 36TTL Parallel control port data I/O. All control parameters are loaded into and read back over this 8 bit data port.
A1-063, 62TTL Parallel control port address inputs. These pins govern whether the
microprocessor interface selects a table/register address or reads/
writes table/register contents.
CS60TTL Parallel control port chip select. When CS is high the microprocessor
interface port, D7-0, is set to HIGH impedance and ignored. When CS
is LOW, the microprocessor can read or write parameters over D7-0. R/W61TTL Parallel control port read/write control. When R/W and CS are LOW,
the microprocessor can write to the control registers or XLUT over
D7-0. When R/W is HIGH and CS is LOW, it can read the contents of
any selected XLUT address or control register over D7-0.
RESET51TTL Chip master reset. Bringing RESET LOW sets the software reset
control bit, SRESET, LOW and disables the digital outputs. If HRESET
is LOW the decoder outputs remain disabled after RESET goes HIGH
until the SRESET bit is set high by the host. If HRESET is HIGH when
RESET goes HIGH the decoder the internal state machines are
enabled.
SER53TTL Serial/parallel interface select. This pin will select between a parallel
(HIGH) or serial (LOW) interface port.
SDA58R-Bus Serial data interface. Bi-directional serial interface to the control port. SCL59R-Bus Serial interface clock.
SA2-056, 55, 54TTL Serial Address. Three bits providing the lsbs of the serial chip ID used
to identify the decoder.
Power Supply
V DD5, 17, 29, 40,
47, 65, 91
+5 V Power Supply. Positive power supply for digital circuits, +5V.
GND4, 16, 28, 39,
46, 57, 64, 76,
90, 920.0 V Ground. Ground for digital circuits, 0V.
Pin Descriptions (cont.)
Pin Name Pin Number Value Pin Function Description
TMC22x5yA
PRODUCT SPECIFICATION
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P r e l i m i n a r y I n f o r m a t i o n
Control Register Map
The TMC22x5yA is initialized and controlled by a set of registers which determine the operating modes.
An external controller is employed to write and read the Control Registers through either the 8-bit parallel or 2-line serial interface port. The parallel port, D 7-0, is governed by pins CS, R/W, and A 1-0. The serial port is controlled by SDA and SCL.Reg Bit Name
Function
Global Control 00
7SRST Software reset 006HRST Hardware reset 005-3SET SET pin function 002DHVEN Output H&V sync enable 001-0STD
Selects video standard Input Processor Control
017reserved, set to zero 016IPMUX Input mux control 015IP8B 8 bit input format 014TDEN TRS detect enable 013TBLK TRS blank enable 012IPCMSB Chroma input msb invert 011ABMUX AB mux control 010CKSEL Input clock rate select Burst Loop Control
027BLLRST BLL auto. reset enable 026VIPEN Video Input Processor enable
025-4LOCK Global lock mode 023BLM BLL lock mode 022KILD Color kill disable 021DMODBY Demod bypass
020CINT C B C R interpolation enable Chroma Processor Control
037-5BLFS Burst loop filter select 034CCEN Chroma coring enable 033-2CCOR Chroma coring threshold 031GAUBY Gaussian filter bypass 030GAUSEL Gaussian filter select Burst Threshold
04
7-0BTH Burst threshold Pedestal
05
7-0
PED Pedestal level
Luma Processor Control 067-6reserved, set to zero
065ANEN Adaptive notch enable 064ANR Adaptive notch rounding 063-2ANT Adaptive notch threshold 061ANSEL Adaptive notch select 060NOTCH Notch enable Comb Processor Control
077LS1BY Line store 1 bypass 076LS1IN Line store 1 input 075LS2DLY Line store 2 delay 074SPLIT Line store 2 data width 073BSFBY Bandsplit filter bypass 072BSFSEL Bandsplit filter select 071BSFMSB Inverts msb of bandsplit filter
07
GRSDLY
Delays input to GRS decode by 1H Mid-Sync Level
08
7-0
MIDS
Mid-sync level
Extended DRS
097-4PCKF Clock rate 093-0VSTD Video standard
Output Control
0A 7OP8B Output rounded to 8 bits 0A 6-5OPLMT Output limit select 0A 4-3MSEN Mixed sync enable 0A 2OPCMSB Chroma output msb invert 0A 1YBAL Luma color correction 0A 0BUREN Output burst enable 0B 7FMT422Enables C B C R output mux 0B 6CDEC C B C R decimation enable 0B 5YUVT
Enables D1 output 0B 4-2reserved, set to zero 0B 1DRSEN DRS output enable 0B 0DRSCK DRS data rate Comb Filter Control
0C 7-6ADAPT Adaption mode 0C 5YCES YC input error signal control
0C 4YCSEL luma/chroma comb filter select
0C
3-0
COMB Comb filter architecture
Reg Bit Name Function
PRODUCT SPECIFICATION
TMC22x5yA
9
Preliminary Information
0D 7-6CEST Chroma error signal transform
0D 5CESG Chroma error signal gain 0D 4YESG Luma error signal gain 0D 3CESTBY Chroma error signal bypass
0D 2XFEN XLUT filter enable 0D 1FAST Adaption speed select 0D 0YWBY Luma weighting bypass 0E 7-6XIP XLUT input select 0E 5-4XSF XLUT special function 0E 3-2YMUX Y output select 0E 1-0CMUX C output select 0F 7reserved, set to zero 0F 6-5CAT Adaption Threshold 0F 4DCES D1 C B C R error signal 0F 3-2IPCF Comb filter input select 0F 1YCCOMP YC or Composite input select
0F 0SYNC Sync processor select
Sync Pulse Generator
107-0STS 7-0Sync to sync 8 lsbs 117-0STB Sync to burst 127-0BTV Burst to video 137-0AV 7-0Active video line 8 lsbs 147-6reserved, set to zero 145-4AV 9-8Active video line 2 msbs 143reserved, set to zero 142-0STS 10-8Sync to sync 3 msbs 157reserved, set to zero 156-2VINDO Number of lines in vertical window
151VDIV Action inside VINDO 150VDOV Action outside VINDO 167-6reserved, set to zero 165-4NFDLY new field detect delay 163-2SPGIP SPG input select
16
1-0
MSIP
Mixed sync separator input select
Buffered register set 0
Active when BUFFER pin set LOW
177-0SG07-0 Msync gain, 8 lsbs 187-0YG07-0 Y gain, 8 lsbs 19
7-0
UG07-0
U gain, 8 lsbs
Reg Bit Name Function
1A 7-0VG07-0 V gain, 8 lsbs 1B 7-6YG09-8Y gain, 2 msbs 1B 5-3UG010-8U gain, 3 msbs 1B 2reserved, set to zero 1B 1-0VG09-8V gain, 2 msbs 1C 7-0YOFF07-0Y offset, 8 lsbs 1D 7-3reserved, set to zero 1D 2YOFF08Y offset, msb 1D 1-0SG07-0 Msync gain, 2 msbs 1E 7-1SYSPH06-07 lsbs of phase 1E 0VAXISO V axis flip 1F 7-0SYSPH014-78 msbs of phase Normalized Subcarrier Frequency
207-4FSC 3-0Bottom 4 bits of f SC 203-0reserved, set to zero 217-0FSC 11-4Lower 8 bits of f SC 227-0FSC 19-12Middle 8 bits of f SC 237-0FSC 27-20Top 8 bits of f SC Clamp Control
247DRFSEL Clamp pulse enable 246PFLTBY Phase filter enable 245-4CLPSEL 1-0Int. clamp selection 243VCLPEN Clamp bypass 242-0BAND 2-0Clamp offset 257-0CPDLY 7-0
Clamp pulse delay Output Format Control 267-6reserved, set to zero
265LDVIO LDV clock select 264OPCKS Output clock select 263DPCEN DPC enable
26
2-0
DPC
Decoder product code
Buffered register set 1
Active when BUFFER pin set HIGH
277-0SG17-0 Msync gain, 8 lsbs 287-0YG17-0 Y gain, 8 lsbs 297-0UG17-0 U gain, 8 lsbs 2A 7-0VG17-0 V gain, 8 lsbs 2B 7-6YG19-8Y gain, 2 msbs 2B 5-3UG110-8
U gain, 3 msbs 2B 2reserved, set to zero 2B 1-0VG19-8V gain, 2 msbs 2C 7-0YOFF17-0Y offset, 8 lsbs 2D
7-3
reserved, set to zero
Reg Bit Name Function
TMC22x5yA
PRODUCT SPECIFICATION
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P r e l i m i n a r y I n f o r m a t i o n
2D 2YOFF18Y offset, msb 2D 1-0SG17-0 Msync gain, 2 msbs 2E 7-1SYSPH16-07 lsbs of phase 2E 0VAXIS1V axis flip 2F 7-0SYSPH114-7
8 msbs of phase Video Measurement 307 set to zero
306LGF Line grab flag 305LGEN Line grab enable 304LGEXT Ext line grab enable 303reserved, set to zero 302PGG Pixel grab gate 301PGEN Pixel grab enable 300PGEXT Ext pixel grab enable 317-0PG 7-0 Pixel grab, 8 lsbs 327-0LG 7-0 Line grab, 8 lsbs 337reserved, set to zero 336-4FG Field grab number 333LG 8Msb of line grab 332-0PG 10-8Pixel grab, 3 msbs 347-0GY 9-2G/Y grab, 8 msbs 357-0BU 9-2B/U grab, 8 msbs 367-0RV 9-2R/V grab, 8 msbs 377-6reserved 375-4GY 1-0G/Y grab, 2 lsbs 373-2BU 1-0B/U grab, 2 lsbs 371-0RV 1-0R/V grab, 2 lsbs 387-0Y 9-2Luma grab, 8 msbs 397-0M 9-2Msync grab, 8 msbs 3A 7-0U 9-2U grab, 8 msbs 3B 7-0V 9-2V grab, 8 msbs 3C 7-6Y 1-0Luma grab, 2 lsbs 3C 5-4M 1-0Msync grab, 2 lsbs 3C 3-2U 1-0U grab, 2 lsbs 3C 1-0V 1-0V grab, 2 lsbs
Test Control
3D 7-0TEST Must be set to zero 3E 7-0TEST Must be set to zero Vertical Blanking Control
3F 7VBIT20V bit control 3F 6PEDDIS Pedestal control 3F
5-0
CCDEN 5-0
Closed caption control
Auto-increment stops at 3F
Reg Bit Name Function
Notes:
1.Functions are listed in the order of reading and writing.
2.For each register listed above up to register 3F, all bits not
specified are reserved and must be set to zero to ensure proper operation.
Status - Read Only
407-0DDSPH DDS phase, 8 msbs 417LINEST Pixel count reset 416BGST Start of burst gate 415VACT2Half line flag 414PALODD PAL Ident
413VFLY Vertical count reset 412FGRAB Field grab 411LGRAB Line grab 410PGRAB Pixel grab
427FLD Field flag (F in D1 output)426VBLK Vertical blanking (V in D1 output)
425HBLK Horizontal blanking (H in D1 output)424-0LID Line identification 437YGO Y/G overflow 436YGU Y/G underflow 435UBO C B /B overflow 434UBU C B /B underflow 433VRO C R /R overflow 432VRU C R /R underflow 431-0reserved 447MONO Color kill active 446-0FPERR Frequency/Phase error 457-0DRS DRS signal 467-0PARTID Reads back xx h 477-0REVID
Revision number 48-4A 7-0reserved
4B 7PKILL Phase kill from comb fail 4B 6-5CFSTAT Comb filter status 4B 4-0XOP
XLUT output 4C-FF
7-0
reserved
Reg Bit Name Function
PRODUCT SPECIFICATION TMC22x5yA
11 Preliminary Information
TMC22x5yA
PRODUCT SPECIFICATION
12
P r e l i m i n a r y I n f o r m a t i o n
Control Register De?nitions (continued)
Input Processor Control (01)
76543210Reserved IPMUX IP8B
TDEN
TBLK
IPCMSB
ABMUX
CKSEL
Reg Bit Name Description
017Reserved Reserved, set to zero.
01
6
IPMUX
Input mux control. Used to select the Video Input Processor, D1, or D2 data as the VA input to the input processor.
VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set HIGH. For YC inputs, the luma data must be passed through the VA input and chroma through the VB input.
IPMUX should be set LOW for line locked composite inputs.
015IP8B 8 bit input format. Bottom two bits of inputs VIDEOA 9-0 and VIDEOB 9-0 are set to zero when HIGH.
01
4
TDEN
TRS detect enable. When HIGH, the TRS words embedded in incoming video are used to reset the horizontal and vertical state machines. When LOW the externally provided or internally generated HSYNC and VSYNC are used to reset the horizontal and vertical state machines.
013TBLK
TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line locked and D1 data, the TRS and AUX data words are set to the luma and chroma blanking levels as appropriate. For D2 (4*f SC ) data, the TRS and AUX data words are set to the sync tip level.
012IPCMSB Chroma input msb invert. The msb of the chroma or C B C R data are inverted when HIGH.
01
1
ABMUX
AB mux control. Selects the primary and secondary inputs to the decoder from the DA and DB outputs of the input processor. When ABMUX is LOW, DA is selected as the primary and DB as the secondary decoder input.010CKSEL
Input clock rate select. Set HIGH for line locked clocks and LOW for
subcarrier locked clocks. Line locked clocks should be at twice the pixel data rate, and the subcarrier clock should be at four times the subcarrier frequency.
PRODUCT SPECIFICATION TMC22x5yA
13 Preliminary Information
TMC22x5yA
PRODUCT SPECIFICATION
14
P r e l i m i n a r y I n f o r m a t i o n
Control Register De?nitions (continued)
Chroma Processor Control (03)
7
65
43
2
10BLFS
CCEN
CCOR
GAUBY
GAUSEL
PRODUCT SPECIFICATION TMC22x5yA
15 Preliminary Information
TMC22x5yA
PRODUCT SPECIFICATION
16
P r e l i m i n a r y I n f o r m a t i o n
Control Register De?nitions (continued)
Comb Processor Control (07)
76543210LS1BY LS1IN LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
GRSDLY
Reg Bit Name Description
08
7-0
MIDS
Mid sync level. Sets the mid point of syncs for the mixed sync separator, in the subcarrier locked mode.
PRODUCT SPECIFICATION TMC22x5yA
17 Preliminary Information
TMC22x5yA
PRODUCT SPECIFICATION
18
P r e l i m i n a r y I n f o r m a t i o n
Control Register De?nitions (continued)
Notes:
1.To enable “super blacks” and disable syncs of the output simply set MSEN[1] HIGH and the sync gain to zero.
Output Control (0A)
7654
3
210OP8B OPLMT OPLMT
MSEN
OPCMSB
YBAL
BUREN
PRODUCT SPECIFICATION TMC22x5yA
19 Preliminary Information
TMC22x5yA
PRODUCT SPECIFICATION
P r e l i m i n a r y I n f o r m a t i o n
Control Register De?nitions (continued)
Comb Filter Control (0C)
7
6
543
2
1
ADAPT
YCES
YCSEL
COMB