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VHDL程序练习题(含答案)

VHDL程序练习题(含答案)
VHDL程序练习题(含答案)

VHDL程序填空题

(一) 在下面横线上填上合适的VHDL关键词,完成2选1多路选择器的设计。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

1 MUX21 IS

PORT(SEL:IN STD_LOGIC;

A,B:IN STD_LOGIC;

Q: OUT STD_LOGIC );

END MUX21;

2 BHV OF MUX21 IS

BEGIN

Q<=A WHEN SEL=?1? EL SE B;

END BHV;

(二) 在下面横线上填上合适的语句,完成BCD-7段LED显示译码器的设计。LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BCD_7SEG IS

PORT( BCD_LED : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

LEDSEG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END BCD_7SEG;

ARCHITECTURE BEHA VIOR OF BCD_7SEG IS

BEGIN

PROCESS(BCD_LED)

3

IF BCD_LED="0000" THEN LEDSEG<="0111111";

ELSIF BCD_LED="0001" THEN LEDSEG<="0000110";

ELSIF BCD_LED="0010" THEN LEDSEG<= 4 ;

ELSIF BCD_LED="0011" THEN LEDSEG<="1001111";

ELSIF BCD_LED="0100" THEN LEDSEG<="1100110";

ELSIF BCD_LED="0101" THEN LEDSEG<="1101101";

ELSIF BCD_LED="0110" THEN LEDSEG<="1111101";

ELSIF BCD_LED="0111" THEN LEDSEG<="0000111";

ELSIF BCD_LED="1000" THEN LEDSEG<="1111111";

ELSIF BCD_LED="1001" THEN LEDSEG<="1101111";

ELSE LEDSEG<= 5 ;

END IF;

END PROCESS;

END BEHA VIOR;

(三) 在下面横线上填上合适的语句,完成数据选择器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX16 IS

PORT( D0, D1, D2, D3: IN STD_LOGIC_VECTOR(15 DOWNTO 0);

SEL: IN STD_LOGIC_VECTOR( 6 DOWNTO 0);

Y: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));

END;

ARCHITECTURE ONE OF MUX16 IS

BEGIN

WITH 7 SELECT

Y <= D0 WHEN "00",

D1 WHEN "01",

D2 WHEN "10",

D3 WHEN 8 ;

END;

(四) 在下面横线上填上合适的语句,完成JK触发器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY JKFF1 IS

PORT (PSET,CLR,CLK,J,K : IN STD_LOGIC;

Q : OUT STD_LOGIC);

END JKFF1;

ARCHITECTURE MAXPLD OF JKFF1 IS

SIGNAL TEMP:STD_LOGIC;

BEGIN

PROCESS(PSET,CLR,CLK)

BEGIN

IF (PSET='0'AND CLR='1' ) THEN TEMP<='1';

ELSIF (PSET='1'AND CLR='0' ) THEN TEMP<='0';

ELSIF (PSET='0'AND CLR='0' ) THEN NULL;

9 (CLK'EVENT AND CLK='1') THEN

10 (J='0' AND K='0') THEN TEMP<=TEMP;

ELSIF (J='0' AND K='1') THEN TEMP<='0';

ELSIF (J='1' AND K='0') THEN TEMP<='1';

ELSIF (J='1' AND K='1') THEN TEMP<= 11 ;

END IF;

END IF;

END PROCESS;

Q<=TEMP;

END ;

(五) 在下面横线上填上合适的语句,完成计数器的设计。

说明:设电路的控制端均为高电平有效,时钟端CLK,电路的预置数据输入端为4位D,计数输出端也为4位Q,带同步始能EN、异步复位CLR和预置控制LD的六进制减法计数器。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT6 IS

PORT(EN,CLR,LD,CLK:IN STD_LOGIC;

D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT6;

ARCHITECTURE BEHA OF CNT6 IS

SIGNAL QTEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK,CLR,LD)

BEGIN

IF CLR='1' THEN QTEMP<="0000"; --CLR=1清零

ELSIF (CLK'EVENT AND CLK='1') THEN --判断是否上升沿

IF LD='1' THEN QTEMP<= 12 ; --判断是否置位

ELSIF EN='1' THEN --判断是否允许计数

IF QTEMP="0000" THEN QTEMP<= 13 ; --等于0,计数值置5 ELSE QTEMP<= 14 ; --否则,计数值减1

END IF;

END IF;

END IF;

Q<=QTEMP;

END PROCESS;

END BEHA;

(六) 在下面横线上填上合适的语句,完成状态机的设计。

说明:设计一个双进程状态机,状态0时如果输入”10”则转为下一状态,否则输出”1001”;状态1时如果输入”11”则转为下一状态,否则输出”0101”;状态2时如果输入”01”则转为下一状态,否则输出”1100”;状态3时如果输入”00”则转为状态0,否则输出”0010”。复位时

为状态0。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MOORE1 IS

PORT (DATAIN: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

CLK, RST:IN STD_LOGIC;

Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END;

ARCHITECTURE ONE OF MOORE1 IS

TYPE ST_TYPE IS (ST0, ST1, ST2, ST3); --定义4个状态

SIGNAL CST, NST: ST_TYPE; --定义两个信号(现态和次态)SIGNAL Q1:STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

REG: PROCESS(CLK, RST) --主控时序进程

BEGIN

IF RST='1' THEN CST<= 15 ; --异步复位为状态0

ELSIF CLK'EVENT AND CLK='1' THEN

CST<= 16 ; --现态=次态

END IF;

END PROCESS;

COM: PROCESS(CST, DA TAIN)

BEGIN

CASE CST IS

WHEN ST0 => IF DATAIN="10" THEN NST<=ST1;

ELSE NST<=ST0; Q1<="1001"; END IF;

WHEN ST1 => IF DATAIN="11" THEN NST<=ST2;

ELSE NST<=ST1; Q1<="0101"; END IF;

WHEN ST2 => IF DATAIN="01" THEN NST<=ST3;

ELSE NST<=ST2; Q1<="1100"; END IF;

WHEN ST3 => IF DATAIN="00" THEN NST<=ST0;

ELSE NST<=ST3; Q1<="0010"; END IF;

17 ;

END PROCESS;

Q<=Q1;

END;

(七) 在下面横线上填上合适的语句,完成减法器的设计。

由两个1位的半减器组成一个1位的全减器

--1位半减器的描述

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY HALF_SUB IS

PORT(A,B : IN STD_LOGIC;

DIFF,COUT : OUT STD_LOGIC);

END HALF_SUB;

ARCHITECTURE ART OF HALF_SUB IS

BEGIN

COUT<= 18 ; --借位

DIFF<= 19 ; --差

END ;

--1位全减器描述

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FALF_SUB IS

PORT(A,B,CIN: IN STD_LOGIC;

DIFF,COUT : OUT STD_LOGIC);

END FALF_SUB;

ARCHITECTURE ART OF FALF_SUB IS

COMPONENT HALF_SUB

PORT(A,B : IN STD_LOGIC;

DIFF,COUT : OUT STD_LOGIC);

END COMPONENT;

20 T0,T1,T2:STD_LOGIC;

BEGIN

U1: HALF_SUB PORT MAP(A,B, 21 ,T1);

U2: HALF_SUB PORT MAP(T0, 22 , 23 ,T2); COUT<= 24 ;

END ;

(八) 在下面横线上填上合适的语句,完成分频器的设计。

说明:占空比为1:2的8分频器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CLKDIV8_1TO2 IS

PORT(CLK:IN STD_LOGIC;

CLKOUT:OUT STD_LOGIC );

END CLKDIV8_1TO2;

ARCHITECTURE TWO OF CLKDIV8_1TO2 IS

SIGNAL CNT:STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL CK:STD_LOGIC;

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE( 25 ) THEN

IF CNT="11" THEN

CNT<="00";

CK<= 26 ;

ELSE CNT<= 27 ;

END IF;

END IF;

CLKOUT<=CK;

END PROCESS;

END;

(九) 在下面横线上填上合适的语句,完成60进制减计数器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNT IS

PORT(CLK: IN STD_LOGIC;

H,L: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COUNT;

ARCHITECTURE BHV OF COUNT IS

BEGIN

PROCESS(CLK)

V ARIABLE HH,LL: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF LL=0 AND HH=0 THEN

HH:="0101"; LL:="1001";

ELSIF LL=0 THEN

LL:= 28 ;

HH:= 29 ;

ELSE

LL:= 30 ;

END IF;

END IF;

H<=HH;

L<=LL;

END PROCESS;

END BHV;

(十)在下面横线上填上合适的语句,完成4-2优先编码器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CODE4 IS

PORT(A,B,C,D : IN STD_LOGIC;

Y0,Y1 : OUT STD_LOGIC);

END CODE4;

ARCHITECTURE CODE4 OF CODE4 IS

SIGNAL DDD:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL Q:STD_LOGIC_VECTOR( 31 DOWNTO 0);

BEGIN

DDD<= 32 ;

PROCESS(DDD)

BEGIN

IF (DDD(0)='0') THEN Q <= "11";

ELSIF (DDD(1)='0') THEN Q <= "10";

ELSIF(DDD(2)='0') THEN Q<="01";

ELSE Q <= "00";

END IF;

33 ;

Y1<=Q(0); Y0<=Q(1);

END CODE4;

(十一) 在下面横线上填上合适的语句,完成10位二进制加法器电路的设计。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ 34 .ALL;

ENTITY ADDER1 IS

PORT(A,B:IN STD_LOGIC_VECTOR(9 DOWNTO 0);

COUT:OUT STD_LOGIC;

SUM:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));

END;

ARCHITECTURE JG OF ADDER1 IS

SIGNAL ATEMP: STD_LOGIC_VECTOR(10 DOWNTO 0);

SIGNAL BTEMP: STD_LOGIC_VECTOR(10 DOWNTO 0);

SIGNAL SUMTEMP: STD_LOGIC_VECTOR( 35 DOWNTO 0); BEGIN

ATEMP<=?0?& A;BTEMP<=?0?& B;

SUMTEMP<= 36 ;

SUM<=SUMTEMP(9 DOWNTO 0);

COUT<= 37 ;

END JG;

(十二) 在下面横线上填上合适的语句,完成移位寄存器的设计。

说明:8位的移位寄存器,具有左移一位或右移一位、并行输入和同步复位的功能。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY SHIFTER IS

PORT(DATA :IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CLK:IN STD_LOGIC;

SHIFTLEFT,SHIFTRIGHT:IN STD_LOGIC;

RESET:IN STD_LOGIC;

MODE:IN STD_LOGIC_VECTOR(1 DOWNTO 0);

QOUT:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0));

END SHIFTER;

ARCHITECTURE ART OF SHIFTER IS

BEGIN

PROCESS

BEGIN

38 (RISING_EDGE(CLK)); --等待上升沿

IF RESET='1' THEN QOUT<="00000000"; --同步复位ELSE

CASE MODE IS

WHEN "01"=>QOUT<=SHIFTRIGHT& 39 ; --右移一位WHEN "10"=>QOUT<=QOUT(6 DOWNTO 0)& 40 ; --左移一位WHEN "11"=>QOUT<= 41 ; --不移,并行输入WHEN OTHERS=>NULL;

42 ;

END IF;

END PROCESS;

END ART;

(十三) 在下面横线上填上合适的语句,完成计数器的设计。

说明:设计一个带有异步复位和时钟使能的一位八进制加法计数器(带进位输出端)。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT8 IS

PORT (CLK,RST,EN : IN STD_LOGIC;

CQ : OUT STD_LOGIC_VECTOR( 43 DOWNTO 0);

COUT : OUT STD_LOGIC );

END CNT8;

ARCHITECTURE BEHA V OF CNT8 IS

BEGIN

PROCESS(CLK, RST, EN)

44 CQI : STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

IF RST = '1' THEN CQI := “000”;

45CLK'EVENT AND CLK='1' THEN

IF EN = '1' THEN

IF CQI < "111" THEN CQI := 46 ;

ELSE CQI := 47 ;

END IF;

END IF;

END IF;

IF CQI = "111" THEN COUT <= '1';

ELSE COUT <= '0';

END IF;

CQ <= CQI;

END PROCESS;

END BEHA V;

(十四) 在下面横线上填上合适的语句,完成序列信号发生器的设计。

说明:已知发送信号为”10011010”,要求以由高到低的序列形式一位一位的发送,发送开始前及发送完为低电平。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY XULIE IS

PORT (RES, CLK: IN STD_LOGIC;

Y: OUT STD_LOGIC );

END;

ARCHITECTURE ARCH OF XULIE IS

SIGNAL REG:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS(CLK, RES)

BEGIN

IF(CLK?EVENT AND CLK=?1?) THEN

IF RES=?1? THEN

Y<=?0?;REG<= 48 ; --同步复位,并加载输入

ELSE Y<= 49 ; --高位输出

REG<= 50 ; --左移,低位补0

END IF;

END IF;

END PROCESS;

END;

(十五) 在下面横线上填上合适的语句,完成数据选择器的设计。

说明:采用元件例化的设计方法,先设计一个2选1多路选择器,再使用3个2选1多路选择器构成一个4选1多路选择器。

LIBRARY IEEE; --2选1多路选择器的描述

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX21 IS

PORT(A,B,SEL : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END MUX21;

ARCHITECTURE ART OF MUX21 IS

BEGIN

Y<=A WHEN SEL='0' ELSE B;

END ;

LIBRARY IEEE; --4选1多路选择器的描述

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41 IS

PORT(A,B,C,D : IN STD_LOGIC;

S1,S2 : IN STD_LOGIC;

Y:OUT STD_LOGIC) ;

END;

ARCHITECTURE ART OF MUX41 IS

COMPONENT MUX41

PORT(A,B,SEL : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END COMPONENT;

51 Y1,Y2:STD_LOGIC;

BEGIN

U1: MUX21 PORT MAP(A,B,S1, 52 );

U2: MUX21 PORT MAP(C,D, 52 ,Y2);

U2: MUX21 PORT MAP(Y1,Y2, 54 ,Y);

END ;

(十六) 在下面横线上填上合适的语句,完成8位奇偶校验电路的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PC IS

PORT ( A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

Y : OUT STD_LOGIC );

END PC;

ARCHITECTURE A OF PC IS

BEGIN

PROCESS(A).

V ARIABLE TMP: STD_LOGIC;

BEGIN

TMP 55 '0';

FOR I IN 0 TO 7 LOOP

TMP:= 56 ;

END LOOP;

Y<= 57 ;

END PROCESS;

END;

(十七)在下面横线上填上合适的语句,完成一个逻辑电路的设计,

其布尔方程为Y=(A+B)(C⊙D)+(B⊕F).

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY COMB IS

PORT(A, B,C,D,E,F,: IN STD_LOGIC;

Y: OUT STD_LOGIC);

END COMB;

ARCHITECTURE ONE OF COMB IS

BEGIN

Y<=(A OR B) AND (C 58 D) OR (B 59 F);

END ARCHITECTURE ONE;

(十八)在下面横线上填上合适的语句,完成一个带使能功能的二-十进制译码器的设计。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MY2TO10 IS

PORT (EN: IN STD_LOGIC;

DIN: IN STD_LOGIC_VECTOR(60 DOWNTO 0);

POUT: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );

END;

ARCHITECTURE ARCH OF MY2TO10 IS

BEGIN

PROCESS(EN, DIN)

BEGIN

IF EN=’1’ THEN

CASE DIN IS

WHEN "0000" => POUT<="0000000001";

WHEN "0001" => POUT<="0000000010";

WHEN "0010" => POUT<="0000000100";

WHEN "0011" => POUT<="0000001000";

WHEN "0100" => POUT<="0000010000";

WHEN "0101" => POUT<="0000100000";

WHEN "0110" => POUT<="0001000000";

WHEN "0111" => POUT<="0010000000";

WHEN "1000" => POUT<="010*******";

WHEN "1001" => POUT<="1000000000";

WHEN OTHERS => POUT<="0000000000";

END CASE;

END IF;

END PROCESS;

END;

(十九)在下面横线上填上合适的语句,完成下降沿触发的D触发器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL ;

ENTITY DFF IS

PORT(D,CLK:IN STD_LOGIC;

Q, QB: OUT STD_LOGIC);

END DFF;

ARCHITECTURE BEHAVE OF DFF IS

BEGIN

PROCESS(CLK)

BEGIN

IF 61 AND CLK'EVENT THEN

Q <=62 ;

QB<=NOT D;

END IF;

END PROCESS;

END BEHAVE;

(二十)在下面横线上填上合适的语句,完成移位寄存器的设计。

说明:4位串入-串出移位寄存器有有1个串行数据输入端(DI)、1个串行数据输出输出端(DO)和1个时钟输入端(CLK)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SISO IS

PORT(DI: IN STD_LOGIC;

CLK:IN STD_LOGIC;

DO:OUT STD_LOGIC);

END SISO;

ARCHITECTURE A OF SISO IS

SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(CLK,DI)

BEGIN

IF CLK’ EVENT AND CLK=’1’ THEN

Q(0)<=63 ;

FOR 64 LOOP

Q(I)<=65 ;

END IF;

END PROCESS;

DO<=Q(3);

END A;

(二十一)在下面横线上填上合适的语句,完成同步22进制计数器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNTER22 IS

PORT( CLK: IN STD_LOGIC;

CH, C: OUT STD_LOGIC;

QB1, QA1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END;

ARCHITECTURE BEHAV OF COUNTER22 IS

SIGNAL QB, QA: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL CIN: STD_LOGIC;

BEGIN

QB1<=QB;

QA1<=QA;

PROCESS(CLK)

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF (QA=66 ) OR (QB=2 AND QA=1) THEN QA<="0000"; CIN<='0';

ELSIF QA=67 THEN CIN<='1'; QA<=QA+1;

ELSE QA<=68 ;

CIN<='0';

END IF;

END IF;

END PROCESS;

PROCESS(CIN, CLK)

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF (QB=2 AND QA=1) THEN QB<=69 ; C<='1';

ELSE C<=70 ;

END IF;

IF CIN='1' THEN QB<=71 ;

END IF;

END IF;

END PROCESS;

CH<=CIN;

END;

(二十二)在下面横线上填上合适的语句,完成一个“01111110”序列发生器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY SENQGEN IS

PORT(CLK,CLR,CLOCK:IN STD_LOGIC;

ZO:OUT STD_LOGIC);

END;

ARCHITECTURE ART OF SENQGEN IS

SIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL Z:STD_LOGIC:='0';

BEGIN

PROCESS(CLK,CLR)

BEGIN

IF CLR='1' THEN COUNT<="000";

ELSE

IF CLK='1' AND CLK'EVENT THEN

IF COUNT=72 THEN COUNT<="000";

ELSE COUNT<=COUNT+1;

END IF;

END IF;

END IF;

END PROCESS;

PROCESS(COUNT)

BEGIN

CASE COUNT IS

WHEN "000"=>Z<='0';

WHEN "001"=>Z<='1';

WHEN "010"=>Z<='1';

WHEN "011"=>Z<='1';

WHEN "100"=>Z<='1';

WHEN "101"=>Z<='1';

WHEN "110"=>Z<='1';

WHEN OTHERS=>Z<=73 ;

END CASE;

END PROCESS;

PROCESS(CLOCK,Z)

BEGIN

IF CLOCK='1' AND CLOCK'EVENT THEN

ZO<=74 ;

END IF;

END PROCESS;

END ART;

(二十三)在下面横线上填上合适的语句,完成一个“01111110”序列信号检测器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DETECT IS

PORT( DATAIN:IN STD_LOGIC;

CLK:IN STD_LOGIC;

Q:BUFFER STD_LOGIC);

END DETECT;

ARCHITECTURE ART OF DETECT IS

TYPE STATETYPE IS (S0,S1,S2,S3,S4,S5,S6,S7,S8);

BEGIN

PROCESS(CLK)

VARIABLE 75 :76 ;

BEGIN

Q<='0';

CASE PRESENT_STATE IS

WHEN S0=>

IF DATAIN='0' THEN PRESENT_STATE:=S1;

ELSE PRESENT_STATE:=S0; END IF;

WHEN S1=>

IF DATAIN='1' THEN PRESENT_STATE:=S2;

ELSE PRESENT_STATE:=S1; END IF;

WHEN S2=>

IF DATAIN='1' THEN PRESENT_STATE:=S3;

ELSE PRESENT_STATE:=S1; END IF;

WHEN S3=>

IF DATAIN='1' THEN PRESENT_STATE:=S4;

ELSE PRESENT_STATE:=S1; END IF;

WHEN S4=>

IF DATAIN='1' THEN PRESENT_STATE:=S5;

ELSE PRESENT_STATE:=S1; END IF;

WHEN S5=>

IF DATAIN='1' THEN PRESENT_STATE:=S6;

ELSE PRESENT_STATE:=S1; END IF;

WHEN S6=>

IF DATAIN='1' THEN PRESENT_STATE:=S7;

ELSE PRESENT_STATE:=S1; END IF;

WHEN S7=>

IF DATAIN='0' THEN PRESENT_STATE:=S8;

Q<='1'; ELSE PRESENT_STATE:=S0; END IF;

WHEN S8=>

IF DATAIN='0' THEN PRESENT_STATE:=77 ;

ELSE PRESENT_STATE:=78 ; END IF;

END CASE;

79 CLK='1';

END PROCESS;

END ART;

(二十四)在下面横线上填上合适的语句,完成序列信号发生器的设计。

说明:带异步复位为CLR,时钟端为CLK,输出端为Q,串行输出指定序列(低位先出)。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SENQGEN IS

PORT(CLR,CLK:IN STD_LOGIC;

Q:OUT STD_LOGIC);

END SENQGEN;

ARCHITECTURE BEHA OF SENQGEN IS

SIGNAL Q_TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

PROCESS(CLK,CLR)

BEGIN

IF CLR='1' THEN Q_TEMP<="000";

80 (CLK'EVENT AND CLK='1') THEN

IF Q_TEMP="111" THEN Q_TEMP<="000";

81 Q_TEMP<=Q_TEMP+1;

END IF;

82 ;

END PROCESS;

PROCESS(Q_TEMP)

BEGIN

CASE Q_TEMP IS

WHEN "000"=>Q<='0';WHEN "001"=>Q<='1';

WHEN "010"=>Q<='0';WHEN "011"=>Q<='1';

WHEN "100"=>Q<='1';WHEN "101"=>Q<='1';

WHEN "110"=>Q<='1';WHEN "111"=>Q<='0';

WHEN OTHERS=>83 ;

END CASE;

END PROCESS;

END BEHA;

(二十五)在下面横线上填上合适的语句,完成七人表决器的设计。说明:一个带输出显示的七人表决器(两种结果:同意,反对)。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BIAOJUE7 IS

PORT(D:IN STD_LOGIC_VECTOR(0 TO 6);

RLED,GLED:OUT STD_LOGIC;

LEDSEG:OUT STD_LOGIC_VECTOR( 6 DOWNTO 0)

);

END;

ARCHITECTURE BEV OF BIAOJUE7 IS

BEGIN

PROCESS(D)

VARIABLE COUNT:INTEGER RANGE 0 TO 7 ;

BEGIN

COUNT:=84 ;

FOR 85 LOOP

IF D(I)='1' THEN COUNT:=86 ;

ELSE COUNT:=COUNT;

END IF;

END LOOP;

IF COUNT>87 THEN GLED<='1'; RLED<='0'; ELSE GLED<='0'; RLED<='1';

END IF;

CASE COUNT IS

WHEN 0=> LEDSEG<="0111111";

WHEN 1=> LEDSEG<="0000110";

WHEN 2=> LEDSEG<="1011011";

WHEN 3=> LEDSEG<="1001111";

WHEN 4=> LEDSEG<="1100110";

WHEN 5=> LEDSEG<="1101101";

WHEN 6=> LEDSEG<="1111101";

WHEN 7=> LEDSEG<="0100111";

END CASE;

END PROCESS;

END BEV;

(二十六)在下面横线上填上合适的语句,完成有限状态机的设计。

说明:状态转换图如右图,S0~S3为状态号,圈内为输出。

LIBRARY 1EEE;

USE IEEE.STD_ LOGIC_1164.ALL;

PORT( CLK,RESET:IN STD_LOGIC;

INPUTS :IN STD_LOGIC_VECTOR (0 TO 1);

OUTPUTS :OUT INTEGER RANGE (0 TO 15 );

END S_ MACHINE;

ARCHITECTURE BEHA V OF S_MACHINE IS

TYPE STA TES IS (S0,S1, S2,S3);

SIGNAL CURCENT_STA TE,NEXT_STATE:STATES;

BEGIN

REG: PROCESS (RESET,CLK) --状态切换

BEGIN

IF RESET = …1? THEN CURRENT_ STA TE <= S0;

ELSIF CLK=’L’AND CLK‘EVENT THEN

CURRENT_ STA TE <= NEXT_ STA TE;

END IF;

END PROCESS;

COM:PROCESS(CURRENT_ STATE,INPUTS)--下一状态、

BEGIN

CASE CURRENT_ STATE IS

WHEN S0 => OUTPUTS<= 88 ;

IF INPUTS=”00” THEN NEXT_ STA TE<=S0;

ELSE NEXT_ STATE<=SL;

END IF;

WHEN SL=> OUTPUTS<=8;

IF INPUTS= 89 THEN NEXT_ STA TE<= 90 ;

ELSE NEXT_STATE<=S2;

END IF;

WHEN S2=> OUTPUTS<=12;

IF INPUTS=“11”THEN NEXT_STATE<=S0;

ELSE NEXT_STATE<= S3;

END IF;

WHEN S3=> OUTPUTS<=14;

IF INPUTS = “11”THEN NEXT_STATE <=S3;;

ELSE NEXT STATE <=S0;

END IF;

END CASE;

91 ;

END BEHA V;

(二十七)在下面横线上填上合适的语句,完成移位寄存器74166的设计。LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TTL74166 IS

PORT( A,B,C,D,E,F,G,H:IN STD_LOGIC; --8位并行输入信号

CLK:IN STD_LOGIC; --时钟信号

RESET:IN STD_LOGIC; --复位信号

SE:IN STD_LOGIC; --串行输入信号

FE:IN STD_LOGIC; --时钟信号禁止端

SL:IN STD_LOGIC; --移位装载控制端

Q:OUT STD_LOGIC); --串行输出信号

END TTL74166;

ARCHITECTURE ART OF TTL74166 IS

SIGNAL TMPREG8:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS(CLK,RESET,SL,FE)

BEGIN

IF RESET='1' THEN TMPREG8<=92 ; Q<=TMPREG8(7); ELSIF CLK'EVENT AND CLK='1' THEN

IF FE='0' THEN

IF SL='0' THEN

TMPREG8(0)<=A;

TMPREG8(1)<=B;

TMPREG8(2)<=C;

TMPREG8(3)<=D;

TMPREG8(4)<=E;

TMPREG8(5)<=F;

TMPREG8(6)<=G;

TMPREG8(7)<=H;

93 SL='1' THEN

FOR I IN TMPREG8'HIGH DOWNTO 94 LOOP

TMPREG8(I)<=95 ;

END LOOP;

TMPREG8(TMPREG8'LOW)<=96 ;

Q<=97 ;

END IF;

END IF;

END IF;

END PROCESS;

END ART;

(二十八)在下面横线上填上合适的语句,完成8位双向总线缓冲器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TRI_BIGATE IS

PORT( A,B: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);

EN, DR: IN STD_LOGIC);

END;

ARCHITECTURE RTL OF TRI_BIGATE IS

SIGNAL AOUT, BOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS(A, DR, EN)

BEGIN IF (EN=‘0’) AND (DR=‘1’) THEN BOUT<=A;

ELSE

BOUT<=“ZZZZZZZZ”;

END IF;

B<=BOUT;

END PROCESS;

PROCESS(B, DR, EN)

BEGIN

IF (EN=‘0’) AND (DR=‘0’) THEN

AOUT<=98 ;

ELSE

AOUT<=99 ;

END IF;

A<=100 ;

END PROCESS;

END;

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