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Low voltage ride through capability of a 5 kW grid-tied solar inverter

Low V oltage Ride Through Capability of a 5kW Grid-Tied Solar Inverter

Christian H.Benz?,W.-Toke Franke,Friedrich W.Fuchs

Christian-Albrechts-University of Kiel,Germany

Institute of Power Electronics and Electrical Drives

?Now Danfoss Solar Inverters A/S/Innovation&Technology,S?nderborg,Denmark

Abstract—Distributed power generation systems(DPGS) such as wind and solar become more and more widely spread.As a consequence grid operating companies demand system services.As part of the general fault ride through (FRT)requirements this paper deals with low voltage ride through(LVRT)capability of a three-phase-four-wire grid-tied solar inverter.The standard system will be described and necessary changes to the control such as positive(PS), negative(NS)and zero sequence(ZS)separation,a stable phase-locked-loop(PLL)as well as voltage support by means of reactive current as well as stress factors to the hardware will be identi?ed.

Keywords—Low Voltage Ride Through,LVRT,Fault Ride Through,FRT,Photovoltaik,PV,Solar Inverter,Power Quality,Grid Codes,P+Resonant,P-Resonant,dq0,3phase 4wire,three-phase-four-wire

I.I NTRODUCTION

With increasing penetration of renewable energies more and more participation on power quality is required in countries like USA,Canada,France,Spain,Germany and Denmark according to[1].With much bigger propor-tion one important feature for wind turbines already is the low voltage ride through(LVRT)capability bring-ing along challenges.Photovoltaic(PV)systems,mostly evolving from single phase applications connected to the low voltage(LV)grid the most attention was paid to maximum power point(MPP)tracking,maximization of active current due to the individual feed in tariff and strict disconnection in any kind of grid faults following interconnection standards such as IEEE1547,UL1741, G83/1or VDE0126-1-1along with national regulations. The overall amount of distributed power generation sys-tems(DPGS)for renewable energy is rapidly increasing. Besides large wind systems not only small PV systems are highly requested but also larger systems of multi MW size either built from central inverters or from a sum of string inverters.With increasing plant size more often connected to the medium voltage(MV)grid and thereby highly increased installed power also PV system starting to have en effect on power quality.As a consequence the interconnection requirements start changing rapidly, requiring participation on system services.Therefore and due to the differences of renewable energies the speci?c behaviour of solar inverters will be investigated.The pa-per is structured as following:In section II power quality and the requirements on grid interconnetion are presented.In the following section the system is described.In sec-tions IV,V and VI the theoretical background is absorbed, simulations are investigated and experimental results are presented.In the last section there is a conclusion.

II.P OWER Q UALITY AND G RID I NTERCONNECTION Power quality is a widely spread area and therefore effected by a variety of phenomena[2].Beyond that it can be seen directly related to voltage and by ohmic law to current quality.EN50160[3]is the central European reference de?ning the voltage quality to the consumer. V oltage quality can among others be de?ned by the Total Harmonic Distortion(THD)and the V oltage Unbalance Factor(VUF).According to the newest version of[3] the voltage THD shall be less than8%and the VUF less than2%to3%.The THD is not directly affected by grid unbalance and according to[3]it is de?ned as the square root of the sum of the harmonics X h divided by the fundamental X1:

T HD=

n=40 h=2X2h

(1) Whereas the VUF is directly related to unbalances in the voltage.The de?nition from[3]calculates the ratio of Negative Sequence(NS)to Positive Sequence(PS)from phase to phase voltages.Following[3]unbalance regard-ing the Zero Sequence(ZS)is not considered relevant for the possible interference of appliances connected to the grid and thereby no limits are de?ned.

V UF=

|U?|

|U+|

= 6·(U2ab+U2bc+U2ca)

(U ab+U bc+U ca)2

?2(2) It is further stated that transient grid failures can occur up to1000times a year.To avoid misunderstandings,it has to be cleared out that[3]does not include limits for emission of harmonics or unbalance but instead values of what can be expected from the grid.Current quality is not de?ned for faulty grid conditions yet and will therefore not be considered in the following.The national grid codes went rapidly through a change of paradigma, coming from disconnection in case of any grid failure and a maximized active power delivery to sharing reactive power for voltage support i.e.by a constant cos(?)differ-ent to1and even grid support in case of transient failures.

14th International Power Electronics and Motion Control Conference, EPE-PEMC 2010

control structure.Starting with the controller itself,taking a stable Phase-Locked-Loop(PLL)into consideration and showing different methods for sequence separation and the chosen detection method for voltage dips and swells it leads to the necessary design.

A.P+Resonant Controller

The often used PI controller shown in eq.(5)perfectly controls DC signals.Therefore the standard approach to control three phase systems is using dq transformations to transform the signal into DC.

G P I=K P+K I,P I·1

(5)

By contrast the resonant controller can track sinusoidal signals having an in?nit gain at its resonance frequency as described among others in[10]and[11].

G P R=K P+K I,P R·

s2+ω2

(6)

Following[12]the connection between both types of controller can be shown using a lowpass-bandpass-tranformation described in eq.(7)by which the transfor-mation from PI(5)to PR(6)can be achieved.Attention has to be paid to the factor of2resulting in a the rede?nition K I,P R=2·K I,P I In this case not the signal is transformed but instead the controller.

s??s2+ω2

2·s

(7)

B.Phase Lock Loop

Faulty grids and unsymmetrical conditions can lead to failing PLL behaviour.In[13]PLL behavior within faulty grid conditions is studied.For synchronization purposes a dq-PLL is used.It is based on Park’s dq-transformation and will therefore be affected by unsymmetrical grid conditions.The sequence separation method will be used as a pre-?lter to give only the PS onto the PLL.This carries out two tasks simultaneously:First it stabilizes the PLL within unsymmetrical conditions as illustrated in ?g.5and?g.6from t=0.05s.Second it ensures the required orientation of the current.

C.Dip Detection and Sequence Separation Methods Two different approaches of dip detection and thereby calculating the required reactive current have been stud-ied.The grid code compliant root mean square(RMS) method is based

on calculating the voltages between Fig.4.Solar inverter with earthed dc link midpoint

[

]

Time[s]

https://www.wendangku.net/doc/ba15984095.html,parison of standard PLL Performance

[

]

Time[s]

https://www.wendangku.net/doc/ba15984095.html,parison of PLL Performance with pre-?lter

phases.By calculating the RMS value over half a period T for each phase detection of the phase to phase(p2p) voltage drop can be determined.

x p2p,RMS= 2T·t0+T/2 t0x2p2p(t)d t(8)

Through sequence separation also the change of PS could be taken for detection purposes,resulting in slightly dif-ferent results from the RMS method under unsymmetrical conditions.As already discussed in[14],[15]and[16] different methods for sequence separation can be found for three-phase-systems.They differ mainly in stability against harmonics and noise as well as detection speed. Based on Clark’sαβ0transformation the zero sequence (ZS)is separated,so that only positive(PS)and negative sequence(NS)remain within the signal.Hereby the methods become also applicable to three-phase-four wire systems as described above.As described in[14]PS(+) as well as NS(-)can be isolated inαβcoordinates by smartly setting the signals against their orthogonal https://www.wendangku.net/doc/ba15984095.html,mon goal of the three separation methods is the creation of the orthogonal component.The T/4 method delays a signal to itself by one fourth of a period and provides thereby cancelling capability for periodic signals.To the same time it reduces accuracy with noise signals.By using the following equations the PS and NS can be obtained.

αβ,T/4

· xαβ(t)+jxαβ t?T4 (9)

αβ,T/4

· xαβ(t)?jxαβ t?T4 (10) The differentiation method(DT)has been studied in[15]. It creates the orthogonal component by differentiating the

signal what makes it very sensible to harmonics.x +

αβ,DT

=12· x αβ(t ?T S )+j ?1ω0 d d t x αβ(t ) (11)x ?αβ,DT =12· x αβ(t ?T S )?j ?1ω0 d d t x αβ(t ) (12)As stated in [14]and [17]the orthogonal component can also be created by using a second-order-generalized-integrator (SOGI)whereas the operator q =e ?j π2.x +αβ,SOGI =12· 1?q q 1 ·x αβ(13)x ?αβ,SOGI =12· 1q ?q 1 ·x αβ(14)In both of the following cases a symmetrical fault (a=b=c=50%)was applied.Fig.7shows the performance of three sequence separation methods also for dip/swell detection and the pure detection method of RMS under ideal conditions whereas ?g.8shows the behavior under grid conditions with a THD of 5%.It can be observed that T/4method does have discontinuities depending on the amplitude of the original wave at failure start.While oscillating with 50V the differentiation method as the fastest method shows highly unsatisfying results under harmonic distorted conditions.SOGI is the slowest but most stable method also under noisy and harmonic distorted conditions.Both,T/4and SOGI are usable for sequence separation and thereby for dip detection by means of PS change.The RMS dip detection method de-tects all kind of dips as well as swells with high accuracy in standard time of half a period.In the following the dip and swell detection will be performed by RMS method in compliance with the grid codes.

U d +/U N

U x y /U x y ,N

Time [s]Fig.7.

Detection methods under unsymmetrical grid fault

U d +/U N

U x y /U x y ,N Time [s]Fig.8.Detection methods under symmetrical grid fault with

harmonics (THD=5%) D.Control Structure A cascaded control structure as shown in ?g.9was chosen.Sequence separation is performed on sampled grid voltages by use of the SOGI method.Because of stability problems with harmonics as shown above the

differentiation method will be neglected,although it is the

fastest of the investigated methods.The often stated T/4

is fast but shows only advantages with periodic signals.

So noise and partly harmonics corrupt performance.The

separated PS is given onto the PLL for synchronization

and stabilization purposes as well as for orientation of

the reactive current during faulty grid conditions.Two

current limitations are implemented.First after the DC-

Link controller limiting the active reference to the rated

current and second after the reference calculation limiting

the vector sum of the currents again to the rated current.

The DC-Link controller generates the active reference

current i ?d,DC under normal grid conditions.The reference

calculation generates the active i ?d and the reactive i ?q (including LCL ?lter comensation)[18]reference current

for the under laid P+Resonant controllers.To improve

the dynamics of the control loop a feed-forward of the

grid voltage is implemented and placed before generating

the PWM pattern.Fig.10illustrates the performance

without grid voltage feed-forward.A voltage dip (a=50%,

b=c=100%)is applied on the shown phase,resulting in

an increasing inverter output current (blue).The reference

current (green)is met by the inverter output current after

14ms.Whereas ?g.11shows the improved bahaviour

including the feed-forward for the same voltage dip,

enabling the control to be fast enough to meet the require-

ments for reactive current delivery as discussed above as

well as protecting the hardware from overcurrent.

V.S IMULATION R ESULTS

The following simulations show different voltage dips

under precondition of a voltage fall and rise time of

u Fig.9.Control Structure

1ms to take cable length and transformation from higher

grid voltage levels into consideration.The described PV

characteristic shown in ?g.3was chosen in a way that

the booster could be deactived for all simulations to

represent a basic solar inverter.Fig.12illustrates in a)a

symmetrical dip (a=b=c=50%)that occurs at 100ms and

lasts for 75ms.The collapsing phases carry an increase of

the currents as seen in b)because of the changed voltage

slope.Further the DC link voltage c)has a dip at failure

start and end because of a varying power transfer before

the DC link controller has adapted.The related active

power P and reactive power Q is shown in d).It can

be seen that the inverters can handle symmetrical grid

faults with a standard control,as long as the grid currents

are limited.Fig.13illustrates simulations results from

an unsymmetrical failure of the same time span.Highly

distorted and excessive grid currents in b),swinging

active and reactive power transfer in d)and by that a

swinging DC link in c)are the upcoming side effects.

Neglecting possible hardware issues at high DC voltages

as ?rst sub conclusion it can be stated that solar inverters

with line current limitation are capable of symmetrical

grid faults.Second they are not necessarily capable of

unsymmetrical grid failures with a standard control loop,

mainly depending on the used PLL.Further in both of

the standard scenarios the inverter does not deliver the

required reactive current for voltage support.Therefore

the advanced control loop as described above was devel-

oped.Its performance under unsymmetrical transient grid

conditions (a=b=100%,c=0%)is shown in ?g.14.The

expected behavior of active and reactive power by means

of swinging can be in?uenced by control strategies as

studied in [14].Each optimization carries a compromise

with its related side effects.The implementation of such

strategies seems not to be necessary referring to no written

requirements in the grid codes regarding balanced or

unbalanced currents to the time being and will therefore

be neglected.Reactive current is fed into the grid as it can

be seen from the reactive power signal Q in d).Using this

control both powers are swinging,which could on the one

hand effect the lifetime of the DC link capacitors regard-

ing the active power but on the other hand this keeps

the THD lower.As studied in [14]the more constant

the powers become the more distorded become the grid

currents.Due to the increase of reactive current and

the Fig.10.Control without grid voltage

feed-forward Fig.11.Control with grid voltage feed-forward

U a b c [V ]

I a b c [A ]

U D C [V ]

P [W ],Q [V A r ]Time [s]

Fig.12.Symmetrical LVRT with standard control U

a b c [V ]

I a b c [A ]U D C [V ]

P [W ],Q [V A r ]Time [s]

Fig.13.Unsymmetrical LVRT with standard control U a

b c [V ]

I a b c [A ]U D C [V ]

P [W ],Q [V A r ]Time [s]Fig.14.Unsymmetrical LVRT with advanced control

system operating at nominal power the active current has to be reduced for system security purposes leading to a increase of the DC link voltage as seen in c).A slight unsteadiness in the symmetrical current signal can be identi?ed at failure start and end.The increase of the DC link voltage is limited to U oc by the I/V characteristic of the solar system,since this voltage is reached no power is transferred from the PV array.Additionally layouting PV systems the maximum voltage U oc is mostly calculated at ?10?C.Depending on the used PV modules this gives an extra safety margin on the voltage following eq.(4)that might enable semiconductors to operate with full current without delivering active power but instead only reactive current.Taking an additional voltage margin due to the PV layout at ?10?C into account and although the PV array does not deliver any power in case U oc is reached,challenges arise.It can be stated that depending on the chosen PV modules as well as semiconductors it is recommended that the maximum voltage is limited by any method to ensure safe operation of the semiconductors as well as to reduce stress on the DC link capacitors.

VI.M EASUREMENTS

A.Test Setup

As power source a standard power supply was used.

The inverter was controlled with an In?nion TriCore

1796μController and connected through a transformer

to the public grid.The switching frequency was chosen

to 20kHz whereas the sampling frequency was 5kHz.

The LCL ?lter was built up slightly different from the

simulation parameters using a choke on the inverter side

L C =2.5mH ,a choke on the grid side L G =0.5mH

and a capacitor C F =4.4μF leading to a resonance

frequency around f res =3717Hz .Grid failures were

performed using a sag generator according to [19].Mea-

surements were performed using either internal registers

of the TriCore itself or a Dewetron DEWE2010power

meter.

B.Phase Locked Loop

The PLL was tested with and without pre-?lter showing

that unsymmetrical voltages will effect the PLL heavily

as it was expected from the simulations.Fig.15shows

the performance of the used PLL with PS pre-?lter at

unsymmetrical grid conditions (a=b=100%,c=0%).Clear

PS characterization of the grid voltage is the foundation of

high quality voltage support by means of reactive current

according to the requirements of [8].In the following 100

steps are equivalent to one grid period of 20ms.

C.Sequence Separation and Detection

The performance of the sequence separation and de-

tection methods over time as studied in the simulations

in ?g.7and ?g.8is illustrated for the three realized

methods in ?g.16,?g.17and ?g.18.The measurement

results are very well ?tting to the above described simu-

lation results regarding characteristic behaviour,detection

time and behaviour due to noise.The accuracy of the

dip /swell detection by the used RMS method was

investigated among others with an unsymmetrical grid

failure (a=b=100%,c=0%).The expected result of 57.4%

remaining voltage can be achieved with a slight variation,

probably depending on a slight variance in measurement

accuracy of the voltage

measurement.φ[r a d ]t [Timerticks]t [s]/5000Fig.15.Measurement performance dq-PLL with pre-?lter

U /U N [%]t [Timerticks]t [s]/

5000Fig.16.Measurement performance T/4

method U /U N [%]t [Timerticks]t [s]/5000Fig.17.Measurement performance SOGI

method U /U N [%]t [Timerticks]t [s]/5000Fig.18.Measurement performance RMS method D.Low Voltage Ride Through Using a controll loop without the described grid voltage feed-forward,LCL ?lter compensation nor line current limitation,the measurements shall be compared

with the simulation results for symmetrical in ?g.12

and for unsymmetrical in ?g.14grid faults.The T/4

method was used as pre-?lter for the PLL.Departing

from the simulations and [8]the grid voltage was

reduced to around one fourth of the nominal voltage and

the required ramp-out of the reactive current after grid

failure clearance according to [8]was neglected to avoid

confusion.In ?g.19the slope for the reactive current

was chosen to k =1.A symmetrical dip (a=b=c=12.5%)

resulting in ca.13V remaining voltage was applied to

the inverter.For the following ?gures k =2was chosen.

Fig.20illustrates a symmetrical LVRT (a=b=c=50%).

As predicted by the simulations in ?g.12the delivered

currents rise depending on the voltage slope.The full

reactive current is not delivered within one periode but

Fig.19.Symmetrical LVRT,grid voltage(upper)and inverter output current(lower)graph

still within the mandatory time of80ms according to [8].Departing from that?g.21shows an unsymmetrical LVRT(a=37%,b=c=100%).It can be seen that due to the common core of the sag generator as described in [19]the dipping phase effects the non dipping phases. Again voltage support by means of reactive current is not quite delivered within one periode of20ms but is still inside the required time of[8].Other than the simulation in?g.14that was performed at nominal power including a line current limitation the currents are not limited and not all three are increasing in the same amount.Due to the reduced voltage using a transformer and using the sag generator which also includes a transformer current distortion and phase displacement is increased with decreasing voltage and current.As sub conlcusion it can be stated that the system behaves as predicted in the simulations.In both cases the basic requirements for voltage support from[5]and[6]by means of staying connected on grid and delivering reactive current as mandatory in[8]can be ful?lled.Anyway the discrete implemented controller design that need to be improved. In addition to the shown measurements the LVRT was also performed with a dq0control according to[10]using the same inverter hardware.These measurements were performed with half the grid voltage.The slope for the required reactive current was chosen to k=1.In general the observed behaviour for symmetrical voltage dips is similar to the previous measurements.Fig.22shows a symmetrical fault(a=b=c=37%).The delivered currents do not rise as heavy as in?g.20.Further a light ring in the output current which is depending on the instantaneous peak value of the failing phase can be obsereved due to the absence of an active damping method.This is created by the capacitor C F of the LCL?lter and dependant on the slope of the voltage failing.Reactive current is delivered to support the voltage.The unsymmetrical LVRT(a=37%, b=c=100%)shown in?g.23shows different behaviour than in?g.21.The current of the failing phase increases as expected but another phase current decreases and all currents are additionally overlaid with harmonic distortion

Fig.20.

Symmetrical LVRT,grid voltage(upper)and inverter output current(lower)graph

Fig.21.Unsymmetrical LVRT,grid voltage(upper)and inverter output current(lower)graph

assumed to be the100Hz created by the existance of the NS.As sub conlcusion it can be statet that the system is able to ride through symetrical grid faults as long as the line current limitations are in place.Unsymmetrical grid faults lead to a NS that can not be handled using the standard dq0control because of the reference frame rotating in positive direction.To prevent this additional NS compensation by means of a dq0reference frame rotation in negative direction is needed.As mentioned in [20]and[21]the resonant controller does not need this due to itsω2in the return path of the integrator which enables the controller handling both sequnces that have in abc reference frame±50Hz.Also for the dq0control the basic requirements for transient voltage support as discussed above can be ful?lled.

VII.C ONCLUSION

The fault ride through capability of a solar inverter is analysed.Main grid requirements are presented.The LVRT of a three-phase-four-wire grid-tied solar system with different control loops,different sequence separation and detection methods as well as stabilization of a three-phase dq-PLL have been investigated by simulations and experimental results.It can be concluded that LVRT capability of solar inverters rises high requirements to

Fig.22.Symmetrical LVRT with dq0control,grid voltage(upper) and inverter output current(lower)

graph

Fig.23.Unsymmetrical LVRT with dq0control,grid voltage(upper) and inverter output current(lower)graph

PLLs,especially under unsymmetrical grid conditions. The investigated topology can handle LVRTs without disconnection as long as a line current limitations are in place.For all types of LVRT special detection methods for transient variation of the grid voltages,a stable PLL as well as sequence separation methods to achieve the PS for orientation purposes of the reactive current required for voltage support have to be https://www.wendangku.net/doc/ba15984095.html,ing P+Resonant controller in abc reference frame no issues due to other sequence components arise.Other than using PI controller in dq0reference frame additional sequence compensation is needed.Although the PV power limits itself,additional stress is created on the DC link capacitors by oscillation during unsymmetrical grid faults and during the absence of a booster stage on the semiconductors by switching full current at the applied open circuit voltage of the PV system.

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