MT9V022_DS_F
PDF: 8129ef0b/Source: 812b6f87
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT9V022_1.fm -Rev.F 12/06 EN
?2005 Micron Technology, Inc. All rights reserved.
1/3-Inch Wide-VGA CMOS Digital Image Sensor
MT9V022
For the latest data sheet revision, refer to Micron’s Web site: https://www.wendangku.net/doc/cf899653.html,/imaging
Features
?Micron ? DigitalClarity ? CMOS imaging technology ?Array format: Wide-VGA, active 752H x 480V (360,960 pixels)
?Global shutter photodiode pixels; simultaneous integration and readout
?Monochrome or color: Near_IR enhanced performance for use with non-visible NIR illumination
?Readout modes: progressive or interlaced ?Shutter efficiency: >99%
?Simple two-wire serial interface ?Register Lock capability
?Window Size: User programmable to any smaller format (QVGA, CIF , QCIF , etc.). Data rate can be maintained independent of window size ?Binning: 2 x 2 and 4 x 4 of the full resolution
?ADC: On-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode)?Automatic Controls: Auto exposure control (AEC) and auto gain control (AGC); variable regional and variable weight AEC/AGC
?Support for four unique serial control register IDs to control multiple imagers on the same bus ?Data output formats: –Single sensor mode:
10-bit parallel/stand-alone 8-bit or 10-bit serial LVDS –Stereo sensor mode:
Interspersed 8-bit serial LVDS
Applications
?Automotive
?Unattended surveillance ?Stereo vision ?Security ?Smart vision ?Automation ?Video as input ?
Machine vision
Table 1: Key Performance Parameters
Ordering Information
Parameter Value
Optical format 1/3-inch
Active imager size 4.51mm(H) x 2.88mm(V)5.35mm diagonal Active pixels 752H x 480V Pixel size
6.0μm x 6.0μm
Color filter array Monochrome or color RGB Bayer pattern
Shutter type
Global shutter—TrueSNAP ?Maximum data rate/ master clock 26.6 MPS/26.6 MHz
Full resolution 752 x 480
Frame rate
60 fps (at full resolution)ADC resolution 10-bit column-parallel Responsivity 4.8 V/lux-sec (550nm)Dynamic range >55dB linear;
>80dB ?100dB in HiDy mode Supply voltage
3.3V +0.3V (all supplies)
Power consumption <320mW at maximum data rate; 100μW standby power Operating temperature -40°C to +85°C
Packaging
52-Ball IBGA, automotive-qualified; wafer or die
Table 2:
Available Part Numbers
Part Number Description
MT9V022I77ATM 52-Ball IBGA (monochrome)MT9V022IA7ATM 52-Ball IBGA (lead-free monochrome)
MT9V022I77ATC 52-Ball IBGA (color)
MT9V022IA7ATC
52-Ball IBGA (lead-free color)
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Color Device Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Pixel Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Interlaced Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Automatic Black Level Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Other Limiting Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Bus Idle State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Start Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Stop Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Acknowledge Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Two-Wire Serial Interface Sample Read and Write Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-Bit Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8-Bit Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 8-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Register Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Lock All Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Lock Read Mode Register Only (R0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Simultaneous Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Sequential Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Snapshot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 On-Chip Biases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 ADC Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 V_Step Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chip Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Blanking Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Pixel Integration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Total Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 R0x0B Total Shutter Width (In Terms of Number of Rows) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 High Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Variable ADC Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Changes to Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Row-wise Noise Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Automatic Gain Control and Automatic Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Pixel Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Hard Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Soft Reset of Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 STANDBY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Monitor Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Read Mode Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Column Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Row Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Pixel Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Row Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Column Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Interlaced Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LINE_VALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 LVDS Serial (Stand-Alone/Stereo) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 LVDS Output Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Propagation Delays for PIXCLK and Data Out Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Propagation Delays for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Performance Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Test 1: Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Test 2: Dark Signal Non-Uniformity (DSNU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Test 3: Photo Response Non-Uniformity (PRNU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Test 4: Dynamic Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Test 5: Signal-to-Noise Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Two-Wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Temperature Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Appendix A–Serial Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Configuration of Sensor for Stand-Alone Serial Output with Internal PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Configuration of Sensor for Stereoscopic Serial Output with Internal PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Broadcast and Individual Writes for Stereoscopic Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Appendix B–Power-On Reset and Standby Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Reset, Clocks, and Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Standby Assertion Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
List of Figures
Figure 1:Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2:52-Ball IBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3:Typical Configuration (Connection)—Parallel Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4:Pixel Array Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5:Pixel Color Pattern Detail (Top Right Corner). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6:Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7:Timing Example of Pixel Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8:Row Timing and FRAME_VALID/LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9:Timing Diagram Showing a Write to R0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10:Timing Diagram Showing a Read from R0x09; Returned Value 0x0284. . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11:Timing Diagram Showing a Bytewise Write to R0x09 with the Value 0x0284. . . . . . . . . . . . . . . . . . . . 18 Figure 12:Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284. . . . . . . . . . . . . . . . 18 Figure 13:Simultaneous Master Mode Synchronization Waveforms #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 14:Simultaneous Master Mode Synchronization Waveforms #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 15:Sequential Master Mode Synchronization Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 16:Snapshot Mode Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 17:Snapshot Mode Frame Synchronization Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 18:Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 19:Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 20:Latency When Changing Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 21:Sequence of Control Voltages at the HDR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22:Sequence of Voltages in a Piecewise Linear Pixel Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 23:12- to 10-Bit Companding Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 24:Latency of Analog Gain Change When AGC Is Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 25:Tiled Sample. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 26:Black Level Calibration Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 27:Controllable and Observable AEC/AGC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 28:Readout of Six Pixels in Normal and Column Flip Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 29:Readout of Six Rows in Normal and Row Flip Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 30:Readout of 8 Pixels in Normal and Row Bin Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 31:Readout of 8 Pixels in Normal and Column Bin Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 32:Spatial Illustration of Interlaced Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 33:Different LINE_VALID Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 34:Serial Output Format for a 6x2 Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 35:Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 36:Propagation Delays for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 37:Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 38:Serial Host Interface Stop Condition Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 39:Serial Host Interface Data Timing for Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 40:Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 41:Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 42:Acknowledge Signal Timing After an 8-Bit READ from the Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 43:Typical Quantum Efficiency—Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 44:Typical Quantum Efficiency—Monochrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 45:52-Ball IBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 46:Stand-Alone Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 47:Stereoscopic Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 48:Two-Wire Serial Interface Configuration in Stereoscopic Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 49:Power-up, Reset, Clock and Standby Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 50:STANDBY Restricted Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
List of Tables
Table 1:Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2:Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 3:Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 4:Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 5:Frame Time—Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 6:Slave Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 7:Default Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 8:Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 9:LVDS Packet Format in Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Table 10:LVDS Packet Format in Stereoscopy Mode (Stereoscopy Mode Bit Asserted) . . . . . . . . . . . . . . . . . . .57 Table 11:Reserved Words in the Pixel Data Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 12:DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 13:Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 14:AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 15:Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
General Description
The Micron? Imaging MT9V022 is a 1/3-inch wide-VGA format CMOS active-pixel
digital image sensor with global shutter and high dynamic range (HDR) operation. The
sensor has specifically been designed to support the demanding interior and exterior
automotive imaging needs, which makes this part ideal for a wide variety of imaging
applications in real-world environments.
This wide-VGA CMOS image sensor features DigitalClarity?Micron’s breakthrough low-
noise CMOS imaging technology that achieves CCD image quality (based on signal-to-
noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and inte-
gration advantages of CMOS.
The active imaging pixel array is 752H x480V. It incorporates sophisticated camera func-
tions on-chip—such as binning 2x2 and 4x4, to improve sensitivity when operating in
smaller resolutions—as well as windowing, column and row mirroring. It is program-
mable through a simple two-wire serial interface.
The MT9V022 can be operated in its default mode or be programmed for frame size,
exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-
size image at 60 frames per second (fps).
An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolu-
tion companded for 10 bits for small signals can be alternatively enabled, allowing more
accurate digitization for darker areas in the image.
In addition to a traditional, parallel logic output the MT9V022 also features a serial low-
voltage differential signaling (LVDS) output. The sensor can be operated in a stereo-
camera, and the sensor, designated as a stereo-master, is able to merge the data from
itself and the stereo-slave sensor into one serial LVDS stream.
The sensor is designed to operate in a wide temperature range (–40°C to +85°C).
Figure 1: Block Diagram
Figure 2: 52-Ball IBGA Package
Ball Descriptions
Table 3: Ball Descriptions
Only pins D OUT0 through D OUT9 may be tri-stated.
52-Ball IBGA
Numbers Symbol Type Description Note H7RSVD Input Connect to D GND.1 D2SER_DATAIN_N Input Serial data in for stereoscopy (differential negative).
Tie to 1KΩ pull-up (to 3.3V) in non-stereoscopy mode.
D1SER_DATAIN_P Input Serial data in for stereoscopy (differential positive).
Tie to D GND in non-stereoscopy mode.
C2BYPASS_CLKIN_N Input Input bypass shift-CLK (differential negative). Tie to
1KΩ pull-up (to 3.3V) in non-stereoscopy mode.
C1BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to
D GND in non-stereoscopy mode.
H3EXPOSURE Input Rising edge starts exposure in slave mode.
H4SCLK Input Two-wire serial interface clock. Connect to V DD with
1.5K resistor even when no other two-wire serial
interface peripheral is attached.
H6OE Input D OUT enable pad, active HIGH.2 G7S_CTRL_ADR0Input Two-wire serial interface slave address bit 3.
H8S_CTRL_ADR1Input Two-wire serial interface slave address bit 5.
G8RESET#Input Asynchronous reset. All registers assume defaults.
F8STANDBY Input Shut down sensor operation for power saving.
A5SYSCLK Input Master clock (26.6 MHz).
G4S DATA I/O Two-wire serial interface data. Connect to V DD with
1.5K resistor even when no other two-wire serial
interface peripheral is attached.
G3STLN_OUT I/O Output in master mode—start line sync to drive slave
chip in-phase; input in slave mode.
G5STFRM_OUT I/O Output in master mode—start frame sync to drive a
slave chip in-phase; input in slave mode.
H2LINE_VALID Output Asserted when D OUT data is valid.
G2FRAME_VALID Output Asserted when D OUT data is valid.
E1D OUT5Output Parallel pixel data output 5.
F1D OUT6Output Parallel pixel data output 6.
F2D OUT7Output Parallel pixel data output 7.
G1D OUT8Output Parallel pixel data output 8
H1D OUT9Output Parallel pixel data output 9.
H5ERROR Output Error detected. Directly connected to STEREO ERROR
FLAG.
G6LED_OUT Output LED strobe output.
B7D OUT4Output Parallel pixel data output 4.
A8D OUT3Output Parallel pixel data output 3.
A7D OUT2Output Parallel pixel data output 2.
B6D OUT1Output Parallel pixel data output 1.
A6D OUT0Output Parallel pixel data output 0.
B5PIXCLK Output Pixel clock out. D OUT is valid on rising edge of this
clock.
B3SHFT_CLKOUT_N Output Output shift CLK (differential negative).
Notes:
1.Pin H7 (RSVD) must be tied to GND.
2.Output Enable (OE) tri-states signals D OUT 0–D OUT 9. No other signals are tri-stated with OE.
3.No connect. These pins must be left floating for proper operation.
Figure 3: Typical Configuration (Connection)—Parallel Output Mode
Note:LVDS signals are to be left floating.
B2SHFT_CLKOUT_P Output Output shift CLK (differential positive).A3SER_DATAOUT_N Output Serial data out (differential negative).A2SER_DATAOUT_P
Output Serial data out (differential positive).B4, E2V DD Supply Digital power 3.3V.C8, F7V AA Supply Analog power 3.3V.B8VAAPIX Supply Pixel power 3.3V.
A1, A4V DD LVDS Supply Dedicated power for LVDS pads.B1, C3LVDSGND Ground Dedicated GND for LVDS pads.C6, F3D GND Ground Digital GND.C7, F6A GND Ground Analog GND.E7, E8, D7, D8
NC NC
No connect.
3
Table 3:
Ball Descriptions (continued)
Only pins D OUT 0 through D OUT 9 may be tri-stated.
52-Ball IBGA Numbers Symbol Type
Description
Note
Pixel Data Format
Pixel Array Structure
The MT9V022 pixel array is configured as 782 columns by 492 rows, shown in Figure4.
The left 26 columns and the top eight rows of pixels are optically black and can be used
to monitor the black level. The black row data is used internally for the automatic black
level adjustment. However, the middle four black rows can also be read out by setting the
sensor to raw data output mode. There are 753 columns by 481 rows of optically active
pixels. The active area is surrounded with optically transparent dummy columns and
rows to improve image uniformity within the active area. One additional active column
and active row are used to allow horizontally and vertically mirrored readout to also start
on the same color pixel.
Figure 4: Pixel Array Description
Figure 5: Pixel Color Pattern Detail (Top Right Corner)
MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor
Color Device Limitations Color Device Limitations
The color version of the MT9V022 does not support or offers reduced performance for
the following functionalities.
Pixel Binning
Pixel binning is done on immediate neighbor pixels only, no facility is provided to skip
pixels according to a Bayer pattern. Therefore, the result of binning combines pixels of
different colors. For more information, see “Pixel Binning” on page52.
Interlaced Readout
Interlaced readout yields one field consisting only of red and green pixels and another
consisting only of blue and green pixels. This is due to the Bayer pattern of the CFA. Automatic Black Level Calibration
When the color bit is set (R0x0F[2]=1), the sensor uses GREEN1 pixels black level correc-
tion value, which is applied to all colors. To use calibration value based on all dark pixels
offset values, the color bit should be cleared.
Other Limiting Factors
Black level correction and row-wise noise correction are applied uniformly to each color.
Automatic exposure and gain control calculations are made based on all three colors,
not just the green luma channel. High dynamic range does operate; however, Micron
strongly recommends limiting use to linear operation if good color fidelity is required. Output Data Format
The MT9V022 image data can be read out in a progressive scan or interlaced scan mode.
Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure6.
The amount of horizontal and vertical blanking is programmable through R0x05 and
R0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure. See
“Output Data Timing” on page13 for the description of FRAME_VALID timing.
Figure 6:
Spatial Illustration of Image Readout
Output Data Timing
The data output of the MT9V022 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
Figure 7: Timing Example of Pixel Data
The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows
PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled,
the PIXCLK is HIGH for one complete master clock master period and then LOW for one
complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for
two complete master clock periods and then LOW for two complete master clock
periods. It is continuously enabled, even during the blanking period. Setting R0x74
bit[4]=1 causes the MT9V022 to invert the polarity of the PIXCLK.
The parameters P1, A, Q, and P2 in Figure8 are defined in Table4.
Figure 8: Row Timing and FRAME_VALID/LINE_VALID Signals
Table 4: Frame Time
Parameter Name Equation Default Timing at 26.66 MHz A Active data time R0x04 752 pixel clocks
= 752 master
= 28.20μs
P1Frame start blanking R0x05 - 2371 pixel clocks
= 71master
= 2.66μs
P2Frame end blanking23 (fixed)23 pixel clocks
= 23 master
= 0.86μs
Q Horizontal blanking R0x0594 pixel clocks
= 94 master
= 3.52μs
Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to Figure 7 on page 13). The recommended master clock frequency is 26.66 MHz. The
vertical blanking and total frame time equations assume that the number of integration rows (bits 11 through 0 of R0x0B) is less than the number of active rows plus blanking rows minus overhead rows (R0x03 + R0x06 - 2). If this is not the case, the number of inte-gration rows must be used instead to determine the frame time, as shown in Table 5. In this example it is assumed that R0x0B is programmed with 523 rows. For Simultaneous Mode, if the exposure time register (0x0B) exceeds the total readout time, then vertical blanking is internally extended automatically to adjust for the additional integration time required. This extended value is not written back to R0x06 (vertical blanking). R0x06 can be used to adjust frame to frame readout time. This register does not effect the exposure time but it may extend the readout time.
Notes:
1.The MT9V022 uses column parallel analog-digital converters, thus short row timing is not possible. The minimum total row time is 660 columns (horizontal width + horizontal blank-ing). The minimum horizontal blanking is 43. When the window width is set below 617, horizontal blanking must be increased. The frame rate will not increase for row times less than 660 columns.
A+Q
Row time
R0x04 + R0x05
846 pixel clocks = 846 master = 31.72μs
V Vertical blanking (R0x06) x (A + Q) + 4
38,074 pixel clocks = 38,074 master = 1.43ms
Nrows x (A + Q)Frame valid time (R0x03) × (A + Q)
406,080 pixel clocks = 406,080 master = 15.23ms
F Total frame time V + (Nrows x (A + Q))
444,154 pixel clocks = 444,154 master = 16.66ms
Table 5:
Frame Time—Long Integration Time
Parameter Name
Equation
(Number of Master Clock Cycles)Default Timing at 26.66 MHz V’
Vertical blanking (long integration time)(R0x0B + 2 - R0x03) × (A + Q) + 4
38,074 pixel clocks = 38,074 master = 1.43ms
F”Total frame time (long integration time)(R0x0B + 2) × (A + Q) + 4
444,154 pixel clocks = 444,154 master = 16.66ms
Table 4:
Frame Time (continued)
Parameter Name Equation Default Timing at 26.66 MHz
Serial Bus Description
Registers are written to and read from the MT9V022 through the two-wire serial inter-
face bus. The MT9V022 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0
and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is
transferred into the MT9V022 and out through the serial data (S DATA) line. The S DATA
line is pulled up to V DD off-chip by a 1.5KΩ resistor. Either the slave or master device can
pull the S DATA line down—the serial interface protocol determines which device is
allowed to pull the S DATA line down at any given time. The registers are 16-bit wide, and
can be accessed through 16- or 8-bit two-wire serial interface sequences.
Protocol
The two-wire serial interface defines several different transmission codes, as follows:
?a start bit
?the slave device 8-bit address
?a(n) (no) acknowledge bit
?an 8-bit message
?a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device’s 8-bit address. The last bit of the address deter-
mines if the request is a read or a write, where a “0” indicates a write and a “1” indicates
a read. The slave device acknowledges its address by sending an acknowledge bit back to
the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight bits. The MT9V022 uses 16-bit data
for its internal registers, thus requiring two 8-bit transfers to write to one register. After
16 bits are transferred, the register address is automatically incremented, so that the next
16 bits are written to the next register address. The master stops writing by sending a
start or stop bit.
A typical read sequence is executed as follows. First the master sends the write mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read mode slave address. The master then clocks out the register
data eight bits at a time. The master sends an acknowledge bit after each 8-bit transfer.
The register address is auto-incremented after every 16 bits is transferred. The data
transfer is stopped when the master sends a no-acknowledge bit. The MT9V022 allows
for 8-bit data transfers through the two-wire serial interface by writing (or reading) the
most significant 8 bits to the register and then writing (or reading) the least significant 8
bits to R0xF0 (240).
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. As indicated above, the MT9V022 allows four possible slave addresses deter-mined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1.
Data Bit Transfer
One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the serial clock—it can only change when the two-wire serial interface clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indi-cates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
Table 6:
Slave Address Modes
{S_CTRL_ADR1, S_CTRL_ADR0}
Slave Address
Write/Read Mode
000x90Write 0x91Read 010x98Write 0x99Read 100xB0Write 0xB1Read 11
0xB8Write 0xB9
Read
Two-Wire Serial Interface Sample Read and Write Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure9. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor
then gives an acknowledge bit and expects the register address to come first, followed by
the 16-bit data. After each 8-bit the image sensor gives an acknowledge bit. All 16 bits
must be written before the register is updated. After 16 bits are transferred, the register
address is automatically incremented, so that the next 16 bits are written to the next
register. The master stops writing by sending a start or stop bit.
Figure 9: Timing Diagram Showing a Write to R0x09 with the Value 0x0284
16-Bit Read Sequence
A typical read sequence is shown in Figure10. First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data 8 bits
at a time. The master sends an acknowledge bit after each 8-bit transfer. The register
address is auto-incremented after every 16 bits is transferred. The data transfer is
stopped when the master sends a no-acknowledge bit.
Figure 10: Timing Diagram Showing a Read from R0x09; Returned Value 0x0284
8-Bit Write Sequence
To be able to write 1 byte at a time to the register a special register address is added. The
8-bit write is done by first writing the upper 8 bits to the desired register and then writing
the lower 8 bits to the special register address (R0xF0). The register is not updated until
all 16 bits have been written. It is not possible to just update half of a register. In
Figure11 on page18, a typical sequence for 8-bit writing is shown. The second byte is
written to the special register (R0xF0).
Figure 11: Timing Diagram Showing a Bytewise Write to R0x09 with the Value 0x0284
8-Bit Read Sequence
To read one byte at a time the same special register address is used for the lower byte.
The upper 8 bits are read from the desired register. By following this with a read from the
special register (R0xF1) the lower 8 bits are accessed (Figure12). The master sets the no-
acknowledge bits shown.
Figure 12: Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284
Register Lock
Included in the MT9V022 is a register lock (R0xFE) feature that can be used as a solution
to reduce the probability of an inadvertent noise-triggered two-wire serial interface
write to the sensor. All registers (or read mode register—register 13 only) can be locked;
it is important to prevent an inadvertent two-wire serial interface write to register 13 in
automotive applications since this register controls the image orientation and any
unintended flip to an image can cause serious results.
At power-up, the register lock defaults to a value of 0xBEEF, which implies that all
registers are unlocked and any two-wire serial interface writes to the register gets
committed.
Lock All Registers
If a unique pattern (0xDEAD) to R0xFE is programmed, any subsequent two-wire serial
interface writes to registers (except R0xFE) are NOT committed. Alternatively, if the user
writes a 0xBEEF to the register lock register, all registers are unlocked and any
subsequent two-wire serial interface writes to the register are committed.
Lock Read Mode Register Only (R0x0D)
If a unique pattern (0xDEAF) to R0xFE is programmed, any subsequent two-wire serial
interface writes to register 13 is NOT committed. Alternatively, if the user writes a
0xBEEF to register lock register, register 13 is unlocked and any subsequent two-wire
serial interface writes to this register is committed.
Registers
Caution Writing and changing the value of a reserved register (word or bit) puts the device in an unknown state and may damage the device.
Table 7: Default Register Descriptions
1 = always 1; 0 = always 0; d = programmable; ? = read only
Register # (Hex)Description Data Format (Binary)Default Value
(Hex)
0x00Chip Version0001 0011 0001 00001 (LSB)Iter. 1: 0x1311
Iter. 2: 0x1311
Iter. 3: 0x1313 0x01Column Start0000 00dd dddd dddd0x0001
0x02Row Start0000 000d dddd dddd0x0004
0x03Window Height0000 000d dddd dddd0x01E0
0x04Window Width0000 00dd dddd dddd0x02F0
0x05Horizontal Blanking0000 00dd dddd dddd0x005E
0x06Vertical Blanking0ddd dddd dddd dddd0x002D
0x07Chip Control0000 dddd dddd dddd0x0388
0x08Shutter Width 10ddd dddd dddd dddd0x01BB
0x09Shutter Width 20ddd dddd dddd dddd0x01D9
0x0A Shutter Width Ctrl0000 00dd dddd dddd0x0164
0x0B Total Shutter Width0ddd dddd dddd dddd0x01E0
0x0C Reset0000 0000 0000 00dd0x0000
0x0D Read Mode0000 0011 dddd dddd0x0300
0x0E Monitor Mode0000 0000 0000 000d0x0000
0x0F Pixel Operation Mode0000 0000 dddd dddd0x0011
0x10Reserved–0x0040
0x11Reserved–0x8042
0x12Reserved–0x0022
0x13Reserved–0x2D32
0x14Reservedl–0x0E02
0x15Reserved–0x7F32
0x16Reserved–0x2802
0x17Reserved–0x3E38
0x18Reserved–0x3E38
0x19Reserved–0x2802
0x1A Reserved–0x0428
0x1B LED_OUT Ctrl0000 0000 0000 00dd0x0000
0x1C ADC Mode Control0000 0000 0000 00dd0x0002
0x1D Reserved–0x0000
0x1E Reserved–0x0000
0x1F Reserved–0x0000
0x20Reserved –0x01D1
0x21Reserved–0x0020
0x22Reserved–0x0020
0x23Reserved–0x0010
0x24Reserved–0x0010
0x25Reserved–0x0020