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DS90CR284MTD中文资料

DS90CR283/DS90CR28428-Bit Channel Link-66MHz

General Description

The DS90CR283transmitter converts 28bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling)data streams.A phase-locked transmit clock is transmitted in par-allel with the data streams over a fifth LVDS link.Every cycle of the transmit clock 28bits of input data are sampled and transmitted.The DS90CR284receiver converts the LVDS data streams back into 28bits of CMOS/TTL data.At a trans-mit clock frequency of 66MHz,28bits of TTL data are trans-mitted at a rate of 462Mbps per LVDS data https://www.wendangku.net/doc/c77342038.html,ing a 66MHz clock,the data throughput is 1.848Gbit/s (231Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction.Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability).Thus,for a 28-bit wide data bus and one clock,up to 58conductors are required.With the Channel Link chipset as few as 11conductors (4data pairs,1clock pair and a minimum of one ground)are needed.This provides a 80%reduction in required cable

width,which provides a system cost savings,reduces con-nector physical size and cost,and reduces shielding require-ments due to the cables’smaller form factor.

The 28CMOS/TTL inputs can support a variety of signal combinations.For example,74-bit nibbles or 39-bit (byte +parity)and 1control.

Features

n 66MHz clock support

n Up to 231Mbytes/s bandwidth

n Low power CMOS design (<610mW)n Power Down mode (<0.5mW total)n Up to 1.848Gbit/s data throughput

n Narrow bus reduces cable size and cost n 290mV swing LVDS devices for low EMI n PLL requires no external components n Low profile 56-lead TSSOP package n Rising edge data strobe

Compatible with TIA/EIA-644LVDS Standard

Block Diagrams

TRI-STATE ?is a registered trademark of National Semiconductor Corporation.

DS90CR283

DS012889-27Order Number DS90CR283MTD See NS Package Number MTD56DS90CR284

DS012889-1

Order Number DS90CR284MTD See NS Package Number MTD56

July 1997

DS90CR283/DS90CR28428-Bit Channel Link-66MHz

?1998National Semiconductor Corporation https://www.wendangku.net/doc/c77342038.html,

Pin Diagrams

Typical Application

DS90CR283

DS012889-21DS90CR284

DS012889-22

DS012889-23

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Absolute Maximum Ratings(Note1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage(V CC)?0.3V to+6V CMOS/TTL Input Voltage?0.3V to(V CC+0.3V) CMOS/TTL Ouput Voltage?0.3V to(V CC+0.3V) LVDS Receiver Input Voltage?0.3V to(V CC+0.3V) LVDS Driver Output Voltage?0.3V to(V CC+0.3V) LVDS Output Short Circuit

Duration Continuous Junction Temperature+150?C Storage Temperature Range?65?C to+150?C Lead Temperature

(Soldering,4sec.)+260?C Maximum Package Power Dissipation@+25?C

MTD56(TSSOP)Package:

DS90CR283 1.63W DS90CR284 1.61W Package Derating:

DS90CR28312.5mW/?C above+25?C DS90CR28412.4mW/?C above+25?C This device does not meet2000V ESD rating(Note4)

Recommended Operating Conditions

Min Nom Max Units Supply Voltage(V CC) 4.75 5.0 5.25V Operating Free Air

Temperature(T A)?10+25+70?C Receiver Input Range0 2.4V Supply Noise Voltage

(V CC)100mV P-P

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS

V IH High Level Input Voltage 2.0V CC V

V IL Low Level Input Voltage GND0.8V

V OH High Level Output Voltage I OH=?0.4mA 3.8 4.9V

V OL Low Level Output Voltage I OL=2mA0.10.3V

V CL Input Clamp Voltage I CL=?18mA?0.79?1.5V

I IN Input Current V IN=V CC,GND,2.5V or0.4V±5.1±10μA

I OS Output Short Circuit Current V OUT=0V?120mA LVDS DRIVER DC SPEClFlCATIONS

V OD Differential Output Voltage R L=100?250290450mV

?V OD Change in V OD between35mV Complementary Output States

V OS Offset Voltage 1.1 1.25 1.375V

?V OS Change in Magnitude of V OS

between Complementary Output

States

35mV

I OS Output Short Circuit Current V OUT=OV,R L=100??2.9?5mA

I OZ Output TRI-STATE?Current Power Down=0V,V OUT=0V or V CC±1±10μA LVDS RECEIVER DC SPECIFlCATIONS

V TH Differential Input High Threshold V CM=+1.2V+100mV

V TL Differential Input Low Threshold?100mV

I IN Input Current V IN=+2.4V,V CC=5.0V±10μA

V IN=0V,V CC=5.0V±10μA TRANSMITTER SUPPLY CURRENT

I CCTW Transmitter Supply Current,R L=100?,C L=5pF,f=32.5MHz4963mA

Worst Case Worst Case Pattern f=37.5MHz5164mA

(Figures1,2)f=66MHz7084mA

I CCTZ Transmitter Supply Current,Power Down=Low

Power Down Driver Outputs in TRI-STATE

under Power Down Mode125μA

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Electrical Characteristics(Continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units RECEIVER SUPPLY CURRENT

I CCRW Receiver Supply Current,

Worst Case C L=8pF,f=32.5MHz6477mA Worst Case Pattern f=37.5MHz7085mA (Figures1,3)f=66MHz110140mA

I CCRZ Receiver Supply Current,Power Down=Low

Power Down Receiver Outputs in Previous State

during Power Down Mode110μA Note1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the device should be operated at these limits.The tables of“Electrical Characteristics”specify conditions for device operation.

Note2:Typical values are given for V CC=5.0V and T A=+25?C.

Note3:Current into device pins is defined as positive.Current out of device pins is defined as negative.Voltages are referenced to ground unless otherwise speci-fied(except V OD and?V OD).

Note4:ESD Rating:HBM(1.5k?,100pF)

PLL V CC≥1000V

All other pins≥2000V

EIAJ(0?,200pF)≥150V

Note5:V OS previously referred as V CM.

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units LLHT LVDS Low-to-High Transition Time(Figure2)0.75 1.5ns LHLT LVDS High-to-Low Transition Time(Figure2)0.75 1.5ns TCIT TxCLK IN Transition Time(Figure4)8ns TCCS TxOUT Channel-to-Channel Skew(Note6)(Figure5)350ps

TPPos0Transmitter Output Pulse Position for Bit0f=66MHz

?0.3000.30ns

(Figure16)

TPPos1Transmitter Output Pulse Position for Bit1 1.70(1/7)T clk 2.50ns TPPos2Transmitter Output Pulse Position for Bit2 3.60(2/7)T clk 4.50ns TPPos3Transmitter Output Pulse Position for Bit3 5.90(3/7)T clk 6.75ns TPPos4Transmitter Output Pulse Position for Bit48.30(4/7)T clk9.00ns TPPos5Transmitter Output Pulse Position for Bit510.40(5/7)T clk11.10ns TPPos6Transmitter Output Pulse Position for Bit612.70(6/7)T clk13.40

TCIP TxCLK IN Period(Figure6)15T50ns TCIH TxCLK IN High Time(Figure6)0.35T0.5T0.65T ns TCIL TxCLK IN Low Time(Figure6)0.35T0.5T0.65T ns TSTC TxIN Setup to TxCLK IN(Figure6)5 3.5ns THTC TxIN Hold to TxCLK IN(Figure6) 2.5 1.5ns TCCD TxCLK IN to TxCLK OUT Delay@25?C, 3.58.5ns V CC=5.0V(Figure8)

TPLLS Transmitter Phase Lock Loop Set(Figure10)10ms TPDD Transmitter Power Down Delay(Figure14)100ns Note6:This limit based on bench characterization.

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Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time(Figure3) 2.5 4.0ns CHLT CMOS/TTL High-to-Low Transition Time(Figure3) 2.0 4.0ns RSKM RxIN Skew Margin(Note7),f=40MHz700ps V CC=5V,T A=25?C(Figure17)f=66MHz600ps RCOP RxCLK OUT Period(Figure7)15T50ns RCOH RxCLK OUT High Time(Figure7)f=40MHz6ns

f=66MHz 4.35ns RCOL RxCLK OUT Low Time(Figure7)f=40MHz10.5ns

f=66MHz7.09ns RSRC RxOUT Setup to RxCLK OUT(Figure7)f=40MHz 4.5ns

f=66MHz 2.5 4.2ns RHRC RxOUT Hold to RxCLK OUT(Figure7)f=40MHz 6.5ns

f=66MHz4 5.2ns RCCD RxCLK IN to RxCLK OUT Delay@25?C, 6.410.7ns V CC=5.0V(Figure9)

RPLLS Receiver Phase Lock Loop Set(Figure11)10ms RPDD Receiver Power Down Delay(Figure11)1μs

Note7:Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs.This margin takes into account transmitter output skew(TCCS) and the setup and hold time(internal data sampling window),allowing for LVDS cable skew dependent on type/length and source clock(TxCLK IN)jitter.

RSKM≥cable skew(type,length)+source clock jitter(cycle to cycle)

AC Timing Diagrams

DS012889-2

FIGURE1.“WORST CASE”Test Pattern

DS012889-3

DS012889-4 FIGURE2.DS90CR283(Transmitter)LVDS Output Load and Transition Timing

DS012889-5

DS012889-6 FIGURE3.DS90CR284(Receiver)CMOS/TTL Output Load and Transition Timing

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AC Timing Diagrams(Continued)

DS012889-7

FIGURE4.DS90CR283(Transmitter)Input Clock Transition Time

DS012889-8 Note8:Measurements at V diff=0V

Note9:TCCS measured between earliest and latest initial LVDS edges.

Note10:TxCLK OUT Differential Low→High Edge

FIGURE5.DS90CR283(Transmitter)Channel-to-Channel Skew

DS012889-9

FIGURE6.DS90CR283(Transmitter)Setup/Hold and High/Low Times

DS012889-10

FIGURE7.DS90CR284(Receiver)Setup/Hold and High/Low Times https://www.wendangku.net/doc/c77342038.html,6

AC Timing Diagrams(Continued)

DS012889-11

FIGURE8.DS90CR283(Transmitter)Clock In to Clock Out Delay

DS012889-12

FIGURE9.DS90CR284(Receiver)Clock In to Clock Out Delay

DS012889-13

FIGURE10.DS90CR283(Transmitter)Phase Lock Loop Set Time

DS012889-14

FIGURE11.DS90CR284(Receiver)Phase Lock Loop Set Time

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AC Timing Diagrams(Continued)

DS012889-15

FIGURE12.Seven Bits of LVDS in One Clock Cycle

DS012889-16 FIGURE13.28Parallel TTL Data Inputs Mapped to LVDS Outputs(DS90CR283)

DS012889-17

FIGURE14.Transmitter Powerdown Delay

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AC Timing Diagrams(Continued)

DS012889-19

FIGURE16.Transmitter LVDS Output Pulse Position Measurement

DS012889-20

SW—Setup and Hold Time(Internal data sampling window)

TCCS—Transmitter Output Skew

RSKM≥Cable Skew(type,length)+Source Clock Jitter(cycle to cycle)

Cable Skew—typically10ps–40ps per foot.

FIGURE17.Receiver LVDS Input Skew Margin

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DS90CR283Pin Description—Channel Link Transmitter

Pin Name I/O No.Description

TxIN I28TTL Level inputs

TxOUT+O4Positive LVDS differential data output

TxOUT?O4Negative LVDS differential data output

TxCLK IN I1TTL level clock input.The rising edge acts as data strobe

TxCLK OUT+O1Positive LVDS differential clock output

TxCLK OUT?O1Negative LVDS differential clock output

PWR DOWN I1TTL level input.Assertion(low input)TRI-STATES the outputs,ensuring low current at power

down

V CC I4Power supply pins for TTL inputs

GND I5Ground pins for TTL inputs

PLL V CC I1Power supply pin for PLL

PLL GND I2Ground pins for PLL

LVDS V CC I1Power supply pin for LVDS outputs

LVDS GND I3Ground pins for LVDS outputs

DS90CR284Pin Description—Channel Link Receiver

Pin Name I/O No.Description

RxIN+I4Positive LVDS differential data inputs

RxIN?I4Negative LVDS differential data inputs

RxOUT O28TTL level outputs

RxCLK IN+I1Positive LVDS differential clock input

RxCLK IN?I1Negative LVDS differential clock input

RxCLK OUT O1TTL level clock output.The rising edge acts as data strobe

PWR DOWN I1TTL level input.Assertion(low input)maintains the receiver outputs in the previous state

V CC I4Power supply pins for TTL outputs

GND I5Ground pins for TTL outputs

PLL V CC I1Power supply for PLL

PLL GND I2Ground pin for PLL

LVDS V CC I1Power supply pin for LVDS inputs

LVDS GND I3Ground pins for LVDS inputs

Applications Information

The Channel Link devices are intended to be used in a wide

variety of data transmission applications.Depending upon

the application the interconnecting media may vary.For ex-

ample,for lower data rate(clock rate)and shorter cable

lengths(<2m),the media electrical performance is less criti-cal.For higher speed/long distance applications the media’s

performance becomes more critical.Certain cable construc-

tions provide tighter skew(matched electrical length be-

tween the conductors and pairs).Twin-coax for example,has

been demonstrated at distances as great as5meters and

with the maximum data transfer of1.848Gbit/s.Additional

applications information can be found in the following Na-

tional Interface Application Notes:

AN=####Topic

AN-1041Introduction to Channel Link

AN-1035PCB Design Guidelines for LVDS and

Link Devices

AN-806Transmission Line Theory

AN=####Topic

AN-905Transmission Line Calculations and

Differential Impedance

AN-916Cable Information

CABLES:A cable interface between the transmitter and re-ceiver needs to support the differential LVDS pairs.The 21-bit CHANNEL LINK chipset(DS90CR213/214)requires four pairs of signal wires and the28-bit CHANNEL LINK chipset(DS90CR283/284)requires five pairs of signal wires. The ideal cable/connector interface would have a constant 100?differential impedance throughout the path.It is also recommended that cable skew remain below350ps(@66 MHz clock rate)to maintain a sufficient data sampling win-dow at the receiver.

In addition to the four or five cable pairs that carry data and clock,it is recommended to provide at least one additional conductor(or pair)which connects ground between the transmitter and receiver.This low impedance ground pro-vides a common mode return path for the two devices.Some of the more commonly used cable types for point-to-point ap-

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Applications Information(Continued) plications include flat ribbon,flex,twisted pair and Twin-Coax.All are available in a variety of configurations and options.Flat ribbon cable,flex and twisted pair generally per-form well in short point-to-point applications while Twin-Coax is good for short and long applications.When using ribbon cable,it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling be-tween adjacent pairs.For Twin-Coax cable applications,it is recommended to utilize a shield on each cable pair.All ex-tended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type.This overall shield results in improved transmis-sion parameters such as faster attainable speeds,longer distances between transmitter and receiver and reduced problems associated with EMS or EMI.

The high-speed transport of LVDS signals has been demon-strated on several types of cables with excellent results. However,the best overall performance has been seen when using Twin-Coax cable.Twin-Coax has very low cable skew and EMI due to its construction and double shielding.All of the design considerations discussed here and listed in the supplemental application notes provide the subsystem com-munications designer with many useful guidelines.It is rec-ommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution.

BOARD LAYOUT:To obtain the maximum benefit from the noise and EMI reductions of LVDS,attention should be paid to the layout of differential lines.Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise can-celing of the differential signals.The board designer should also try to maintain equal length on signal traces for a given differential pair.As with any high speed design,the imped-ance discontinuities should be limited(reduce the numbers of vias and no90degree angles on traces).Any discontinui-ties which do occur on one signal line should be mirrored in the other line of the differential pair.Care should be taken to ensure that the differential trace impedance match the differ-ential impedance of the selected physical media(this imped-ance should also match the value of the termination resistor that is connected across the differential pair at the receiver’s input).Finally,the location of the CHANNEL LINK TxOUT/ RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs.All of these consider-ations will limit reflections and crosstalk which adversely ef-fect high frequency performance and EMI.

UNUSED INPUTS:All unused inputs at the TxIN inputs of the transmitter must be tied to ground.All unused outputs at the RxOUT outputs of the receiver must then be left floating. TERMINATION:Use of current mode drivers requires a ter-minating resistor across the receiver inputs.The CHANNEL LINK chipset will normally require a single100?resistor be-tween the true and complement lines on each differential pair of the receiver input.The actual value of the termination resistor should be selected to match the differential mode characteristic impedance(90?to120?typical)of the cable. Figure18shows an example.No additional pull-up or pull-down resistors are necessary as with some other differ-ential technologies such as PECL.Surface mount resistors are recommended to avoid the additional inductance that ac-companies leaded resistors.These resistors should be placed as close as possible to the receiver input pins to re-duce stubs and effectively terminate the differential lines. DECOUPLING CAPACITORS:Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance.For a conservative approach three parallel-connected decoupling capacitors(Multi-Layered Ce-ramic type in surface mount form factor)between each V CC and the ground plane(s)are recommended.The three ca-pacitor values are0.1μF,0.01μF and0.001μF.An example is shown in Figure19.The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane.If board space is limiting the number of bypass capacitors,the PLL V CC should receive the most filtering/bypassing.Next would be the LVDS V CC pins and finally the logic V CC pins.

DS012889-24

FIGURE18.LVDS Serialized Link Termination

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Applications Information

(Continued)

CLOCK JITTER:The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface.The width of each bit in the serialized LVDS data stream is one-seventh the clock period.For example,a 66MHz clock has a period of 15ns which results in a data bit width of 2.16ns.Differential skew (?t within one differential pair),interconnect skew (?t of one differential pair to an-other)and clock jitter will all reduce the available window for sampling the LVDS serial data streams.Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal.Individual bypassing of each V CC to ground will minimize the noise passed on to the PLL,thus creating a

low jitter LVDS clock.These measures provide more margin for channel-to-channel skew and interconnect skew as a part of the overall jitter/skew budget.

COMMON MODE vs.DIFFERENTIAL MODE NOISE MAR-GIN:The typical signal swing for LVDS is 300mV centered at +1.2V.The CHANNEL LINK receiver supports a 100mV threshold therefore providing approximately 200mV of differ-ential noise https://www.wendangku.net/doc/c77342038.html,mon mode protection is of more im-portance to the system’s operation due to the differential data transmission.LVDS supports an input voltage range of Ground to +2.4V.This allows for a ±1.0V shifting of the cen-ter point due to ground potential differences and common mode noise.

POWER SEQUENCING AND POWERDOWN MODE:Out-puts of the CHANNEL LINK transmitter remain in TRI-STATE until the power supply reaches 3V.Clock and data outputs will begin to toggle 10ms after V CC has reached 4.5V and the Powerdown pin is above 2V.Either device may be placed into a powerdown mode at any time by asserting the Power-down pin (active low).Total power dissipation for each de-vice will decrease to 5μW (typical).

The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or re-ceiver.If power to the transmit board is lost,the receiver clocks (input and output)stop.The data outputs (RxOUT)re-tain the states they were in when the clocks stopped.When the receiver board loses power,the receiver inputs are shorted to V CC through an internal diode.Current is limited (5mA per input)by the fixed current mode drivers,thus avoiding the potential for latchup when powering the device.

DS012889-25

FIGURE 19.CHANNEL LINK Decoupling Configuration DS012889-26

FIGURE 20.Single-Ended and Differential Waveforms

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Physical Dimensions inches(millimeters)unless otherwise noted

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be reasonably expected to result in a significant injury

to the user.

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device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system,or to affect its safety or effectiveness.

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56-Lead Molded Thin Shrink Small Outline Package,JEDEC

Order Number DS90CR283MTD or DS90CR284MTD

NS Package Number MTD56

National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.