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MCP1827T-2502EAB中文资料

MCP1827/MCP1827S

Features

? 1.5A Output Current Capability

?Input Operating Voltage Range: 2.3V to 6.0V ?Adjustable Output Voltage Range: 0.8V to 5.0V (MCP1827 only)

?Standard Fixed Output Voltages:

-0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V ?Other Fixed Output Voltage Options Available Upon Request

?Low Dropout Voltage: 330mV Typical at 1.5A ?Typical Output Voltage Tolerance: 0.5%?Stable with 1.0μF Ceramic Output Capacitor ?Fast response to Load Transients

?Low Supply Current: 120μA (typ)

?Low Shutdown Supply Current: 0.1μA (typ) (MCP1827 only)

?Fixed Delay on Power Good Output

(MCP1827 only)

?Short Circuit Current Limiting and Overtemperature Protection

?5-Lead Plastic DDPAK, 5-Lead TO-220 Package Options (MCP1827)

?3-Lead Plastic DDPAK, 3-Lead TO-220 Package Options (MCP1827S)

Applications

?High-Speed Driver Chipset Power ?Networking Backplane Cards

?Notebook Computers

?Network Interface Cards

?Palmtop Computers

? 2.5V to 1.XV Regulators Description

The MCP1827/MCP1827S is a 1.5A Low Dropout (LDO) linear regulator that provides high current and low output voltages. The MCP1827 comes in a fixed or adjustable output voltage version, with an output voltage range of 0.8V to 5.0V. The 1.5A output current capability, combined with the low output voltage capability, make the MCP1827 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. The MCP1827S is a 3-pin fixed voltage version. The MCP1827/MCP1827S is based upon the MCP1727 LDO device.

The MCP1827/MCP1827S is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1μF of output capacitance is needed to stabilize the LDO.

Using CMOS construction, the quiescent current consumed by the MCP1827/MCP1827S is typically less than 120μA over the entire input voltage range, making it attractive for portable computing applications that demand high output current. The MCP1827 versions have a Shutdown (SHDN) pin. When shut down, the quiescent current is reduced to less than 0.1μA.

On the MCP1827 fixed output versions the scaled-down output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). The PWRGD delay is internally fixed at 200μs (typical). The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions.

Package Types

Fixed/Adjustable3-LD DDPAK

5-LD DDPAK

3-LD TO-220

5-LD TO-220

12345

123

V I

(

)

V I

(

)

V I

(

)

V I

(

)

T MCP1827

MCP1827

MCP1827S

1.5A, Low Voltage, Low Quiescent Current LDO Regulator

? 2006 Microchip Technology Inc.DS22001B-page 1

MCP1827/MCP1827S

DS22001B-page 2? 2006 Microchip Technology Inc.

Typical Application

MCP1827 Adjustable Output Voltage

MCP1827 Fixed Output Voltage

V OUT = 1.8V @ 1A V IN = 2.3V to 2.8V

On Off

1μF

100k Ω

4.7μF

C 1C 2R 1SHDN V IN

GND

V OUT

PWRGD

20k Ω

R 2VADJ

12345

V OUT = 1.2V @ 1A V IN = 2.3V to 2.8V

On Off

1μF

40k Ω

4.7μF

C 1C 2R 1SHDN V IN

GND

V OUT

12345

? 2006 Microchip Technology Inc.DS22001B-page 3

MCP1827/MCP1827S

Functional Block Diagram - Adjustable Output

+–

V OUT

PMOS

R f

C f I SNS

Overtemperature

V REF

Comp

92% of V REF

T DELAY

V IN

Driver w/limit and SHDN

GND

Soft-Start

ADJ

Undervoltage Lock Out V IN

Reference

SHDN

SHDN SHDN Sensing

(UVLO)

MCP1827/MCP1827S

DS22001B-page 4? 2006 Microchip Technology Inc.

Functional Block Diagram - Fixed Output (5 pin)

+–

V OUT

PMOS

R f

C f

I SNS

V REF

Comp

92% of V REF

T DELAY

V IN

GND

Soft-Start

Sense

V IN

Reference

SHDN

SHDN SHDN PWRGD

Overtemperature

Driver w/limit and SHDN

Undervoltage Lock Out Sensing

(UVLO)

? 2006 Microchip Technology Inc.DS22001B-page 5

MCP1827/MCP1827S

Functional Block Diagram - Fixed Output (3-Pin)

+–

V OUT

PMOS

R f

C f

I SNS

V REF

Comp

92% of V REF

T DELAY

V IN

GND

Soft-Start

Sense

V IN

Reference

SHDN

SHDN SHDN Overtemperature

Driver w/limit and SHDN

Undervoltage Lock Out Sensing

(UVLO)

MCP1827/MCP1827S

DS22001B-page 6? 2006 Microchip Technology Inc.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings ?

V IN ....................................................................................6.5V Maximum Voltage on Any Pin..(GND – 0.3V) to (V DD + 0.3)V Maximum Power Dissipation.........Internally-Limited (Note 6)Output Short Circuit Duration................................Continuous Storage temperature .....................................-65°C to +150°C Maximum Junction Temperature, T J ...........................+150°C ESD protection on all pins (HBM/MM)........... ≥2kV;≥ 200V

? Notice: Stresses above those listed under “Maximum Rat-ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo-sure to maximum rating conditions for extended periods may affect device reliability.

AC/DC CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, V IN = V OUT(MAX) + V DROPOUT(MAX) Note 1, V R =1.8V for Adjustable Output, I OUT = 1mA, C IN = C OUT = 4.7μF (X7R Ceramic), T A = +25°C. Boldface type applies for junction temperatures, T J (Note 7) of -40°C to +125°C

Parameters

Sym Min Typ

Max Units Conditions

Input Operating Voltage V IN 2.3 6.0V Note 1

Input Quiescent Current I q

—120220μA I L = 0mA, V IN = Note 1,V OUT = 0.8V to 5.0V Input Quiescent Current for SHDN Mode

I SHDN —0.13μA SHDN = GND

Maximum Output Current I OUT 1.5——A V IN = 2.3V to 6.0V

V R = 0.8V to 5.0V, Note 1Line Regulation ΔV OUT /(V OUT x ΔV IN )—0.050.16%/V (Note 1) ≤ V IN ≤ 6V Load Regulation

ΔV OUT /V OUT -1.0±0.5 1.0%I OUT = 1mA to 1.5A,V IN = Note 1, (Note 4)Output Short Circuit Current

I OUT_SC

—

2.2—

V IN = Note 1, R LOAD <0.1Ω, Peak Current

Adjust Pin Characteristics (Adjustable Output Only)Adjust Pin Reference Voltage V ADJ 0.4020.4100.418V V IN = 2.3V to V IN =6.0V,I OUT = 1mA

Adjust Pin Leakage Current I ADJ -10±0.01+10nA V IN = 6.0V, V ADJ =0V to 6V Adjust Temperature Coefficient TCV OUT

—

ppm/°C

Note 3

Fixed-Output Characteristics (Fixed Output Only)

Note 1:

The minimum V IN must meet two conditions: V IN ≥ 2.3V and V IN ≥ V OUT(MAX) + V DROPOUT(MAX).

V R is the nominal regulator output voltage for the fixed cases. V R = 1.2V, 1.8V, etc. V R is the desired set point output voltage for the adjustable cases. V R = V ADJ * ((R 1/R 2)+1). Figure 4-1.

3:TCV OUT = (V OUT-HIGH – V OUT-LOW ) *106 / (V R * ΔTemperature). V OUT-HIGH is the highest voltage measured over the temperature range. V OUT-LOW is the lowest voltage measured over the temperature range.

4:Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current.

5:Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of V IN = V OUTMAX + V DROPOUT(MAX).

The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction

temperature and the thermal resistance from junction to air. (i.e., T A , T J , θJA ). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability.

The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.

? 2006 Microchip Technology Inc.DS22001B-page 7

MCP1827/MCP1827S

Voltage Regulation V OUT

V R - 2.5%

V R ±0.5%

V R + 2.5%

Note 2

Dropout Characteristics Dropout Voltage

V IN -V OUT

—

330

600

Note 5, I OUT = 1.5A, V IN(MIN)=2.3V

Power Good Characteristics PWRGD Input Voltage Operat-ing Range

V PWRGD_VIN

1.0— 6.0V

T A = +25°C

1.2

—

6.0

T A = -40°C to +125°C For V IN < 2.3V, I SINK =100μA

PWRGD Threshold Voltage (Referenced to V OUT )

V PWRGD_TH

%V OUT

Falling Edge

899295V OUT < 2.5V Fixed, V OUT = Adj.90

9294V OUT >= 2.5V Fixed

PWRGD Threshold Hysteresis V PWRGD_HYS 1.0 2.0 3.0%V OUT

PWRGD Output Voltage Low V PWRGD_L —0.20.4V I PWRGD SINK = 1.2mA,ADJ = 0V

PWRGD Leakage P WRGD _LK

—1—nA V PWRGD = V IN = 6.0V PWRGD Time Delay T PG —200—μs Rising Edge

R PULLUP = 10k Ω

Detect Threshold to PWRGD Active Time Delay T VDET-PWRGD

—

200

—

μs

V ADJ or V OUT = V PWRGD_TH + 20mV to V PWRGD_TH - 20mV

Shutdown Input Logic High Input V SHDN-HIGH 45

%V IN V IN = 2.3V to 6.0V Logic Low Input

V SHDN-LOW 15%V IN V IN = 2.3V to 6.0V SHDN Input Leakage Current SHDN ILK

-0.1

±0.001

+0.1

μA

V IN =6V, SHDN =V IN ,SHDN = GND

AC Performance Output Delay From SHDN T OR 100μs SHDN = GND to V IN V OUT = GND to 95% V R Output Noise

e N

—

2.0

—

μV/√Hz

I OUT = 200mA, f = 1kHz, C OUT = 10μF (X7R Ceramic), V OUT = 2.5V

AC/DC CHARACTERISTICS (CONTINUED)

Parameters

Sym Min Typ Max Units Conditions

Note 1:

The minimum V IN must meet two conditions: V IN ≥ 2.3V and V IN ≥ V OUT(MAX) + V DROPOUT(MAX).

V R is the nominal regulator output voltage for the fixed cases. V R = 1.2V, 1.8V, etc. V R is the desired set point output voltage for the adjustable cases. V R = V ADJ * ((R 1/R 2)+1). Figure 4-1.

4:Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current.

The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction

MCP1827/MCP1827S

DS22001B-page 8? 2006 Microchip Technology Inc.

TEMPERATURE SPECIFICATIONS

Power Supply Ripple Rejection Ratio

PSRR

—

f = 100Hz, C OUT = 10μF,I OUT = 10mA,

V INAC = 30mV pk-pk,C IN = 0μF

Thermal Shutdown Temperature T SD —150—°C I OUT = 100μA, V OUT = 1.8V, V IN = 2.8V

Thermal Shutdown Hysteresis ΔT SD

—

°C

I OUT = 100μA, V OUT = 1.8V, V IN = 2.8V

Electrical Specifications: Unless otherwise indicated, all limits apply for V IN = 2.3V to 6.0V.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Operating Junction Temperature Range T J -40—+125°C Steady State Maximum Junction Temperature T J ——+150°C Transient

Storage Temperature Range T A

-65

—

+150

°C

Thermal Package Resistances Thermal Resistance, 5LD DDPAK θJA —31.2—°C/W 4-Layer JC51 Standard Board Thermal Resistance, 3LD DDPAK θJA —31.4—°C/W 4-Layer JC51 Standard Board Thermal Resistance, 5LD TO-220θJA —29.3—°C/W 4-Layer JC51 Standard Board Thermal Resistance, 3LD TO-220

θJA

—

29.4

—

°C/W

4-Layer JC51 Standard Board

AC/DC CHARACTERISTICS (CONTINUED)

Parameters

Sym Min Typ Max Units Conditions

Note 1:

The minimum V IN must meet two conditions: V IN ≥ 2.3V and V IN ≥ V OUT(MAX) + V DROPOUT(MAX).

V R is the nominal regulator output voltage for the fixed cases. V R = 1.2V, 1.8V, etc. V R is the desired set point output voltage for the adjustable cases. V R = V ADJ * ((R 1/R 2)+1). Figure 4-1.

4:Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1mA to the maximum specified output current.

The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction

MCP1827/MCP1827S 2.0TYPICAL PERFORMANCE CURVES

NOTE: Unless otherwise indicated, V IN = V OUT + 0.6V, I OUT = 1mA and T A = +25°C.

FIGURE 2-1:Quiescent Current vs. Input Voltage (1.2V Adjustable).

FIGURE 2-2:Ground Current vs. Load Current (1.2V Adjustable).

FIGURE 2-3:Quiescent Current vs. Junction Temperature (1.2V Adjustable).FIGURE 2-4:Line Regulation vs. Temperature (1.2V Adjustable).

FIGURE 2-5:Load Regulation vs. Temperature (Adjstable Version). FIGURE 2-6:Adjust Pin Voltage vs. Temperature.

Note:The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

? 2006 Microchip Technology Inc.DS22001B-page 9

MCP1827/MCP1827S

DS22001B-page 10? 2006 Microchip Technology Inc.

NOTE: Unless otherwise indicated, V IN = V OUT + 0.6V, I OUT = 1mA and T A = +25°C.

FIGURE 2-7:Dropout Voltage vs. Load Current (Adjustable Version).

FIGURE 2-8:Dropout Voltage vs. Temperature (Adjustable Version).

FIGURE 2-9:Power Good (PWRGD) Time Delay vs. Temperature (Adjustable Version).

FIGURE 2-10:Quiescent Current vs. Input Voltage (0.8V Fixed).

FIGURE 2-11:Quiescent Current vs. Input Voltage (2.5V Fixed).

FIGURE 2-12:Ground Current vs. Load

Current.

MCP1827/MCP1827S NOTE: Unless otherwise indicated, V IN = V OUT + 0.6V, I OUT = 1mA and T A = +25°C.

FIGURE 2-13:Quiescent Current vs. Temperature.

FIGURE 2-14:I SHDN vs. Temperature. FIGURE 2-15:Line Regulation vs. Temperature (0.8V Fixed).FIGURE 2-16:Line Regulation vs. Temperature (2.5V Fixed).

FIGURE 2-17:Load Regulation vs. Temperature (V OUT < 2.5V Fixed). FIGURE 2-18:Load Regulation vs. Temperature (V OUT≥ 2.5V Fixed).

? 2006 Microchip Technology Inc.DS22001B-page 11

MCP1827/MCP1827S

DS22001B-page 12? 2006 Microchip Technology Inc.

NOTE: Unless otherwise indicated, V IN = V OUT + 0.6V, I OUT = 1mA and T A = +25°C.

FIGURE 2-19:Dropout Voltage vs. Load

Current.

FIGURE 2-20:Dropout Voltage vs.

Temperature.

FIGURE 2-21:Short Circuit Current vs.

Input Voltage.

FIGURE 2-22:Output Noise Voltage Density vs. Frequency.

FIGURE 2-23:Power Supply Ripple

Rejection (PSRR) vs. Frequency (V OUT = 1.2V Adj.).

FIGURE 2-24:Power Supply Ripple

Rejection (PSRR) vs. Frequency (V OUT = 1.2V Adj.).

MCP1827/MCP1827S NOTE: Unless otherwise indicated, V IN = V OUT + 0.6V, I OUT = 1mA and T A = +25°C.

FIGURE 2-25:Power Supply Ripple Rejection (PSRR) vs. Frequency (V OUT = 3.3V Fixed).

FIGURE 2-26:Power Supply Ripple Rejection (PSRR) vs. Frequency (V OUT = 3.3V Fixed).

FIGURE 2-27: 2.5V (Adj.) Startup from V IN.FIGURE 2-28: 2.5V (Adj.) Startup from Shutdown.

FIGURE 2-29:Power Good (PWRGD) Timing.

FIGURE 2-30:Dynamic Line Response (3.3V Fixed).

? 2006 Microchip Technology Inc.DS22001B-page 13

MCP1827/MCP1827S

DS22001B-page 14? 2006 Microchip Technology Inc.

NOTE: Unless otherwise indicated, V IN = V OUT + 0.6V, I OUT = 1mA and T A = +25°C.

FIGURE 2-31:Dynamic Load Response (3.3V Fixed, 10mA to 1500mA).FIGURE 2-32:Dynamic Load Response (3.3V Fixed, 100mA to 1500

mA).

MCP1827/MCP1827S

3.0PIN DESCRIPTION

The descriptions of the pins are listed in Table3-1.

TABLE 3-1:PIN FUNCTION TABLE

3.1Input Voltage Supply (V IN)

Connect the unregulated or regulated input voltage source to V IN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1μF to 10μF should be sufficient for most applications.

3.2Shutdown Control Input (SHDN) The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1μA.

3.3Ground (GND)

Connect the GND pin of the LDO to a quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the quiescent current of the LDO (typically 120μA), so a heavy trace is not required. For applications have switching or noisy inputs tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients.3.4Power Good Output (PWRGD)

The PWRGD output is an open-drain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD threshold has a typical hysteresis value of 2%. The PWRGD output is delayed by 200μs (typical) from the time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. This delay time is internally fixed.

3.5Output Voltage Adjust Input (ADJ) For adjustable applications, the output voltage is connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This provides the user the capability to set the output voltage to any value they desire within the 0.8V to 5.0V range of the device.

3.6Regulated Output Voltage (V OUT) The V OUT pin is the regulated output voltage of the LDO. A minimum output capacitance of 1.0μF is required for LDO stability. The MCP1827/MCP1827S is stable with ceramic, tantalum and aluminum-electro-lytic capacitors. See Section

4.3 “Output Capacitor”for output capacitor selection guidance.

3.7Exposed Pad (EP)

The DDPAK and TO-220 package have an exposed tab on the package. A heat sink may be mount to the tab to aid in the removal of heat from the package during operation. The exposed tab is at the ground potential of the LDO.

3-Pin Fixed Output 5-Pin Fixed

Output

Adjustable

Output

Name Description

—11SHDN Shutdown Control Input (active-low)

122V IN Input Voltage Supply

233GND Ground

344V OUT Regulated Output Voltage

—5—PWRGD Power Good Output

——5ADJ Voltage Adjust/Sense Input

Pad Pad Pad EP Exposed Pad of the Package (ground potential)

? 2006 Microchip Technology Inc.DS22001B-page 15

MCP1827/MCP1827S

DS22001B-page 16? 2006 Microchip Technology Inc.

4.0

DEVICE OVERVIEW

The MCP1827/MCP1827S is a high output current,

Low Dropout (LDO) voltage regulator. The low dropout voltage of 330mV typical at 1.5A of current makes it ideal for battery-powered applications. Unlike other high output current LDOs, the MCP1827/MCP1827S only draws a maximum of 220μA of quiescent current.

The MCP1827 has a shutdown control input and a power good output.

4.1LDO Output Voltage

The 5-pin MCP1827 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for both versions.The 3-pin MCP1827S LDO is available as a fixed voltage device.

4.1.1ADJUST INPUT

The adjustable version of the MCP1827 uses the ADJ pin (pin 5) to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors.The nominal voltage for ADJ is 0.41V.

Figure 4-1 shows the adjustable version of the MCP1827. Resistors R 1 and R 2 form the resistor divider network necessary to set the output voltage.With this configuration, the equation for setting V OUT is:

EQUATION 4-1:

FIGURE 4-1:Typical adjustable output voltage application circuit.

The allowable resistance value range for resistor R 2 is from 10k Ω to 200k Ω. Solving the equation for R 1yields the following equation:

EQUATION 4-2:

4.2

Output Current and Current Limiting

The MCP1827/MCP1827S LDO is tested and ensured to supply a minimum of 1.5A of output current. The MCP1827/MCP1827S has no minimum output load, so the output load current can go to 0mA and the LDO will continue to regulate the output voltage to within tolerance.

The MCP1827/MCP1827S also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 2.2A (typical). If the overload condition is a soft overload, the MCP1827/MCP1827S will supply higher load currents of up to 3A. The MCP1827/MCP1827S should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 1.5A or less.

Output overload conditions may also result in an over-temperature shutdown of the device. If the junction temperature rises above 150°C, the LDO will shut down the output voltage. See Section 4.8 “Overtem-perature Protection” for more information on overtemperature shutdown.

4.3

Output Capacitor

The MCP1827/MCP1827S requires a minimum output capacitance of 1μF for output voltage stability. Ceramic capacitors are recommended because of their size,cost and environmental robustness qualities.

Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1μF X7R 0805 capacitor has an ESR of 50 milli-ohms.

Larger LDO output capacitors can be used with the MCP1827/MCP1827S to improve dynamic performance and power supply ripple rejection performance. A maximum of 22μF is recommended.Aluminum-electrolytic capacitors are not recom-mended for low-temperature applications of < -25°C.

V OUT

V ADJ R 1R 2

+R 2------------------??

=Where:V OUT =

LDO Output Voltage

V ADJ

=ADJ Pin

Voltage

(typically 0.41V)

SHDN

GND

ADJ

21μF

V OUT

4.7μF

V IN On Off

R 1

R 2

C 1C2MCP1827-ADJ

1345

R 1R 2V OUT V ADJ

–V ADJ --------------------------------????

=Where:V OUT =

LDO Output Voltage

V ADJ

=ADJ Pin

Voltage

(typically 0.41V)

MCP1827/MCP1827S

4.4Input Capacitor

Low input source impedance is necessary for the LDO

output to operate properly. When operating from

batteries, or in applications with long lead length

(> 10 inches) between the input source and the LDO,

some input capacitance is recommended. A minimum

of 1.0μF to 4.7μF is recommended for most

applications.

For applications that have output step load

requirements, the input capacitance of the LDO is very

important. The input capacitance provides the LDO

with a good local low-impedance source to pull the

transient currents from in order to respond quickly to

the output load step. For good step response

performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO.

4.5Power Good Output (PWRGD)

The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation value.

As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as T PG in the Electrical Characteristics table). The power good time delay is fixed at 200μs (typical). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 170μs delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure4-2 for power good timing characteristics.

When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure4-3.

The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2mA (V PWRGD < 0.4V maximum). FIGURE 4-2:Power Good Timing. FIGURE 4-3:Power Good Timing from

Shutdown.

4.6Shutdown Input (SHDN)

The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of V IN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400ns in pulse width. If the shutdown input is pulled low for more than 400ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal.

On the rising edge of the SHDN input, the shutdown circuitry has a 30μs delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After

T PG

T VDET_PWRGD V PWRGD_TH

V OUT

PWRGD

V OL

V OH

V IN

SHDN

V OUT

30μs

70μs

T OR

PWRGD

T PG

? 2006 Microchip Technology Inc.DS22001B-page 17

MCP1827/MCP1827S

DS22001B-page 18? 2006 Microchip Technology Inc.

the 30μs delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30μs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the LDO output being in regulation is typically 100μs. See Figure 4-4 for a timing diagram of the SHDN input.

FIGURE 4-4:Shutdown Input Timing

Diagram.

4.7

Dropout Voltage and Undervoltage Lockout

Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a V R + 0.6V differential applied. The MCP1827/MCP1827S LDO has a very low dropout voltage specification of 330mV (typical) at 1.5A of output current. See Section 1.0 “Electrical Characteristics”for maximum dropout voltage specifications.

The MCP1827/MCP1827S LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 2.04V (typical).

Since the MCP1827/MCP1827S LDO undervoltage lockout activates at 2.04V as the input voltage is falling,the dropout voltage specification does not apply for output voltages that are less than 1.9V.

For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout.

4.8Overtemperature Protection

The MCP1827/MCP1827S LDO has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 “Application Circuits/Issues” for more information on LDO power dissipation and junction temperature.

SHDN

V OUT

30μs 70μs

T OR

400ns (typ)

? 2006 Microchip Technology Inc.DS22001B-page 19

MCP1827/MCP1827S

5.0

APPLICATION CIRCUITS/ISSUES

5.1

Typical Application

The MCP1827/MCP1827S is used for applications that require high LDO output current and a power good output.

FIGURE 5-1:Typical Application Circuit.

5.1.1

APPLICATION CONDITIONS

5.2

Power Calculations

5.2.1

POWER DISSIPATION

The internal power dissipation within the MCP1827/MCP1827S is a function of input voltage, output voltage, output current and quiescent current.Equation 5-1 can be used to calculate the internal power dissipation for the LDO.

EQUATION 5-1:

In addition to the LDO pass element power dissipation,there is power dissipation within the MCP1827/MCP1827S as a result of quiescent or ground current.The power dissipation as a result of the ground current can be calculated using the following equation:

EQUATION 5-2:

The total power dissipated within the MCP1827/MCP1827S is the sum of the power dissipated in the LDO pass device and the P(I GND ) term. Because of the CMOS construction, the typical I GND for the MCP1827/MCP1827S is 120μA. Operating at a maximum of 3.465V results in a power dissipation of 0.49milli-Watts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected.

The maximum continuous operating junction temperature specified for the MCP1827/MCP1827S is +125°C . To estimate the internal junction temperature of the MCP1827/MCP1827S, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (R θJA ) of the device. The thermal resistance from junction to ambient for the TO-220-5package is estimated at 29.3°C/W.

EQUATION 5-3:

Package Type =TO-220-5

Input Voltage Range = 3.3V ± 5%

V IN maximum = 3.465V V IN minimum = 3.135V V DROPOUT (max) =0.550V V OUT (typical) = 2.5V

I OUT = 1.5A maximum

P DISS (typical) = 1.2W Temperature Rise =35.2°C

10μF

V OUT = 2.5V @ 1.5A

R 1C 210k Ω

PWRGD

SHDN GND

24.7μF

On Off

C 1MCP1827-2.5

1345

3.3V

V IN P LDO V IN MAX )()V OUT MIN ()–()I OUT MAX )()×=Where:

P LDO =LDO Pass device internal power dissipation V IN(MAX)=Maximum input voltage V OUT(MIN)

LDO minimum output voltage

P I GND ()V IN MAX ()I VIN

×=Where:

P I(GND =Power dissipation due to the quiescent current of the LDO V IN(MAX)

=Maximum input voltage I VIN

Current flowing in the V IN pin with no LDO output current (LDO quiescent current)

T J MAX ()P TOTAL R θJA ×T AMAX

+=T J(MAX)=Maximum continuous junction

temperature P TOTAL =Total device power dissipation R θJA =Thermal resistance from junction to

ambient T AMAX =Maximum ambient temperature

MCP1827/MCP1827S

DS22001B-page 20? 2006 Microchip Technology Inc.

The maximum power dissipation capability for a package can be calculated given the junction-to-ambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation.

EQUATION 5-4:

EQUATION 5-5:

EQUATION 5-6:

5.3Typical Application

Internal power dissipation, junction temperature rise,junction temperature and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected.

5.3.1

POWER DISSIPATION EXAMPLE

5.3.1.1Device Junction Temperature Rise

The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (R θJA ) is derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is JESD51. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Appli-cation” (DS00792), for more information regarding this subject.

P D MAX ()

T J MAX ()T A MAX ()–()R θJA

---------------------------------------------------=P D(MAX)=Maximum device power dissipation T J(MAX)=maximum continuous junction temperature T A(MAX)=maximum ambient temperature R θJA =Thermal resistance from junction to

ambient

T J RISE ()P D MAX ()R θJA

×=T J(RISE)=Rise in device junction temperature

over the ambient temperature P D(MAX)=Maximum device power dissipation R θJA =Thermal resistance from junction to

ambient

T J T J RISE ()T A

+=T J =Junction temperature

T J(RISE)=Rise in device junction temperature

over the ambient temperature

T A =Ambient temperature

Package

Package Type =TO-220-5Input Voltage

V IN = 3.3V ± 5%

LDO Output Voltage and Current

V OUT = 2.5V I OUT = 1.5A

Maximum Ambient Temperature T A(MAX)

=60°C

Internal Power Dissipation

P LDO(MAX) =(V IN(MAX) – V OUT(MIN)) x I OUT(MAX)

P LDO =((3.3V x 1.05) – (2.5V x 0.975)) x 1.5A P LDO =1.54 Watts

T J(RISE) =P TOTAL x R θJA T JRISE = 1.54 W x 29.3° C/W T JRISE =45.12°C