UG7128D6688LQ-DZ中文资料
P r e i n a r y
I A L
1
Re-Tek- 979
support@https://www.wendangku.net/doc/c79732857.html, https://www.wendangku.net/doc/c79732857.html,,
45388 Warm Springs Blvd. Fremont, CA. 94539TEL: (510) 668-2088 FAX: (510)661-2788Customer Comment Line: 1-800-826-0808
SYNCHRONOUS DRAM MODULE
1G Bytes (128M x 64 bits)
based on 16 pcs 64M x 8 DDR SDRAM 8K Refresh
184 Pin DDR SDRAM Unbuffered DIMM
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2 DQ0
3 V SS
4 DQ1
5 DQS0
6 DQ2
7 V DD
8 DQ3
9 NC 10 NC 11 V SS 12 DQ813 DQ914 DQS115 VDDQ 16 CK11 V REF 52 BA147 NC 48 A049 NC 50 V SS 51 NC 53 DQ3254 VDDQ 55 DQ3356 DQS457 DQ3458 V SS 59 BA060 DQ3561 DQ4062 VDDQ 93 V SS 104 VDDQ 94 DQ495 DQ596 VDDQ 98 DQ699 DQ7100 V SS 101 NC 102 NC 103 NC 105 DQ12106 DQ13108 V DD 144 NC 139 V SS 141 A10142 NC 143 VDDQ 145 V SS 146 DQ36147 DQ37148 V DD
150 DQ38151 DQ39152 V SS 153 DQ44154 /RAS FEATURES
ABSOLUTE MAXIMUM RATINGS
REVISION HISTORY
Rev - A Product brief released.
May 14 , 2002
? Voltage Relative to GND -0.5 to + 4.6V ? Operating Temperature 0 to + 70°C ? Storage Temperature -55°C to + 150°C ? Short circuit Output Current 50mA ? Power Dissipation 16W
REF. CYCLE
SDRAM PACKAGE PLATING UG7128D6688LQ
8K
400mil TSOP
Gold
PART IDENTIFICATION
PART NO.? 1GB (128Meg X 64)
? Quad internal banks operation
? Auto & self refresh capability (64ms/8K)? SSTL_2 compatible inputs and outputs ? 2.5V ± 0.2V for VDDQ & VDD ? Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8)
? Data scramble ;Sequential & Interleave ? Double Data Rate architecture ? Differential clock inputs (CK , /CK)
? Data inputs and DM are synchronized with both edges of DQS
? Data outputs and DQS are synchronized with a cross point of CK and /CK
? Serial presence detect with EEPROM
? PCB : Height (1250mil), double sided component
97 DM0/DQS9107 DM1/DQS10140 DM8149 DM4/DQS13-EB CL2 10ns 100MHz SPEED INFORMATION
Module Marking CAS Latency SPEED
-EZ CL2 7.5ns 133MHz -DB CL2.5 10ns 100MHz -DZ CL2.5 7.5ns 133MHz
2
Re-Tek- 979
support@https://www.wendangku.net/doc/c79732857.html, https://www.wendangku.net/doc/c79732857.html,,
45388 Warm Springs Blvd. Fremont, CA. 94539TEL: (510) 668-2088 FAX: (510)661-2788
Customer Comment Line: 1-800-826-0808
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i n y
O N F I D E N T I A L
Physical Dimension
Functional Block Diagram
A0 - A12
A0-A12: SDRAMs D0 - D15CAS: SDRAMs D0 - D15CKE0 CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D15
CKE1CKE: SDRAMs D8 - D15BA0 - BA1BA0-BA1: SDRAMs D0 - D15* Wire per Clock Loading Table/Wiring Diagrams
Notes:
1.DQ-to-I/O wiring is shown as recommended but may be changed.
2.DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3.DQ, DQS, DM/DQS resistors: 22 Ohms ± 5%.
A0Serial PD
A1A2SA0
SA1
SA2
SCL SDA
WP
V DD
V SS
D0 - D15D0 - D15
V DDQ
D0 - D15D0 - D15V REF V DDSPD
SPD Tolerances : ± 0.005 unless otherwise specified Units : Inches
0.10M C B
A M DQS1