PACNLT101中文资料

Non-Linear High Speed Termination IC

Features

?16 channel, dual rail clamping action in

a single package

?Provides bus termination independent of line impedance or loading conditions

?Uses CAMD’s patented EZterm? technology

?24-pin QSOP package saves board space and eases layout in space critical areas.

?One IC replaces and outperforms up to 32 discrete components.

?Enable pin included

Product Description

CAMD’s non-linear termination IC is specifically de-signed to minimize overshoot/undershoot disturbances caused by impedance mismatch reflections and noise on high-speed transmission lines.

Reflections on high-speed data lines lead to voltage overshoot and undershoot disturbances, which may result in data loss or improper system operation. Resis-tive terminations, when used to terminate these high-speed data lines, increase power consumption and degrade output levels, resulting in reduced noise immu-nity. Clamping-type termination is the best overall solution for applications in which these may be consider-ations.

This highly integrated non-linear termination IC provides very effective termination performance for high-speed data lines under variable loading conditions. The device supports up to 16 terminated lines per package – each of which are clamped to both ground and power supply rail. A typical application may use 4 devices to replace (and outperform) 64 conventional Schottky diode pairs; thus providing significant reductions in component and assembly costs, improvements in manufacturing effi-ciency and reliability, and savings in allocated board area for space-critical designs.Application

?High speed, low voltage buses

L L

Operating Characteristics - V

= 3.3V , Enable = 3.3V, Temperature = –40°C to 85°C

Operating Characteristics - V DD = 2V , Enable = 2V, Temperature = –40°C to 85°C

*These parameters are guaranteed by design and characterization.

Operating Characteristics - V = 2.5V, Enable = 2.5V , Temperature = 27°C

Figure 1. DC I-V Curves for V DD = 2V and V DD = 3.3V

Application Information

Figure 2 shows one method of configuring the printed circuit board such that all 16 terminated signals are easily accessible. The decoupling capacitor should be a high-frequency type, 0.1μF or larger, and placed as close to the IC as possible. This will minimize

the positive overshoot voltage and also reduce EMI emissions. It should be noted that for optimum performance the PACNLT101 termination should be

located as physically close to the receiving IC input as is possible.

Figure 2. Printed Circuit Board with Accessible Configuration for 16 Terminated Signals

05101520253035

4045500

100

200

300

400

500

600

Voltage above V DD (mV)

C u r r e n t (m A )

16

Terminated

Signals

Figure 5. With PACNLT101 Termination

Figure 4. 74AC244 Termination Only

Figure 3. Example Circuit: Single-Driver/Single Receiver

V C1 Rise 1.14ns ?: 2.50V

C1 Fall 1ns C1 Max 3.30V C1 Min –1.20V

C1 Rise 1.18ns ?: 2.50V

C1 Fall 1ns C1 Max 2.82V C1 Min –

500mV

Enable pin

In normal use the Enable pin is connected to V DD .If the Enable pin is set to 0V or disconnected (high impedance), then the PACNLT101 will be disabled. The supply current will drop to almost zero and the clamping performance will be worsened.

The Enable pin can also be used to vary the supply current and clamping voltage. As the current into the Enable pin is increased the supply current will increase and the clamping voltage will be reduced. The minimum clamping voltage will occur when the Enable pin voltage equals the supply voltage. (The Enable pin voltage

cannot exceed the supply voltage.)

Users who cannot tolerate the supply current quoted in the Operating Characteristics can connect a resistor in series with the Enable pin to reduce the supply current,at the cost of increasing the clamping voltage. See Figure 6.

The controller IC sets the powerdown pin to 0V to powerdown the PACNLT101, and sets the powerdown pin to V DD to power up the PACNLT101. The system

designer can vary the value of R1 to optimize the trade-off between power consumption and clamping voltage.See Figure 7, 8, 9, and 10.

Figure 7. I DD vs R1 @ V DD = 3.3V

Figure 6. Resistor In Series with the Enable Pin

01020304050607080901000

100

220

470

1000

2200

Value of External Resistor R1 (?)

I D D (m A )

500

550600650700750800010022047010002200

Value of External Resistor R1 (?)

C l a m p i n g V o l t a g e a b o v e V

D D f o r 50m A (m V )

Figure 8. Clamping Voltage vs R1 @ V DD = 3.3V

Figure 9. I DD vs R1 @ V DD = 2V

Figure 10. Clamping Voltage vs R1 @ V DD = 2V

51015202530

010022047010002200470010000100000

Value of External Resistor R1 (?)

I D D (m A )

300

350400450550500600650

100

220

470

10002200470010000100000

Value of External Resistor R1 (?)

C l a m p i n g V o l t a g e a b o v e V

D D f o r 20m A (m V )