Fault Injection for Logic Synthesis Design using VHDL

Fault Injection for Logic Synthesis Design using VHDL

Todd A. DeLong

Anup K. Ghosh

Barry W. Johnson

Center for Semicustom Integrated Systems

Department of Electrical Engineering

University of Virginia

contact: bwj@https://www.wendangku.net/doc/da3869105.html,

Joseph A. Profeta, III

Union Switch and Signal, Incorporated

Abstract

Fault injection provides a method of assessing the dependability of a system under test. Traditionally fault injection is employed near the end of the design process after hardware and software prototypes have been developed. In order to eliminate costly re-designs near the end of the design process, a methodology for performing fault injection throughout the design process is described in this paper. This methodology incorporates a fault injection technique that can be used with any VHDL model, including behavioral, synthesizeable VHDL models. The technique separates the fault-free VHDL descriptions from the fault injection process so that existing models can be used with minimal changes to the existing VHDL code. The fault injection is accomplished through the use of an alternate de?nition of the Mentor Graphics standard bit type, qsim_state, so that fault injection can be performed on the same VHDL model that is synthesized using Autologic. Also, the same fault injection technique can be used on a structural VHDL model of the synthesized design generated using the Mentor Graphics utility, vhdlwrite. The fault injection methodology is applied to the design of a watchdog monitor card in a distributed computer system. Simulation results illustrate the fault injection methodology at multiple levels.

1Introduction

The purpose of fault injection is to provide a method for assessing the dependability of the system under test. Fault injection involves inserting faults into a system and monitoring the system to determine its behavior in response to a fault. Fault injection is often the only alternative when the complexity of computer systems precludes analytical solutions to safety and reliability. Fault injection has traditionally been performed in hardware and software prototypes near the end of the design cycle. For computer applications in which safety or reliability is the paramount concern, dependability evaluation must be performed from system level design to gate level implementation in order to meet stringent requirements on reliability and safety. Furthermore, performing re-designs after assessing dependability at the prototype phase is a more costly alternative than evaluating dependability and re-engineering, if necessary, early in the design process. Performing fault injection in simulation models at multiple levels of design enables dependability and performance evaluation throughout the design process in a cost effective design methodology.

This paper describes a fault injection methodology using VHDL in which fault injection

may be incorporated from the system level of a design to the synthesized gate-level logic in order

to assess the dependability of the design under test. The fault injection methodology is applied to

the design of an on-line processor monitoring card used in a distributed computer system

architecture for wayside and carborne train control applications. The monitoring card, hereafter

referred to as the watchdog monitor, was designed using synthesizeable VHDL and implemented

in Field Programmable Gate Arrays (FPGAs). The key features presented in this paper are: 1) fault

injection is performed at multiple levels of design, 2) fault injection is performed using standard

VHDL; consequently this approach can be applied in any standard VHDL simulation environment,

3) the fault injection methodology is independent of the modeled system, facilitating fault injection

in existing designs with little modi?cation, and 4) fault injection can be performed in a synthesized

VHDL model automatically without having to write gate-level VHDL descriptions.

Following this introduction, Section 2 presents the fault injection methodology for the

design process. Section 3 describes the watchdog monitor design. Simulation results from fault-

free simulations for functional veri?cation and fault injection experiments for dependability

assessment are presented at two levels of design in Section 4. Conclusions are summarized in

Section 5.

2Fault Injection Methodology

The fault injection methodology applied at all levels of design in this work involves the

interception of signals and the corruption of the information present on the signal according to fault

injection times and error types. This methodology separates the functional descriptions of design

models from the fault injection process. Since the fault injection process is independent of the

design models, the fault models can be applied to a wide range of designs without altering the

functional VHDL design descriptions. Additionally, the fault injection process is controllable so

that fault-free simulations of the design model can be executed with the fault injection process

present. Finally, since the fault injection process is written in standard VHDL, the methodology is

simulator-independent.

At the system level, dedicated fault injection components written in VHDL are instantiated

in the designs in order to corrupt signals and the ?ow of information. An example of this is shown

in Figure 1(a). At this level, information is represented as packets of data, referred to as tokens

[1][2][3], depicted as the q in Figure 1(a). The tokens can either represent only information ?ow (referred to as Uninterpreted Modeling [1][2][3]) or information ?ow along with value(s) for the

information (referred to as Interpreted Modeling [1][2][3]). At the higher levels of abstraction, the

effect of lower level faults can be manifested in a number of different ways corresponding to

classes of an error model. The fault injection components at the higher levels of design re?ect the

error model found at the architectural and algorithmic levels of design. At lower levels of design,

including the functional block and logic gate levels, the stuck-at fault model is used to inject faults

transiently or permanently. As shown in Figure 1(b) and Figure 1(c), the fault injection module

maps the input and output signal(s) to a data structure that associates a fault mask with the data

value of each signal. The fault mask indicates which bit(s) will be corrupted and what stuck-at

value(s) will be used. A Bus Resolution Function (BRF) is used to determine the resulting value of

the data signal with the fault(s) injected according the mask value.

Figure 3 Schematic of the Watchdog Monitor Design

Actel ACT2 technology [5]). Timing information regarding gate delays and so forth has been back-annotated into the design to provide more realistic simulation results. This could also include incorporating third-party vendor models (such as Logic Modeling Corporation (LMC) models [6]) into the design as well. For instance, LMC models for the data bus line drivers and the PROMs were added to the design to further improve the simulation results. Finally, all the additional components that are necessary to prepare the design for board-level fabrication (such as P1-P2 connectors, decoupling capacitors, and so forth) are added to the schematic.

4Simulation of the Functional Block Level Watchdog Monitor

As in most design methodologies, simulations were performed at each stage in the design of the watchdog monitor to ensure the correct functional behavior under fault-free conditions. However, as mentioned earlier, when safety is a concern, the design must also be simulated under faulty conditions to ensure it will still perform in a safe manner. The functional block level model of the watchdog monitor shown in Figure 3 was simulated with and without fault injection. At this level in the design process, faults can be injected on any of the signals de?ned in the behavioral, synthesizeable VHDL model(s). This includes the port signals as well as any internal signals that have been de?ned to be synthesized. For instance, the example fault injection experiment shown

in Figure 5 is one where the lower three bits of the address value generated by the comparator circuit to address the PROM that stores the expected signature(s) are stuck at “000”. In Figure 5(a), the values for the PROM address and the two 500 Hz signals (labeled as toggle(1:0) in Figure 5) generated by the comparator are shown. As can be seen, the values for the two 500 Hz signals are toggling from “10” to “01” which is an indication that the watchdog monitor has not detected an error in the system. However, as shown in Figure 5(b), when the lower three bits of the PROM address are stuck at “000” at time 3 ms, the two signals ?atline to “00” to indicate an error has occurred and been detected.

Similar results are obtainable at the logic level since the fault injection mechanism is identical to the one used at the functional block level. However, at the logic level, the designer can now inject faults on any input or output signals to any gates in the synthesized design. And, the most important feature to recognize here is that the fault injection occurs on VHDL that is not written by the designer but generated automatically by the design tool.

For instance, consider the simulation results for the signature comparator shown in Figure 5. Remember that during fault free operation (in the system as well as the watchdog monitor), the comparator compares the computed signature (labeled as actual_sig in Figure 5) with the expected signature that was computed off-line (labeled as expected_sig in Figure 5) one bit at a time. If these two signatures match, then the comparator outputs two 500 Hz complementary signals (labeled as toggle(1:0) in Figure 5). This is shown in Figure 5(a). In Figure 5(b), a stuck-at-1 fault is injected on signal mgc_n10 (this is the signal that is responsible for causing toggle(1:0) to toggle between “10” and “01” if actual_sig and expected_sig are equal) at 4519999 ns for 2 ns. This fault causes toggle(1:0) to ?atline to “00” to indicate that the fault was detected.

5Conclusions

Presented in this paper is a design process that incorporates a fault injection technique that can be applied at multiple levels in the design process. Two such levels, the functional block and logic levels, were presented in this paper. The design process was applied to a watchdog monitor system which was designed using synthesizeable VHDL and implemented using Actel FPGAs. The most important thing to keep in mind about the fault injection technique is that it is independent of the modeled system. This implies several things. First, the synthesizeable VHDL used at the functional block level to perform the fault simulations is the same VHDL that is used to perform the logic synthesis. Thus, the same model that is used in the design process can be used in the fault simulations. Second, the fault injection technique can be applied to existing models. For instance, the fault simulations that were performed at the logic level were performed on a VHDL model that was generated from the synthesized schematic by the Mentor Graphics system (using the Mentor Graphics tool, vhdlwrite). Finally, the fault injection is performed using standard VHDL constructs. Thus, the fault simulations can be performed using any VHDL simulation environment that supports full 1076 VHDL.

6References

[1]J.H. Aylor, R. Waxman, B.W. Johnson, R.D. Williams, “The Integration of Performance and

Functional Modeling in VHDL”,Performance and Fault Modeling with VHDL, J.M. Schoen, editor, Prentice Hall, Englewood Cliffs, N.J., 1992, pp. 22 - 145.

[2]DeLong, Todd A., Barry W. Johnson, Joseph A. Profeta III, and Danielle Bozzolo, “A Novel

Fault In

j ection Technique for Behavioral-Level Modeling using VHDL”,V HDL

International Users’ Forum - Notebook of Sessions, McLean, VA, November 13-16, pp. 9.13-

9.21.

[3]Cutright, E.D., R. Rao, J. H. Aylor, and B. W. Johnson, “Performance Modeling of Fault-

Tolerant Systems Using VHDL”, Technical Report # 900914.1, Dept. of Electrical Engineering, University of Virginia, September 1990.

[4]Smith, D. Todd, Barry W. Johnson, Joseph A. Profeta III, and Daniele G. Bozzolo, “A Method

to Determine Equivalent Fault Classes for Permanent and Transient Faults”,Annual Reliability and Maintainability Symposium - 1995 Proceedings, Washington DC, January 16-19, 1995, pp. 418-424.

[5]Actel FPGA Data Book and Design Guide, Actel Corporation, 1993.

[6]SmartModel Library User’s Guide, Logic Modeling Corporation, 1993.

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(完整)高中英语阅读课公开课说课稿一等奖

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中英语阅读课公开课原文 Interpretation Good morning, ladies and gentlemen. It’s my great honor and pleasure to be here sharing my lesson with you. I have been ready to begin this representation with five parts. Analysis of the teaching material, the teaching aims, the important and difficult points, the studying methods, and the teaching procedure. Part 1 Teaching Material The content of my lesson is a reading material, through the learning of which, I’ll enable students to know more about Jackie Chan, his life career and the qualities that lead to his success. At the same time, make Ss aware of the question-and-answer format in an interview and learn how to conclude a question from the answer. Part 2 Teaching Aims According to the new standard curriculum and the syllabus (新课程标准和教学大纲), and after studying the teaching material, the teaching aims are the followings: 1.Knowledge objects (语言目标：语音，词汇，语法，功能，话题) (1)The Ss can learn question-and-answer format in an interview. (2) The Ss can understand the content of the lesson, talk about Jackie Chan’s life career and form their own opinion about success. 2.Ability objects (技能目标：听，说，读，写) (1) To develop the Ss’ abilities of listening, speaking, reading and writing (2) To improve Ss' reading abilities, especially their skimming and scanning abilities. (3) To train the Ss’ abilit ies of studying by themselves and through cooperating. 3.Emotion or moral objects (情感目标：兴趣，自信，合作，爱国，国际视野) Learn from Jackie Chan and understand the way to success is not smooth. Put the moral education in the process of study. Part 3 the Important and Difficult Points The important points are what qualities are required to be successful? Such as creativity, persistence and talent. The difficult points are Help students to conclude the questions of interviewers according to Jackie Chan’s answers. Part 4 Teaching Methods As is known to us all, a good teaching method requires that the teacher should help Ss develop good sense of the English language. For achieving these teaching aims,

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