MM54C164中文资料

TL F 5896MM54C164 MM74C1648-Bit Parallel-Out Serial Shift Register

February 1988

MM54C164 MM74C164

8-Bit Parallel-Out Serial Shift Register

General Description

The MM54C164 MM74C164shift registers are a monolithic complementary MOS (CMOS)integrated circuit constructed with N-and P-channel enhancement transistors These 8-bit shift registers have gated serial inputs and clear Each regis-ter bit is a D-type master slave flip-flop A high-level input enables the other input which will then determine the state of the flip-flop

Data is serially shifted in and out of the 8-bit register during the positive going transition of clock pulse Clear is indepen-dent of the clock and accomplished by a low level at the clear input All inputs are protected against electrostatic ef-fects

Features

Y Supply voltage range

3V to 15V

Y Tenth power TTL compatible drive 2LPTTL loads

Y High noise immunity 0 45V CC (typ )Y Low power

50nW (typ )Y

Medium speed operation

0 8MHz (typ )with 10V supply

Applications

Y Data terminals Y Instrumentation Y Medical electronics Y

Alarm systems

Y Industrial electronics Y Remote metering Y

Computers

Truth Table

Serial Inputs A and B Inputs Output t n t n a 1A B Q A 1110101000

Connection Diagram

Dual-In-Line Package

TL F 5896–2

Top View

Order Number MM54C164or MM74C164

Block Diagram

TL F 5896–1

C 1995National Semiconductor Corporation RRD-B30M105 Printed in U S A

Absolute Maximum Ratings(Note1)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin b0 3V to V CC a0 3V Operating Temperature Range

MM54C164b55 C to a125 C MM74C164b40 C to a85 C Storage Temperature Range b65 C to a150 C Absolute Maximum V CC18V Power Dissipation(P D)

Dual-In-Line700mW Small Outline500mW Operating V CC Range3V to15V Lead Temperature(soldering 10sec )260 C

DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V IN(1)Logical‘‘1’’Input Voltage V CC e5V3 5V

V CC e10V8 0V

V IN(0)Logical‘‘0’’Input Voltage V CC e5V1 5V

V CC e10V2 0V

V OUT(1)Logical‘‘1’’Output Voltage V CC e5V I O e b10m A4 5V

V CC e10V I O e b10m A9 0V

V OUT(0)Logical‘‘0’’Output Voltage V CC e5V I O e a10m A0 5V

V CC e10V I O e a10m A1 0V I IN(1)Logical‘‘1’’Input Current V CC e15V V IN e15V0 0051 0m A I IN(0)Logical‘‘0’’Input Current V CC e15V V IN e0V b1 0b0 005m A I CC Supply Current V CC e15V0 05300m A CMOS TO LPTTL INTERFACE

V IN(1)Logical‘‘1’’Input Voltage54C V CC e4 5V V CC b1 5V

74C V CC e4 75V V CC b1 5V

V IN(0)Logical‘‘0’’Input Voltage54C V CC e4 5V0 8V

74C V CC e4 75V0 8V

V OUT(1)Logical‘‘1’’Output Voltage54C V CC e4 5V I O e b360m A2 4V

74C V CC e4 75V I O e b360m A2 4V

V OUT(0)Logical‘‘0’’Output Voltage54C V CC e4 5V I O e360m A0 4V

74C V CC e4 75V I O e360m A0 4V OUTPUT DRIVE(See54C 74C Family Characteristics Data Sheet)(Short Circuit Current)

I SOURCE Output Source Current V CC e5V V IN(0)e0V

b1 75mA

T A e25 C V OUT e0V

I SOURCE Output Source Current V CC e10V V IN(0)e0V

b8 0mA

T A e25 C V OUT e0V

I SINK Output Sink Current V CC e5V V IN(1)e5V

1 75mA

T A e25 C V OUT e V CC

I SINK Output Sink Current V CC e10V V IN(1)e10V

8 0mA

T A e25 C V OUT e V CC

Note1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operation

2

AC Electrical Characteristics T A e25 C C L e50pF unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

t pd1Propagation Delay Time to a Logical‘‘0’’or a V CC e5V230310ns Logical‘‘1’’from Clock to Q V CC e10V90120ns

t pd0Propagation Delay Time to a Logical‘‘0’’from V CC e5V280380ns Clear to Q V CC e10V110150ns

t S Time Prior to Clock Pulse that Data V CC e5V200110ns Must be Present V CC e10V8030ns

t H Time After Clock Pulse that V CC e5V00ns Data Must be Held V CC e10V00ns

f MAX Maximum Clock Frequency V CC e5V2 03MHz

V CC e10V5 58MHz

t W Minimum Clear Pulse Width V CC e5V150250ns

V CC e10V5590ns

t r t f Maximum Clock Rise and Fall Time V CC e5V15m s

V CC e10V5m s

C IN Input Capacitance Any Input(Note2)5pF

C P

D Power Dissipation Capacitance(Note3)140pF AC Parameters are guaranteed by DC correlated testing

Note2 Capacitance is guaranteed by periodic testing

Note3 C PD determines the no load AC power consumption of any CMOS device For complete explanation see54C 74C Family Characteristics application note AN-90

Logic Waveforms

TL F 5896–3

3

Switching Time Waveforms

CMOS to CMOS

TL F 5896–4t r e t f e 20ns

TTL to CMOS

TL F 5896–5

AC Test Circuit

TL F 5896–6

Typical Applications

74C Compatibility

TL F 5896–7

Guaranteed Noise Margin as a Function of V CC

TL F 5896–8

4

Physical Dimensions inches(millimeters)

Ceramic Dual-In-Line Package(J)

Order Number MM54C164J or MM74C164J

NS Package Number J14A

5

M M 54C 164 M M 74C 1648-B i t P a r a l l e l -O u t S e r i a l S h i f t R e g i s t e r

Physical Dimensions inches (millimeters)

Molded Dual-In-Line Package (N)

Order Number MM54C164N or MM74C164N

NS Package Number N14A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness

be reasonably expected to result in a significant injury to the user

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