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60进制计数器verilog设计代码

module CatShitOne(clk,ret,LED,saomiao);
input clk;
input ret;
output reg [2:0] saomiao;
output reg [6:0] LED;
reg [13:0] clk_ct;
reg pulse;
reg [3:0] SECL,SECH;
reg [3:0] MINL,MINH;
reg [3:0] LEDSTATE;

always @ (posedge clk)
begin
if(clk_ct==900)
begin
clk_ct<=0;
pulse<=~pulse;
end
else clk_ct<=clk_ct+1;
end

always @ (posedge pulse or negedge ret)
if(!ret)
begin
SECL<=0;
SECH<=0;
MINL<=0;
MINH<=0;
end
else
begin
if(SECL==9)
begin
SECL<=0;
if(SECH==5)
begin
SECH<=0;
if(MINL==9)
begin
MINL<=0;
if(MINH==5)
MINH<=0;
else MINH<=MINH+1;
end
else MINL<=MINL+1;
end
else SECH<=SECH+1;
end
else SECL<=SECL+1;
end

always @ (posedge clk)
saomiao<=saomiao+1;

always @ (saomiao)
case(saomiao)
3'b000: LEDSTATE=4'b0000;
3'b001: LEDSTATE=4'b0000;
3'b010: LEDSTATE=4'b0000;
3'b011: LEDSTATE=MINH;
3'b100: LEDSTATE=MINL;
3'b101: LEDSTATE=4'b1010;
3'b110: LEDSTATE=SECH;
3'b111: LEDSTATE=SECL;
default:LEDSTATE=SECL;//
endcase

always @ (LEDSTATE)
case(LEDSTATE)
4'b0000: LED=7'b1111110;
4'b0001: LED=7'b0110000;
4'b0011: LED=7'b1111001;
4'b0100: LED=7'b0110011;
4'b0101: LED=7'b1011011;
4'b0110: LED=7'b1011111;
4'b0111: LED=7'b1110000;
4'b1000: LED=7'b1111111;
4'b1001: LED=7'b1111011;
4'b1010: LED=7'b0000000;
default: LED=7'b0000000;
endcase
endmodule


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