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ACT-5261PC-250F17M中文资料

Features

eroflex Circuit Technology – RISC TurboEngines For The Future ? SCD5261 REV 1 12/22/98

Block Diagram

s Full militarized QED RM5261 microprocessor

Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle

q 133, 150, 200, 250 MHz operating frequencies – Consult Factory

for latest speeds

q 345 Dhrystone 2.1 MIPS

q SPECInt95 7.3, SPECfp95 8.3

s Pinout compatible with popular RM5260

High performance system interface compatible with RM5260, RM 5270, RM5271, RM7000, R4600, R4700 and R5000

q 64-bit multiplexed system address/data bus for optimum price/

performance

q High performance write protocols maximize uncached write bandwidth

q Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)q IEEE 1149.1 JTAG boundary scan

? Integrated on-chip caches

q 32KB instruction - 2 way set associative q 32KB data - 2 way set associative q Virtually indexed, physically tagged

q Write-back and write-through on per page basis q Pipeline restart on first double for data cache misses

? Integrated memory management unit

q Fully associative joint TLB (shared by I and D translations)q 48 dual entries map 96 pages

q Variable page size (4KB to 16MB in 4x increments)

High-performance floating point unit: up to 500 MFLOPS

q Single cycle repeat rate for common single precision operations

and some double precision operations

q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations

q Single cycle repeat rate for single precision combined multiply- add operation

? MIPS IV instruction set

q Floating point multiply-add instruction increases performance in

signal processing and graphics applications q Conditional moves to reduce branch frequency q Index address modes (register + register)

Embedded application enhancements

q Specialized DSP integer Multiply-Accumulate instruction and 3

operand multiply instruction q I and D cache locking by set

q Optional dedicated exception vector for interrupts

Fully static CMOS design with power down logic

q Standby reduced power mode with WAIT instruction q 3.6 Watts typical power @ 200MHz q 2.5V core with 3.3V IO’s

s 208-lead CQFP , cavity-up package (F17)

s 208-lead CQFP , inverted footprint (F24), Intended to duplicate the commercial QED footprint

179-pin PGA package (Future Product ) (P10)

Preliminary

64-Bit Superscaler Microprocessor

ACT 5261

DESCRIPTION

The Aeroflex ACT5261 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 32 KByte 2-way set associative instruction cache, a 32 KByte 2-way set associative data cache, and a high-performance 64-bit system interface. The ACT5261 can issue both an integer and a floating point instruction in the same cycle.

The ACT5261 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.

HARDWARE OVERVIEW

The ACT5261 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the ACT5261 are briefly described below.

Superscalar Dispatch

The ACT5261 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/ store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5261 provides unparalleled price/performance in computationally intensive embedded applications.

CPU Registers

Like all MIPS ISA processors, the ACT5261 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Pipeline

For integer operations, loads, stores, and other non-floating-point operations, the ACT5261 uses the simple 5-stage pipeline also found in the RM52xx family, 4600, R4700, and R5000. In addition to this standard pipeline, the ACT5261 uses an extended seven stage pipeline for floating-point operations. Like the ACT5260, the ACT5261 does virtual to physical translation in parallel with cache access.Integer Unit

Like the ACT5260, the ACT5261 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5261 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5261 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply.

The ACT5261 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/ divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/divide operations, and the program counter(PC).

The ACT5261 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.

ALU

The ACT5261 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle.

For additional Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark? RM 5261?, 64-Bit Superscalar Microprocessor see the latest QED datasheet (Revision 1.0 July 1998).

1.8401.880

1.700BSC 1.700BSC 1.8401.880

V U T R P N M L K J H G F E D C B A

9101112131415161718

Bottom View

Side View

Future Package – "P10" – PGA 179 Pins (Advanced)

1.131 (28.727) SQ 1.109 (28.169) SQ

1.009 (25.63).9998 (25.37)51 Spaces at .0197(51 Spaces at .50)

.0236 (.51).0158 (.49)

208

156

157

105

10453Pin 1 Chamfer

Detail "A"

0°±5°1.331 (33.807)1.269 (32.233)

.005 (.127).008 (.258)

.055 (1.397)

REF .055 (1.397).045 (1.143)

.115 (2.921)

MAX

.960 (24.384) SQ

REF

.130 (3.302)

MAX

.010R MIN

.010R MIN .009 (.253).007 (.178)

.015 (.381).009 (.229)

.100 (2.540).080 (2.032)

Package Information – "F17" – CQFP 208 Leads

Detail "A"

BSC

.100.221MAX

.018

.050

Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction.

.035 (.889).025 (.635)

Units: Inches (Millimeters)

ACT5261 Microprocessor CQFP Pinouts – "F17"

Pin #Function Pin #Function Pin # Function Pin # Function 1Vcc (3.3V)53NC105Vcc (3.3V)157NC

2NC54NC106NMI*158NC

3NC55NC107ExtRqst*159NC

4Vcc (3.3V)56Vcc (3.3V)108Reset*160NC

5Vss57Vss109ColdReset*161Vcc (3.3V) 6SysAD458ModeIn110VccOK162Vss

7SysAD3659RdRdy*111BigEndian163SysAD28 8SysAD560WrRdy*112Vcc (3.3V)164SysAD60 9SysAD3761ValidIn*113Vss165SysAD29 10Vcc (2.5V)62ValidOut*114SysAD16166SysAD61 11Vss63Release*115SysAD48167Vcc (2.5V) 12SysAD664VccP116Vcc (2.5V)168Vss

13SysAD3865VssP117Vss169SysAD30 14Vcc (3.3V)66SysClock118SysAD17170SysAD62 15Vss67Vcc (2.5V)119SysAD49171Vcc (3.3V) 16SysAD768Vss120SysAD18172Vss

17SysAD3969Vcc (3.3V)121SysAD50173SysAD31 18SysAD870Vss122Vcc (3.3V)174SysAD63 19SysAD4071Vcc (2.5V)123Vss175SysADC2 20Vcc (2.5V)72Vss124SysAD19176SysADC6 21Vss73SysCmd0125SysAD51177Vcc (2.5V) 22SysAD974SysCmd1126Vcc (2.5V)178Vss

23SysAD4175SysCmd2127Vss179SysADC3 24Vcc (3.3V)76SysCmd3128SysAD20180SysADC7 25Vss77Vcc (3.3V)129SysAD52181Vcc (3.3V) 26SysAD1078Vss130SysAD21182Vss

27SysAD4279SysCmd4131SysAD53183SysADC0 28SysAD1180SysCmd5132Vcc (3.3V)184SysADC4 29SysAD4381Vcc (3.3V)133Vss185Vcc (2.5V) 30Vcc (2.5V)82Vss134SysAD22186Vss

31Vss83SysCmd6135SysAD54187SysADC1 32SysAD1284SysCmd7136Vcc (2.5V)188SysADC5 33SysAD4485SysCmd8137Vss189SysAD0 34Vcc (3.3V)86SysCmdP138SysAD23190SysAD32 35Vss87Vcc (2.5V)139SysAD55191Vcc (3.3V) 36SysAD1388Vss140SysAD24192Vss

37SysAD4589Vcc (2.5V)141SysAD56193SysAD1 38SysAD1490Vss142Vcc (3.3V)194SysAD33 39SysAD4691Vcc (3.3V)143Vss195Vcc (2.5V) 40Vcc (2.5V)92Vss144SysAD25196Vss

41Vss93Int0*145SysAD57197SysAD2 42SysAD1594Int1*146Vcc (2.5V)198SysAD34 43SysAD4795Int2*147Vss199SysAD3 44Vcc (3.3V)96Int3*148SysAD26200SysAD35 45Vss97Int4*149SysAD58201Vcc (3.3V) 46ModeClock98Int5*150SysAD27202Vss

47JTDO99Vcc (3.3V)151SysAD59203NC

48JTDI100Vss152Vcc (3.3V)204NC

49JTCK101NC153Vss205NC

50JTMS102NC154NC206NC

51Vcc (3.3V)103NC155NC207Vcc (3.3V) 52Vss104NC156Vss208Vss

Sample Ordering Information

Part Number

Screening Speed (MHz)

Package ACT - 5261PC-133F17I Industrial Temperature 133 208 Lead CQFP ACT - 5261PC-150F17C Commercial Temperature 150 208 Lead CQFP ACT - 5261PC-200F17T Military Temperature 200 208 Lead CQFP ACT -5261PC-250F17M

Military Screening

250

208 Lead CQFP

Aeroflex Circuit Technology 35 South Service Road

Plainview New York 11803 Telephone: (516) 694-6700FAX: (516) 694-6715

Toll Free Inquiries: (800) https://www.wendangku.net/doc/d56805952.html,/act1.htm

E-Mail: sales-act@https://www.wendangku.net/doc/d56805952.html,

Specifications subject to change without notice.

C I R C U I T T E C H N O L O G Y

Part Number Breakdown

ACT– 5261PC –200F17M

Aeroflex Circuit Technology

Base Processor Type

133 = 133MHz 150 = 150MHz 200 = 200MHz 250 = 250MHz

266 = 266MHz (Future Option)

Cache Style

Package Type & Size

C = Commercial Temp, 0°C to +70°C I = Industrial T emp, -40°C to +85°C T = Military T emp, -55°C to +125°C

M = Military T emp, -55°C to +125°C, Screened *Q = MIL-PRF-38534 Compliant/SMD if applicable

Screening

* Screened to the individual test methods of MIL-STD-883

PC = Primary Cache

Maximum Pipeline Freq.

Surface Mount Package

F17 = 1.120" SQ 208 Lead CQFP

F24 = 1.120" SQ Inverted 208 Lead CQFP

Thru-Hole Package

P10 = 1.86"SQ PGA 179 pins with shoulder (Advanced)