AD5200_5201

a
FEATURES AD5200—256-Position AD5201—33-Position 10 k , 50 k 3-Wire SPI-Compatible Serial Data Input Single Supply 2.7 V to 5.5 V or Dual Supply 2.7 V for AC or Bipolar Operations Internal Power-On Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching
256-Position and 33-Position Digital Potentiometers AD5200/AD5201
FUNCTIONAL BLOCK DIAGRAM
AD5200/AD5201
VDD VSS A CS CLK SDI GND PWR-ON PRESET SER REG Dx W B 8/6 RDAC REG SHDN
GENERAL DESCRIPTION
The AD5200 and AD5201 are programmable resistor devices, with 256 positions and 33 positions respectively, that can be digitally controlled through a 3-wire SPI serial interface. The terms programmable resistor, variable resistor (VR), and RDAC are commonly used interchangeably to refer to digital potentiometers. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Both AD5200/AD5201 contain a single variable resistor in the compact μSOIC-10 package. Each device contains a fixed wiper resistance at the wiper contact that taps the programmable resistance at a point determined by a digital code. The code is loaded in the serial input register. The resistance between the wiper and either end point of the programmable resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 10 k? or 50 k?
has a nominal temperature coefficient of 500 ppm/°C. The VR has a VR latch that holds its programmed resistance value. The VR latch is updated from an SPI-compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eight data bits for the AD5200 and six data bits for the AD5201 make up the data word that is clocked into the serial input register. The internal preset forces the wiper to the midscale position by loading 80H and 10H into AD5200 and AD5201 VR latches respectively. The SHDN pin forces the resistor to an end-to-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch setting puts the wiper in the same resistance setting prior to shutdown. The digital interface is still active during shutdown so that code changes can be made that will produce a new wiper position when the device is returned from shutdown. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 https://www.wendangku.net/doc/d512510558.html, Fax: 781/326-8703 ? Analog Devices, Inc., 2001

AD5200/AD5201–SPECIFICATIONS
AD5200 ELECTRICAL CHARACTERISTICS –40 C < T < +85 C unless otherwise noted.)
A
(VDD = 5 V
10%, or 3 V
10%, VSS = 0 V, VA = +VDD, VB = 0 V,
Min Typ1 –1 –2 –30 Max Unit LSB LSB % ppm/°C ? Bits LSB LSB ppm/°C LSB LSB V pF pF μA nA V V V V μA pF V V V μA μA mW %/% kHz kHz % μs nV√Hz
Parameter
Symbol
Conditions RWB, VA = No Connect RWB, VA = No Connect TA = 25°C V AB = V DD, Wiper = No Connect V DD = 5 V
DC CHARACTERISTICS RHEOSTAT MODE R-DNL Resistor Differential Nonlinearity 2 R-INL Resistor Integral Nonlinearity 2 ?RAB Nominal Resistor Tolerance 3 Resistance Temperature Coefficient RAB/?T Wiper Resistance RW
± 0.25 +1 ± 0.5 +2 +30 500 50 100
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N DNL Differential Nonlinearity 4 INL Integral Nonlinearity 4 Code = 80 H Voltage Divider Temperature Coefficient ?VW/?T Code = FF H Full-Scale Error V WFSE Zero-Scale Error V WZSE Code = 00 H RESISTOR TERMINALS Voltage Range 5 Capacitance 6 A, B Capacitance 6 W Shutdown Supply Current Common-Mode Leakage V A, B, W C A, B CW IDD_SD ICM VIH VIL VIH VIL IIL C IL V LOGIC V DD RANGE VDD/SS RANGE IDD ISS PDISS PSS
6, 9
8 –1 –2
± 1/4 ± 1/2 5 –1.5 –0.5 0 +0.5 VSS
+1 +2 0 +1.5 VDD
7
f = 1 MHz, Measured to GND, Code = 80 f = 1 MHz, Measured to GND, Code = 80 V DD = 5.5 V V A = V B = V DD/2
H H
45 60 0.01 1 2.4
5
DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance 6 POWER SUPPLIES Logic Supply Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation 8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth –3 dB Total Harmonic Distortion V W Settling Time (10 k?/50 k?) Resistor Noise Voltage Density
0.8 V DD = 3 V, VSS = 0 V V DD = 3 V, VSS = 0 V V IN = 0 V or 5 V 2.1 0.6 ±1 5 2.7 –0.3 ± 2.3 5.5 5.5 ± 2.7 15 40 15 40 0.2 –0.01 0.001 +0.01 600 100 0.003 2/9 9
V SS = 0 V V IH = +5 V or V IL = 0 V V SS = –5 V V IH = +5 V or V IL = 0 V, VDD = +5 V, VSS = 0 V ?VDD = +5 V ± 10%, Code = Midscale RAB = 10 k?, Code = 80 H RAB = 50 k?, Code = 80 H V A = 1 V rms, V B = 0 V, f = 1 kHz, R AB = 10 k? V A = 5 V, VB = 0 V, ± 1 LSB Error Band RWB = 5 k?, RS = 0
BW_10 k? BW_50 k? THD W tS e N_WB
NOTES 1 Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both V DD = +2.7 V, V SS = –2.7 V. 3 VAB = VDD, Wiper (VW) = No connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. 5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. A terminal is open-circuited in shutdown mode. 8 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use V DD = 5 V, VSS = 0 V. Specifications subject to change without notice.
–2–
REV. B

AD5200/AD5201 AD5201 ELECTRICAL CHARACTERISTICS –40 C < T < +85 C unless otherwise noted.)
A
(VDD = 5 V
10%, or 3 V
10%, VSS = 0 V, VA = +VDD, VB = 0 V,
Min Typ1 –0.5 ± 0.05 –1 ± 0.1 –30 500 50 6 –0.5 ± 0.01 –1 ± 0.02 5 –1/2 –1/4 0 +1/4 VSS Max +0.5 +1 +30 100 Unit LSB LSB % ppm/°C ? Bits LSB LSB ppm/°C LSB LSB V pF pF μA nA V V V V μA pF V V V μA μA mW %/% kHz kHz % μs nV√Hz
Parameter
Symbol
Conditions RWB, VA = No Connect RWB, VA = No Connect TA = 25°C VAB = V DD, Wiper = No Connect VDD = 5 V
DC CHARACTERISTICS RHEOSTAT MODE R-DNL Resistor Differential Nonlinearity 2 R-INL Resistor Integral Nonlinearity 2 ?RAB Nominal Resistor Tolerance 3 Resistance Temperature Coefficient RAB/?T Wiper Resistance RW
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) N Resolution 4 DNL Differential Nonlinearity 5 INL Integral Nonlinearity 5 Code = 10 H Voltage Divider Temperature Coefficient ?VW/?T Code = 20 H Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00 H RESISTOR TERMINALS Voltage Range 6 Capacitance 7 A, B Capacitance 7 W Shutdown Supply Current Common-Mode Leakage VA, B, W C A, B CW IDD_SD ICM VIH VIL VIH VIL IIL C IL VLOGIC VDD RANGE VDD/SS RANGE IDD ISS PDISS PSS
7, 10
+0.5 +1 0 +1/2 VDD
8
f = 1 MHz, Measured to GND, Code = 10 f = 1 MHz, Measured to GND, Code = 10 VDD = 5.5 V VA = V B = V DD/2
H H
45 60 0.01 1 2.4
5
DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance 7 POWER SUPPLIES Logic Supply Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation 9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (10 k?/50 k?) Resistor Noise Voltage Density
0.8 VDD = 3 V, VSS = 0 V VDD = 3 V, VSS = 0 V VIN = 0 V or 5 V 2.1 0.6 ±1 5 2.7 –0.3 ± 2.3 5.5 5.5 ± 2.7 15 40 15 40 0.2 –0.01 0.001 +0.01 600 100 0.003 2/9 9
VSS = 0 V VIH = +5 V or V IL = 0 V VSS = –5 V VIH = +5 V or V IL = 0 V, VDD = +5 V, VSS = –5 V ?VDD = +5 V ± 10% RAB = 10 k?, Code = 10 H RAB = 50 k?, Code = 10 H VA = 1 V rms, V B = 0 V, f = 1 kHz, R AB = 10 k? VA = 5 V, VB = 0 V, ± 1 LSB Error Band RWB = 5 k?, RS = 0
BW_10 k? BW_50 k? THD W tS e N_WB
NOTES 1 Typicals represent average readings at 25°C and V DD = 5 V, VSS = 0 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V, VSS = –2.7 V. 3 VAB = VDD, Wiper (VW) = No connect. 4 Six bits are needed for 33 positions even though it is not a 64-position device. 5 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. 6 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Measured at the A terminal. A terminal is open-circuited in shutdown mode. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use V DD = 5 V, VSS = 0 V. Specifications subject to change without notice.
REV. B
–3–

AD5200/AD5201–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
(VDD = 5 V 10%, or 3 V unless otherwise noted.)
Conditions
10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C
Min 20 5 5 15 40 0 0 10 Typ1 Max Unit ns ns ns ns ns ns ns ns
Symbol
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3]) Input Clock Pulsewidth tCH, tCL Clock Level High or Low Data Setup Time tDS Data Hold Time tDH CS Setup Time tCSS CS High Pulsewidth tCSW CLK Fall to CS Fall Hold Time tCSH0 CLK Fall to CS Rise Hold Time tCSH1 CS Rise to Clock Rise Setup tCS1
NOTES 1 Typicals represent average readings at 25°C and VDD = 5 V, VSS = 0 V. 2 Guaranteed by design and not subject to production test. 3 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using V LOGIC = 5 V. Specifications subject to change without notice.
1 SDI 0 1 CLK 0 1 CS VOUT 0 1 0 DAC REGISTER LOAD D7 D6 D5 D4 D3 D2 D1 D0
Figure 1a. AD5200 Timing Diagram
1 SDI 0 1 CLK 0 1 CS VOUT 0 0 1 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
Figure 1b. AD5201 Timing Diagram
1 Dx 0 1 CLK 0 1 CS 0 VDD VOUT 0 1LSB Dx
SDI (DATA IN)
tCH
tDS
tDH
tCS1
tCSH0 tCSS
tCL tCSH1 tCSW tS
Figure 1c. Detail Timing Diagram
–4–
REV. B

AD5200/AD5201
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted)
PIN FUNCTION DESCRIPTIONS
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA2 Digital Inputs and Output Voltage to GND . . . . . . . 0 V, 7 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ Max) . . . . . . . . . 150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C Thermal Resistance θJA, μSOIC-10 . . . . . . . . . . . . . 200°C/W Package Power Dissipation = (TJ Max – TA)/θJA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Max current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31 and TPC 32 for detail.
Pin 1 2 3 4
Name B VSS GND CS
Description B Terminal. Negative Power Supply, specified for operation from 0 V to –2.7 V. Ground. Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register. Serial Data Input. Serial Clock Input, positive edge triggered. Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistors of RDAC to temporary infinite. Positive Power Supply (Sum of VDD + VSS ≤ 5.5 V). Wiper Terminal. A Terminal.
5 6 7
SDI CLK SHDN
8 9 10
VDD W A
PIN CONFIGURATION
B 1 VSS 2 GND 3 CS 4
10
A W VDD
AD5200/ AD5201
9 8
TOP VIEW 7 SHDN (Not to Scale) 6 CLK SDI 5
ORDERING GUIDE Model AD5200BRM10-REEL7 AD5200BRM50-REEL7 AD5201BRM10-REEL7 AD5201BRM50-REEL7 RES 256 256 33 33 k 10 50 10 50 Temperature Range –40°C/+85°C –40°C/+85°C –40°C/+85°C –40°C/+85°C Package Description μSOIC-10 μSOIC-10 μSOIC-10 μSOIC-10 Package Option RM-10 RM-10 RM-10 RM-10 Full Reel Qty. 5000 5000 5000 5000 Branding Information DLA DLB DMA DMB
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–

AD5200/AD5201–Typical Performance Characteristics
0.20
0.12
VDD = 2.7V, VSS = 0V
0.15 0.10
0.10 VDD = 5.5V, VSS = 0V 0.08
RDNL – LSB
RINL – LSB
0.05 0.00 0.05 0.10
0.06 0.04
VDD = +2.7V VSS = –2.7V
0.02
VDD = +2.7V, VSS = –2.7V
0.15
VDD = 2.7V, VSS = 0V 0.00
VDD = 5.5V, VSS = 0V
0.20
0
32
64
96 128 160 CODE – Decimal
192
224
256
–0.02
0
4
8
12 16 20 CODE – Decimal
24
28
32
TPC 1. AD5200 10 k ? RDNL vs. Code
TPC 4. AD5201 10 k ? RINL vs. Code
0.03 VDD = 5.5V, VSS = 0V 0.02 VDD = 2.7V, VSS = 0V
0.10 0.05 0.00
VDD = 2.7V, VSS = 0V
0.01
RDNL – LSB
0.00
–0.01 VDD = +2.7V, VSS = –2.7V –0.20 VDD = 5.5V, VSS = 0V –0.25 VDD = +2.7V, VSS = –2.7V –0.03 –0.30
–0.02
0
4
8
12 16 20 CODE – Decimal
24
28
32
DNL – LSB
–0.05 –0.10 –0.15
0
32
64
96 128 160 CODE – Decimal
192
224
256
TPC 2. AD5201 10 k ? RDNL vs. Code
TPC 5. AD5200 10 k ? DNL vs. Code
0.7 0.6 VDD = 2.7V, VSS = 0V 0.5
0.020
0.015
0.010
RINL – LSB
DNL – LSB
0.4 0.3 0.2 0.1 VDD = 5.5V, VSS = 0V
VDD = 5.5V, VSS = 0V VDD = +2.7V, VSS = –2.7V
0.005
0.000
–0.005
0.0 –0.1 VDD = +2.7V, VSS = –2.7V
–0.010
192 224 256
VDD = 2.7V, VSS = 0V
0
32
64
96 128 160 CODE – Decimal
0
4
8
12 16 20 CODE – Decimal
24
28
32
TPC 3. AD5200 10 k ? RINL vs. Code
TPC 6. AD5201 10 k ? DNL vs. Code
–6–
REV. B

AD5200/AD5201
0.3 0.2 VDD = 5.5V, VSS = 0V 0.1 0.0 20 18 VIL = VSS VIH = VDD VDD = 5.5V 16 14 12 10 VDD = 2.7V 8 6 4 2 VDD = 2.7V, VSS = 0V 0 –40
–0.1 –0.2 –0.3 –0.4 –0.5 VDD = +2.7V, VSS = –2.7V
0
32
64
96 128 160 CODE – Decimal
192
224
256
IDD SUPPLY CURRENT – A
INL – LSB
–20
0
20 40 60 TEMPERATURE – C
80
100
TPC 7. AD5200 10 k ? INL vs. Code
TPC 10. Supply Current vs. Temperature
0.020 VDD = +2.7V, VSS = –2.7V
14 VDD = 5.5V 12
0.015
IA SHUTDOWN CURRENT – nA
32
VDD = 5.5V, VSS = 0V 0.010
10 8 6 4 2 0
INL – LSB
0.005
0.000
–0.005 VDD = 2.7V, VSS = 0V
–0.010
0
4
8
12 16 20 CODE – Decimal
24
28
–2 –40
–20
0
20 40 60 TEMPERATURE – C
80
100
TPC 8. AD5201 10 k ? INL vs. Code
TPC 11. Shutdown Current vs. Temperature
10
160
IDD @ VDD/VSS = 5V/0V
140 120
SEE TEST CIRCUIT 13 TA = 25 C
1.0
IDD/ISS – mA
IDD @ VDD/VSS =
2.5V
100
VDD = 2.7V
RON –
0.1
80 60 40 VDD = 5.5V
ISS @ VDD/VSS =
0.01
2.5V
IDD @ VDD/VSS = 3V/0V
20 0 0
0.001 0.0
1.0
2.0
VIH – V
3.0
4.0
5.0
1
2
3 VSUPPLY – V
4
5
6
TPC 9. Supply Current vs. Logic Input Voltage
TPC 12. Wiper ON Resistance vs. V SUPPLY
REV. B
–7–

AD5200/AD5201
500 CODE FFH 450 400 350
6
0 80H –6 –12 40H 20H 10H 08H 04H –36 02H –42 –48 –54 1k 01H
IDD/ISS – A
GAIN – dB
300 250 ISS @ VDD/VSS = 200 150 100 50 0 10k IDD @ VDD/VSS = 5V/0V IDD @ VDD/VSS = 3V/0V IDD @ VDD/VSS = 2.5V 2.5V
–18 –24 –30
1M 100k FREQUENCY – Hz
10M
10k 100k FREQUENCY – Hz
1M
TPC 13. AD5200 10 k? Supply Current vs. Clock Frequency
TPC 16. AD5200 10 k ? Gain vs. Frequency vs. Code
500 CODE 55H 450 400 350
6
0 –6 –12
ISS @ VDD/VSS = 2.5V 2.5V
80H 40H 20H 10H 08H 04H 02H 01H
IDD/ISS – A
250 200 150
GAIN – dB
10M
300
–18 –24 –30 –36
IDD @ VDD/VSS =
IDD @ VDD/VSS = 5V/0V 100 IDD @ VDD/VSS = 3V/0V 50 0 10k
–42 –48
1M 100k FREQUENCY – Hz
–54 1k
10k 100k FREQUENCY – Hz
1M
TPC 14. AD5200 10 k? Supply Current vs. Clock Frequency
TPC 17. AD5200 50 k ? Gain vs. Frequency vs. Code
80
CODE = 80H, VA = VDD, VB = 0V
6
0
60
+PSRR @ VDD = 5V DC
10% p-p AC
–6 –12
10H 8H 4H 2H 1H
PSRR – dB
40
+PSRR @ VDD = 3V DC 10% p-p AC
GAIN – dB
100k 1M
–18 –24 –30 –36
20
–PSRR @ VDD = 3V DC 10% p-p AC
–42 –48
0
100
1k
10k FREQUENCY – Hz
–54 1k
10k 100k FREQUENCY – Hz
1M
TPC 15. Power Supply Rejection Ratio vs. Frequency
TPC 18. AD5201 10 k ? Gain vs. Frequency vs. Code
–8–
REV. B

AD5200/AD5201
6
0 –6 –12 10H 8H 4H 2H 1H
12
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
6 0 –6 –12 –18 –24 –30 –36 –42 –48 10
SEE TEST CIRCUIT 10 CODE = 80H VDD = 5V TA = 25 C 50k
10k
GAIN – dB
–18 –24 –30 –36 –42 –48 –54 1k
10k 100k FREQUENCY – Hz
1M
100
1k 10k FREQUENCY – Hz
100k
1M
TPC 19. AD5201 50 k ? Gain vs. Frequency vs. Code
TPC 22. Normalized Gain Flatness vs. Frequency
12
12
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
6 10k 0 –6 50k
6 0 –6
SEE TEST CIRCUIT 10 CODE = 10H VDD = 5V TA = 25 C 10k
GAIN – dB
–12 –18 –24 –30 –36 –42 –48 1k VIN = 100mV rms VDD = 5V RL = 1M
–12 50k –18 –24 –30 –36 –42 –48 10
10k 100k FREQUENCY – Hz
1M
100
1k 10k FREQUENCY – Hz
100k
1M
TPC 20. AD5200 –3 dB Bandwidth
TPC 23. AD5201 Normalized Gain Flatness vs. Frequency
12
6 10k 0 –6 50k
GAIN – dB
–12 –18 –24 –30 –36 –42 –48 1k VIN = 100mV rms VDD = 5V RL = 1M
VW (20mV/DIV)
CS (5V/DIV)
10k 100k FREQUENCY – Hz
1M
TPC 21. AD5201 –3 dB Bandwidth
TPC 24. One Position Step Change at Half Scale
REV. B
–9–

AD5200/AD5201
3500 3000 2500 2000 1500 1000 500 0
500
OUTPUT (2V/DIV)
INPUT (5V/DIV)
RHEOSTAT MODE TEMPCO – ppm/ C
0
32
64
96
128 160 CODE – Decimal
192
224
256
TPC 25. Large Signal Settling Time
TPC 28. AD5200 ?R WB/?T Rheostat Mode Temperature Coefficient
3000
POTENTIOMETER MODE TEMPCO – ppm/ C
2500
2000
VOUT (20mV/DIV)
1500 1000
500 0
–500 0
4
8
12 16 20 CODE – Decimal
24
28
32
TPC 26. Digital Feedthrough vs. Time
TPC 29. AD5201 Potentiometer Mode Temperature Coefficient
4000
POTENTIOMETER MODE TEMPCO – ppm/ C
3500 3000 2500 2000 1500 1000 500 0
500
50
POTENTIOMETER MODE TEMPCO – ppm/ C
0 32 64 96 128 160 CODE – Decimal 192 224 256
40
30 20
10
0
–10
–20
0
4
8
12 16 20 CODE – Decimal
24
28
32
TPC 27. AD5200 ?V WB /?T Potentiometer Mode Temperature Coefficient
TPC 30. AD5201 ?V WB/?T Potentiometer Mode Tempco
–10–
REV. B

AD5200/AD5201
100.0
Table I. AD5200 Serial-Data Word Format
B7 B6 D6 B5 D5 B4 D4 B3 D3 B2 D2 B1 D1 B0 D0 LSB 20
THEORETICAL IMAX – mA
10.0
D7 MSB
RAB = 10k
27
1.0
RAB = 50k
Table II. AD5201 Serial-Data Word Format
0.1
B5*
0 32 64 96 128 160 CODE – Decimal 192 224 256
B4 D4
B3 D3
B2 D2
B1 D1
B0 D0 LSB 20
D5* MSB 25
TPC 31. AD5200 I MAX vs. Code
100.0
*Six data bits are needed for 33 positions.
THEORETICAL IMAX – mA
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
10.0
RAB = 10k 1.0 RAB = 50k
0.1
0
4
8
16 12 20 CODE – Decimal
24
28
32
TPC 32. AD5201 I MAX vs. Code
OPERATION
The AD5200/AD5201 provide 255 and 33 positions digitallycontrolled variable resistor (VR) devices. Changing the programmed VR settings is accomplished by clocking in an 8-bit serial data word for AD5200, and a 6-bit serial data word for AD5201, into the SDI (Serial Data Input) pins. Table I provides the serial register data word format. The AD5200/AD5201 are preset to a midscale internally during power-on condition. In addition, the AD5200/AD5201 contain power shutdown SHDN pins that place the RDAC in a zero power consumption state where the immediate switches next to Terminals A and B are open-circuited. Meanwhile, the wiper W is connected to B terminal, resulting in only leakage current consumption in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. When the part is returned from shutdown, the stored VR setting will be applied to the RDAC.
The nominal resistance of the RDAC between Terminals A and B are available with values of 10 k? and 50 k?. The final two digits of the part number determine the nominal resistance value, e.g., 10 k? = 10 and 50 k? = 50. The nominal resistance (RAB) of AD5200 has 256 contact points accessed by the wiper terminal. The 8-bit data word in the RDAC latch of AD5200 is decoded to select one of the 256 possible settings. In both parts, the wiper’s first connection starts at the B terminal for data 00H. This B-terminal connection has a wiper contact resistance of 50 ? as long as valid VDD/VSS is applied, regardless of the nominal resistance. For a 10 k? part, the second connection of AD5200 is the first tap point with 89 ? [RWB = RAB/255 + RW = 39 ? + 50 ?] for data 01H. The third connection is the next tap point representing 78 + 50 = 128 ? for data 02H. Due to its unique internal structure, AD5201 has 5-bit + 1 resolution, but needs a 6-bit data word to achieve the full 33 steps resolution. The 6-bit data word in the RDAC latch is decoded to select one of the 33 possible settings. Data 34 to 63 will automatically be equal to Position 33. The wiper 00H connection of AD5201 gives 50 ?. Similarly, for a 10 k? part, the first tap point of AD5201 yields 363 ? for data 01H, 675 ? for data 02H. For both AD5200 and AD5201, each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached. Figures 2a and 2b show the simplified diagrams of the equivalent RDAC circuits.
REV. B
–11–

AD5200/AD5201
A SHDN D7 D6 D5 D4 D3 D2 D1 D0 SWSHDN SW2N 1
Note D in AD5200 is between 0 to 255 for 256 positions. On the other hand, D in AD5201 is between 0 to 32 so that 33 positions can be achieved due to the slight internal structure difference, Figure 2b. Again if RAB = 10 k? and A terminal can be opened or tied to W, the following output resistance between W to B will be set for the following RDAC latch codes:
W
R
SW2N 2
AD5200 Wiper-to-B Resistance
RAB 2N–1
R
SW1 R
RDAC LATCH & DECODER
R
SW0
D (DEC) 255 128 1 0
RWB ( ) 10050 5070 89 50
Output State Full-Scale (RAB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance)
B DIGITAL CIRCUITRY OMITTED FOR CLARITY
Figure 2a. AD5200 Equivalent RDAC Circuit. 255 positions can be achieved up to Switch SW 2N–1.
A SHDN SWSHDN SW2N
AD5201 Wiper-to-B Resistance
D (DEC) 32 16 1 0
RWB ( ) 10050 5050 363 50
Output State Full-Scale (RAB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance)
R D5 D4 D3 D2 D1 D0
SW2N 1
R
SW2N 2
R
SW1 R
W
RDAC LATCH & DECODER
R
SW0
RAB 2N
Note that in the zero-scale condition a finite wiper resistance of 50 ? is present. Care should be taken to limit the current flow between W and B in this state to no more than ± 20 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and Terminal A also produces a digitally controlled resistance RWA. When these terminals are used, the B terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is: RWA (D) =
B
DIGITAL CIRCUITRY OMITTED FOR CLARITY
Figure 2b. AD5201 Equivalent RDAC Circuit. Unlike AD5200, 33 positions can be achieved all the way to Switch SW 2N.
The general equation determining the digitally programmed output resistance between W and B is: RWB (D) =
RWB D =
D RAB + 50 ? 255
D RAB + 50 ? 32
for AD5200
(1)
(255 ? D) R
255
AB
+ 50 ?
for AD5200
(3)
( )
for AD5201
(2)
where: D is the decimal equivalent of the data contained in RDAC latch.
RAB is the nominal end-to-end resistance. RW is the wiper resistance contributed by the on-resistance of the internal switch.
for AD5201 (4) AB + 50 ? 32 Similarly, D in AD5200 is between 0 to 255, whereas D in AD5201 is between 0 to 32. For RAB = 10 k? and B terminal is opened or tied to the wiper W, the following output resistance between W and A will be set for the following RDAC latch codes:
RWA D =
( )
(32 ? D) R
–12–
REV. B

AD5200/AD5201
AD5200 Wiper-to-A Resistance
D (DEC) 255 128 1 0
RWA ( ) 50 5030 10011 10050
Output State Full-Scale (RW) Midscale 1 LSB Zero-Scale (RAB + RW)
Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors and not the absolute values; therefore, the drift reduces to 15 ppm/°C.
DIGITAL INTERFACING
AD5201 Wiper-to-A Resistance
D (DEC) 32 16 1 0
RWA ( ) 50 5050 9738 10050
Output State Full-Scale (RW) Midscale 1 LSB Zero-Scale (RAB + RW)
The AD5200/AD5201 contain a standard three-wire serial input control interface. The three inputs are clock (CLK), CS, and serial data input (SDI). The positive-edge-sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 3 shows more detail of the internal digital circuitry. When CS is low, the clock loads data into the serial register on each positive clock edge (see Table III).
VDD CS CLK SDI GND PWR-ON PRESET SER REG 8/6 Dx RDAC REG SHDN
AD5200/AD5201
VSS A W B
The tolerance of the nominal resistance can be ± 30% due to process lot dependance. If users apply the RDAC in rheostat (variable resistance) mode, they should be aware of such specification of tolerance. The change in RAB with temperature has a 500 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
Figure 3. Block Diagram
Table III. Input Logic Control Truth Table
The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A to B. Unlike the polarity of VDD – VSS, which must be positive, voltage across A–B, W–A, and W–B can be at either polarity. If ignoring the effects of the wiper resistance for an approximation, connecting A terminal to 5 V and B terminal to ground produces an output voltage at the wiper which can be any value starting at almost zero to almost full scale with the minor deviation contributed by the wiper resistance. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 2N-1 and 2N position resolution of the potentiometer divider for AD5200 and AD5201 respectively. The general equation defining the output voltage with respect to ground for any valid input voltage applied to Terminals A and B is: VW (D) = VW (D) = D VAB + VB 255 D VAB + VB 32 for AD5200 (5) CLK L P X X X
CS L L P H H
SHDN H H H H L
Register Activity No SR effect. Shift one bit in from the SDI pin. Load SR data into RDAC latch. No operation. Open circuit on A terminal and short circuit between W to B terminals.
NOTE P = positive edge, X = don’t care, SR = shift register.
All digital inputs are protected with a series input resistor and parallel Zener ESD structure shown in Figure 4. Applies to digital input pins CS, SDI, SHDN, CLK.
340 LOGIC
for AD5201
(6)
VSS
Figure 4. ESD Protection of Digital Pins
where D in AD5200 is between 0 to 255 and D in AD5201 is between 0 to 32. For more accurate calculation, including the effects of wiper resistance, VW can be found as:
VW D =
A,B,W
VSS
( )
RWB D RAB
( )V
A
+
RWA D RAB
( )V
Figure 5. ESD Protection of Resistor Terminals
B
(7)
where RWB(D) and RWA(D) can be obtained from Equations 1 to 4.
REV. B
–13–

AD5200/AD5201
TEST CIRCUITS
Figures 6 to 14 define the test conditions used in the product specification table.
DUT A V+ B W VMS V+ = VDD 1 LSB = V+/2N
OFFSET GND VIN W
5V
OP279
VOUT
A
DUT
B
OFFSET BIAS
Figure 6. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)
NO CONNECT DUT A W B VMS IW
Figure 11. Noninverting Gain Test Circuit
A W VIN OFFSET GND B 2.5V
+15V
OP42 –15V
VOUT
Figure 7. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Figure 12. Gain vs. Frequency Test Circuit
DUT
DUT VMS2 A W B VMS1 VW IW = VDD/RNOMINAL
RSW =
0.1V ISW
W B ISW
CODE = OOH + 0.1V –
VSS TO VDD
RW = [VMS1 – VMS2]/IW
Figure 8. Wiper Resistance Test Circuit
Figure 13. Incremental ON Resistance Test Circuit
NC
VA VDD V+ B VMS
VDD DUT A W GND B ICM
A W
V+ = VDD
10% VMS VDD
VSS
PSRR (dB) = 20 LOG PSS (%/%) = VMS% VDD%
VCM
NC NC = NO CONNECT
Figure 9. Power Supply Sensitivity Test Circuit (PSS, PSRR)
Figure 14. Common-Mode Leakage Current Test Circuit
A
DUT B 5V W
VIN OFFSET GND
OP279
VOUT
OFFSET BIAS
Figure 10. Inverting Gain Test Circuit
–14–
REV. B

AD5200/AD5201
DIGITAL POTENTIOMETER SELECTION GUIDE
Number of VRs per Package 1 Terminal Voltage Range ± 3 V, +5.5 V 5.5 V ± 15 V, +28 V ± 3 V, +5.5 V 5.5 V ± 3 V, +5.5 V ± 3 V, +5.5 V ± 3 V, +5.5 V 5.5 V ± 3 V, +5.5 V ± 3 V, +5.5 V ± 5 V, +12 V 5.5 V ± 3 V, +5.5 V ± 3 V, +5.5 V 5.5 V ± 3 V, +5.5 V Interface Data Control 3-Wire Nominal Resistance (k ) 10, 50 Resolution (Number Of Wiper Positions) 33 Power Supply Current (IDD) 60 μA 40 μA 100 μA 60 μA 5 μA 5 μA 10 μA 80 μA 5 μA 10 μA 5 μA 60 μA 5 μA 10 μA 5 μA 5 μA 5 μA
Part Number AD5201
Packages μSOIC-10 PDIP, SO-8, μSOIC-8 PDIP-14, SOL-16, TSSOP-14 μSOIC-10 SO-8 SO-14, TSSOP-14
Comments Full AC Specs, Dual Supply, Pwr-On-Reset, Low Cost No Rollover, Pwr-On-Reset Single 28 V or Dual ± 15 V Supply Operation Full AC Specs, Dual Supply, Pwr-On-Reset Full AC specs I2C-Compatible, TC < 50 ppm/°C Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability No Rollover, Stereo, Pwr-OnReset, TC < 50 ppm/°C Full AC Specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability I2C-Compatible, TC < 50 ppm/°C Medium Voltage Operation, TC < 50 ppm/°C Full AC specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability Full AC Specs, Dual Supply, Pwr-On-Reset Full AC Specs, nA Shutdown Current Full AC Specs, Dual Supply, Pwr-On-Reset
AD5220 AD7376
1 1
Up/Down 3-Wire
10, 50, 100 10, 50, 100, 1000
128 128
AD5200
1
3-Wire
10, 50
256
AD8400
1
3-Wire 2-Wire
1, 10, 50, 100 10, 100, 1000
256 256
AD5241* 1
AD5231* 1
3-Wire
10, 50, 100
1024
TSSOP-16
AD5222
2
Up/Down
10, 50, 100, 1000
128
SO-14, TSSOP-14
AD8402
2
3-Wire
1, 10, 50, 100
256
PDIP, SO-14, TSSOP-14 TSSOP-16
AD5232* 2
3-Wire
10, 50, 100
256
AD5242* 2
2-Wire
10, 100, 1000
256
SO-16, TSSOP-16
AD5262* 2
3-Wire
10, 50, 100
256
TSSOP-16
AD5203
4
3-Wire
10, 100
64
PDIP, SOL-24, TSSOP-24 TSSOP-16
AD5233* 4
3-Wire
10, 50, 100
64
AD5204
4
3-Wire
10, 50, 100
256
PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24
AD8403
4
3-Wire
1, 10, 50, 100
256
AD5206
6
3-Wire
10, 50, 100
256
*Future product, consult factory for latest status.
REV. B
–15–

AD5200/AD5201
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10-Lead SOIC (RM-10)
0.124 (3.15) 0.112 (2.84)
10
6
0.124 (3.15) 0.112 (2.84)
1 5
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0197 (0.50) BSC 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 6 SEATING 0.006 (0.15) 0.016 (0.41) PLANE 0 0.022 (0.56) 0.011 (0.28) 0.002 (0.05) 0.006 (0.15) 0.021 (0.53) 0.003 (0.08) 0.122 (3.10) 0.110 (2.79)
0.038 (0.97) 0.030 (0.76)
Revision History
Location Data Sheet changed from REV. A to REV. B. Page
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
02/01—Data Sheet changed from REV. O to REV. A.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TPCs 31 and 32 added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PRINTED IN U.S.A.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
–16–
REV. B
C02188–0–8/01(B)