外国大学物理演示实验8
Fabrication of samples for scanning probe experiments on quantum spin Hall effect in HgTe quantum wells
M. Baenninger, M. K?nig, A. G. F. Garcia, M. Mühlbauer, C. Ames et al.
Citation: J. Appl. Phys. 112, 103713 (2012); doi: 10.1063/1.4767362
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Fabrication of samples for scanning probe experiments on quantum spin Hall effect in HgTe quantum wells
M.Baenninger,1M.K€o nig,1A.G.F.Garcia,1M.M€u hlbauer,2C.Ames,2P.Leubner,2
C.Br€u ne,2H.Buhmann,2L.W.Molenkamp,2and
D.Goldhaber-Gordon1
1Department of Physics,Stanford University,Stanford,California94305,USA
2Physikalisches Institut(EP3)and R€o ntgen Center for Complex Material Systems,Universit€a t W€u rzburg,
Am Hubland,97074W€u rzburg,Germany
(Received8September2012;accepted26October2012;published online28November2012)
We present a fabrication process for devices on HgTe quantum wells through which the quantum
spin Hall regime can be reached without the use of a top-gate electrode.We demonstrate that a
nominally undoped HgTe quantum well can be tuned from p-type to n-type,crossing through the
quantum spin Hall regime,using only a back-gate hundreds of microns away.Such structures will
enable scanning probe investigations of the quantum spin Hall effect that would not be possible in
the presence of a gate electrode on the surface of the wafer.All processes are kept below80 C to
avoid degradation of the heat-sensitive HgTe quantum wells.V C2012American Institute of Physics.
[https://www.wendangku.net/doc/d018912970.html,/10.1063/1.4767362]
INTRODUCTION
The quantum spin Hall(QSH)effect has attracted a lot of attention in the condensed matter community since its theoret-ical prediction1–3and experimental demonstration4soon after. One of the most intriguing predictions for the QSH effect is that ballistic transport should occur in edge states even at zero magnetic?eld.While there has been convincing indirect evi-dence that this is,indeed,the case,4,5there has been no direct imaging of the current?ow along the edges.Scanning probe microscopy(SPM)experiments such as scanning gate micros-copy,6scanning SQUID microscopy,7or microwave imped-ance microscopy8could not only provide direct evidence of the quantum spin Hall edge states but also probe various aspects of the helical edge states on a local scale.However, all QSH experiments to date have been carried out in n-doped wafers,where the QSH regime was only reached by depleting the bulk carriers in the quantum well with a top-gate elec-trode.This approach is not practical for most scanning probe experiments since the metal on the surface would screen the interactions between the probe and the quantum well.In this communication,we describe a method for fabricating devices suitable to study the QSH effect with scanning probes. FABRICATION
Fabricating microstructures on HgTe/HgCdTe quantum wells pose substantial challenges:The heterostructures are very sensitive to heat and need to be kept at T80 C at all times during processing to avoid interdiffusion of well and barrier materials.9This makes it impossible to use many standard processes for optical and electron beam lithography, where the resist usually has to be baked at T>80 C.Other challenges include the softness of the material,which makes wirebonding and general handling dif?cult,and the reactivity of HgTe/HgCdTe with other materials.10In the following paragraphs,we describe a low-temperature fabrication pro-cess for microstructures on HgTe quantum wells using opti-cal lithography.
We start with heterostructures grown by molecular beam epitaxy on a(100)Cd0.96Zn0.04Te(below referred to as CdZnTe)or CdTe substrate.11,12The layer structure bottom up consists of a CdTe buffer,a Hg0.3Cd0.7Te(below referred to as HgCdTe)layer followed by a thin HgTe layer(the quan-tum well),and?nally a HgCdTe cap of15–100nm.The band structure is normal for quantum well widths d QW<6.3nm but inverted for d QW>6.3nm and,therefore,appropriate for the quantum spin Hall effect.4Iodine doping can be intro-duced on either side of the quantum well,but this paper focuses on undoped wafers.The?rst step in fabrication of a HgTe quantum well device from a wafer is to de?ne a mesa. There are few wet etchants for HgTe/HgCdTe,and the com-monly used Br2in ethylene glycol is problematic due to its toxicity and its isotropic etch behavior that tends to undercut the etch mask and make a reproducible process dif?cult.9 Therefore,we used Ar ion milling.While undercut does not generally occur in ion mill patterning,one commonly encountered problem is side wall re-deposition along the edge of a mesa.In scanning probe experiments,the resulting “fences”which protrude above the mesa edge(see Figs.1(c) and1(d))can affect the coupling of the scanning probe to the quantum well,leading to measurement artifacts,and can also cause the probe to crash.This may require a larger separation of the probe from the device,limiting sensitivity and resolu-tion.We developed an ion milling process that avoids this problem by etching at an optimized angle on a rotating stage as described below.The patterning is done with optical li-thography,using the photoresist as an etch mask.We spin Shipley3612at5500rpm,bake it for2min on an80 C hot-plate,then expose it for5s at a UV intensity of10mW/cm2 and develop in Microposit CD-30developer for30s.The ion milling is done at a beam voltage V b?150V and intensity J b%0.1mA/cm2at an angle h?20 off the normal on a stage rotating at30rpm.The samples are mounted with a thermally conductive silver paste to the stage that is cooled to T stage?5 C to avoid overheating.After etching,the photore-sist is removed in hot acetone(50 C)and ultrasonic bath.
0021-8979/2012/112(10)/103713/6/$30.00V C2012American Institute of Physics
112,103713-1
JOURNAL OF APPLIED PHYSICS112,103713(2012)
The ion mill settings were optimized to get a highly reproduc-ible etch rate of 7–8nm/min and minimal fencing,as shown in Figs.1(a)and 1(b)in atomic force microscope (AFM)and scanning electron microscope (SEM)images,respectively.In contrast,Figs.1(c)and 1(d)show the strong buildup along the mesa edge typical for non-optimum settings.
The next step is the fabrication of ohmic contacts to the quantum well layer.The optical lithography is done in the same way as described above.For shallow quantum wells ( 30nm below the surface),a sequence of 50nm AuGe eutectic (88:12wt.%),5nm Ti,and 50nm Au is evaporated directly after the photolithography,in an electron beam evaporator (base pressure <5?10à7Torr)with liquid nitro-gen cooled stage (à30 C T stage à10 C)followed by a lift-off in hot acetone and a short time in the ultrasonic bath.For deeper quantum wells,an ion milling step is added after the lithography to locally reduce the cap layer thickness to <30nm.After that,the same metallization and lift-off are carried out.No annealing step is required in this process to achieve a good ohmic contact (R Contact 500X )to the quan-tum well.An alternative way of fabricating patterned ohmic contacts is to thermally evaporate 50nm of indium followed by 50nm of gold.In this process,quantum wells as deep as 80nm have been contacted without etching or annealing,but it is dif?cult to wirebond to the contacts as described below.
Although the main focus of this article is on devices without top-gate electrode,we also include the description of a process for fabricating top-gates.Top-gated devices can be used for a wide range of experiments without scanning probe but also for certain scanning probes that do not couple elec-trically such as scanning SQUID microscopy.HgCdTe does not generally build a good Schottky barrier with metals,therefore,a gate insulator is required between the wafer sur-face and the metal.We use low temperature atomic layer deposition (ALD)of Al 2O 3as gate dielectric,where we reduce the chamber temperature to 60 C from the usual 110–120 C but increase the exposure times from 0to 5s and pump times from 5s to 30–50s.An Al 2O 3layer of %40nm was found to withstand several volts on the topgate.This
gate dielectric is only about one third of the thickness used in previously reported Si-O-N insulator layers.13Optical li-thography for the topgate is done with the same process as described above.It is important to use a passivized developer such as Microposit CD-30that does not strongly etch the Al 2O 3(CD-26is in fact a convenient etchant for Al 2O 3).As an extra precaution,care is taken not to overdevelop the resist and the devices are rinsed extensively in DI water after developing,in order to avoid extended exposure of the Al 2O 3to the developer.Metallization of 20nm/100nm Ti/Au is done in an e-beam evaporator with liquid nitrogen cooled stage (à30 C T stage à10 C)followed by a liftoff in hot acetone.
The devices are mounted onto a chip carrier with GE-varnish or silver paint.Wirebonding to the contacts can be dif?cult on HgTe/HgCdTe heterostructures.While AuGe/Ti/Au ohmics can be bonded to with a wedge bonder,although with reduced power,this does not work for In/Au ohmics or Ti/Au gate contacts,due to the softness of the HgCdTe and poor adhesion of the metal.For those contacts,a different method is used,where a wire is bonded on the chip carrier with the wedge bonder but the second bond is placed on the chip with zero ultrasound power,which cuts the wire without damaging the surface of the device.A 200l m diameter indium dot is then placed on the contact with a tweezers tip and the wire end is squeezed manually into the indium.This technique leads to a mechanically robust and electrically reliable contact that survives multi-ple thermal cycles to 4K.The spacing between contacts needs to be larger than with normal wirebonding,but contacts at a 500l m pitch can be bonded quite comfortably after some practice.
RESULTS
We now present experimental results that demonstrate that nominally undoped HgTe quantum wells can be tuned from p-type to n-type with only a backgate,thereby crossing the quantum spin Hall regime in the case of
inverted
FIG.1.Mesa etching without fencing:(a)A line cut through an AFM image and (b)a SEM image,respec-tively,of a mesa edge etched with the settings V b ?150V,j b %0.1mA/cm 2,and h ?20 off the nor-mal,which were found to produce a fenceless mesa with an etch rate of 7–8nm/min very reproducibly.(c)and (d)show the same,but for a mesa edge with strong fencing due to non-optimum ion mill settings.In (c),the beam voltage was V b ?300V,beam current density j b %0.33mA/cm 2,and the angle h ?5 ,in (d)V b ?300V,j b %0.2mA/cm 2,and h ?15 .
band structure.Devices used in these experiments were 50l m?30l m Hall bars as shown in an optical microscope image in Fig.2(a),fabricated with the process described above but without a topgate electrode.The device used here was made from a wafer with a7nm HgTe quantum well below a50nm HgCdTe cap.It was glued with a thin layer of GE-varnish onto the metallic surface of a chip carrier,which acted as a backgate electrode,separated from the quantum well by about800l m of CdTe substrate.Transport measure-ments were carried out with the sample immersed in liquid he-lium at 4.2K with standard lock-in techniques.Fig.2(b) shows the4-probe longitudinal resistance as a function of backgate voltage.There is a clear maximum with resistance of100–120k X at V bg?0–50V,which indicates that the de-vice can be tuned from p-type at large negative V bg through the QSH regime to n-type at large positive V bg.Our gate sweeps show a quite strong hysteresis but after a slight shift between the?rst and second loops,subsequent hysteresis loops were very reproducible in their overall shape.However, there are?uctuations of about10%of the resistance,which are not reproducible.These?uctuations can be reduced by sweeping very slowly,and they completely disappear when the backgate is kept at a?xed voltage.We attribute the?uctu-ations to charging events at one of the layer interfaces between the backgate and the quantum well.13Interface charging can also explain the hysteresis and the weakening of the backgate effect observed in several devices when applying |V bg|>200V(not shown).While the appearance of a resist-ance maximum as a function of backgate voltage indicates tuning from p-to n-type,Hall measurements give unequivocal evidence of a change in the sign of the charge carriers. Figs.2(c)and2(d)show the low?eld longitudinal and trans-verse magnetoresistance at V bg?6210V,respectively.The negative slope in the Hall resistance at V bg?à210V shows that the charge carriers are positive,i.e.,holes,whereas the positive slope at V bg?210V shows that the carriers are elec-trons.The extracted densities of p%6?1010cmà2at V bg?à210V and n%5?1010cmà2at V bg?210V are con-sistent with the location of the resistance maximum at slightly positive backgate voltage although the total change in density is almost a factor of4larger than expected from the capacitor model discussed below.We believe that the extracted den-sities are substantially higher than the real density.A system-atic overestimate of the density determined from the slope
of FIG. 2.Demonstration of QSH effect with backgate:(a)Optical micrograph of a typical Hall bar device with ohmic contacts.(b)Longitudinal resistance as a fuction of backgate voltage measured at 4K in a4-probe measurement con?gura-tion.A maximum with?nite resistance R max?100–120k X indicates that the device can be tuned through the QSH re-gime.(c)and(d)Longitudinal and trans-verse low?eld magnetoresistance at V bg?6210V.The change in sign of the Hall slope demonstrates a change from p-type to n-type and,therefore,tuning through the gap.(e)and(f)The clear non-local resistance for two different con?gurations provides very strong evi-dence of edge state stransport at V bg%0 and therefore the QSH regime.
the Hall resistance can be explained by the onset of localiza-tion effects in the low-density regime.14The non-linear fea-ture in R xy atà0.1T
We found experimentally that a backgate voltage change fromà200V tot200V across an800l m thick CdTe sub-strate only changes the density by D n5?1010cmà2.The substrate breaks down under a voltage of%450V,but the density saturates at lower voltages so that for|V bg|>200V,the achieved density change is substantially reduced.This means that the as-grown density of the wafer needs to be 2.5?1010cmà2for the QSH regime to be reachable with the backgate.Unfortunately,nominally undoped HgTe quan-tum wells tend to be p-type,sometimes substantially (p>1011cmà2)depending on growth conditions,most likely due to Hg vacancies in the HgCdTe.This limits the wafers that are suitable for scanning probe investigations of the QSH effect.In order to increase the density range that can be accessed with a backgate,we investigated thinning of the substrate to bring the backgate closer to the quantum well. The fabrication process for thinned-substrate devices is as follows:First,a regular device is fabricated with the process described above.The device is glued face down onto a glass slide with superglue and then mechanically lapped from the back to a thickness of about100l m.After thinning,the glue is dissolved in hot acetone and the device is?ipped over and transferred to a new substrate:a silicon chip slightly larger than the HgTe device,on which Ti/Au was evaporated followed by deposition of2000cycles of ALD Al2O3 (%200nm).The Ti/Au serves as a backgate electrode and the thick Al2O3layer is required as a strong insulator that allows application of>200V to the backgate even though the 100l m CdTe substrate would break down at much lower voltages.The thinned device is glued onto the prepared sub-strate with a thin layer(1l m)of PMMA and then both are mounted on a chip carrier.A schematic diagram of a thinned device mounted on a backgate/substrate is shown in Fig. 3(a),and an optical micrograph of a thinned,mounted Hall bar device is shown in Fig.3(b).
Fig.3(c)compares the density dependence on backgate voltage for a normal and a thinned device,where the den-sities were obtained from the low?eld Hall resistance.The two devices discussed here were made from two different, nominally undoped wafers,with a25nm HgCdTe cap layer and QW thickness of8nm(thinned device)and7nm (unthinned device),respectively.The blue data in Fig.3(c) show a typical gating behavior of an unthinned device with a relatively high as-grown p-type density.A simple plate ca-pacitor model predicts the relation between V bg and charge density to be p?C0(V bgàV0)with C0?e0e/ed,where e0e are the dielectric constants,e is the electron charge,and d is the separation between the backgate and the quantum well. With e(CdTe)%10.2(Ref.16)and d%800l m,the predicted C0%7?107Và1cmà2is smaller than the slope C%1.1?108Và1cmà2obtained from a linear?t to the data.We consistently found that the experimental C was larger than the theoretical C0with the deviation varying from30%to 70%.A systematic error in the measured density as discussed above can be ruled out since the data were taken in the higher density regime,where the Hall slope gives reliable density values.We do not have a good explanation for this deviation from the theoretical model at this point.The red data in Fig.3(c)show the backgate characteristics for a de-vice that was thinned to about100l m.Here,the slope is C%5.4?108Và1cmà2,almost a factor of5higher than for the typical unthinned device.The total measured change in density D p%1.98?1011cmà2is about4.5times more than D p%4.43?1010cmà2in the unthinned device.The
effective D p in the thinned device might even be a bit larger,since the density point at V bg ?210V is not reliable due to the systematic error near the localization transition and this point was excluded from the linear ?t.Indeed,the Hall resist-ance shows a zero ?eld offset that is not expected for the Hall effect in the metallic regime (not shown)and the longi-tudinal resistivity shown in Fig.3(d)is larger than h/e 2indi-cating the transition to the localized regime.Further support that the density does not really saturate comes from the de-pendence of resistance on gate voltage shown in Fig.3(d),which continues to increase up to V bg ?210V without any sign of saturation.The resistance trace is stable and only shows a weak hysteresis,con?rming the good quality of the backgate.The CdZnTe substrates are very brittle and prone to breaking apart during thinning.For a successful thinning,the device needs to be attached to the glass slide very well but great care has to be taken not to damage to soft topside of the wafer.We found that it is very important that the thinned chips have very clean edges,otherwise the device starts to break off starting from cracks at the edge.We man-aged to improve the yield substantially with these steps but a risk remained that the device could be damaged during thin-ning as can be seen for the chip in Fig.3(b),where parts of the device broke off during thinning.More work is required to improve the yield but our results demonstrate the potential that substrate thinning has to improve the backgate ef?ciency.
CONCLUSION
We have presented a low-temperature process for fabri-cation of microstructures on HgTe quantum well wafers.We demonstrate that for quantum wells with low as-grown den-sity,the quantum wells can be tuned into the quantum spin Hall regime without a topgate,opening up a path to a wide range of scanning probe experiments.We also show that thinning of the wafer substrate can increase the density change achievable with a backgate several times,potentially
allowing higher as-grown density wafers to be tuned into the QSH regime.
ACKNOWLEDGMENTS
The process development for fabrication of devices suit-able for scanning probe experiments was supported by the NSF Center for Probing the Nanoscale under Grant No.PHY-0830228.Characterization of undoped wafers and demonstration of QSH in backgated devices were supported by the DARPA Meso project under Grant No.N66001-11-1-4105.Part of this work was performed at the Stanford Nano Center (SNC)part of the Stanford Nano Shared Facilities.The mechanical substrate thinning was carried out by the Ginzton Crystal Shop at Stanford.We thank Adam Sciambi for advice on substrate thinning and indium bonding,and Reyes Calvo,Katja Nowack and Eric Spanton for useful discussions.
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