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SCAN18541TSSCX中文资料

? 2000 Fairchild Semiconductor Corporation DS010965

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October 1991Revised April 2000

SCAN18541T Non-Inverting Line Driver with 3-STATE Outputs

SCAN18541T

Non-Inverting Line Driver with 3-STATE Outputs

General Description

The SCAN18541T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control sig-nals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).

Features

s IEEE 1149.1 (JTAG) Compliant s Dual output enable signals per byte

s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications

s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive 50? transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs

s 25 mil pitch SSOP (Shrink Small Outline Package)s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN Products

Ordering Code:

Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.

Connection Diagram Pin Names

Truth Tables

H = HIGH Voltage Level X = Immaterial

L = LOW Voltage Level

Z = High Impedance

Order Number Package Number

Package Description

SCAN18541TSSC

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Pin Names Description

AI (0–8)Input Pins, A Side BI (0–8)

Input Pins, B Side

AOE 1, AOE 23-STATE Output Enable Input Pins, A Side BOE 1, BOE 23-STATE Output Enable Input Pins, B Side

AO (0–8)Output Pins, A Side AO (0–8)

Output Pins, B Side

Inputs

AO (0–8)

AOE 1AOE 2AI (0–8)L L H H H X X Z X H X Z L

L L

L Inputs

BO (0–8)

BOE 1BOE 2BI (0–8)L L H H H X X Z X H X Z L

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S C A N 18541T

Block Diagrams

Byte A

Tap Controller

Byte B

Note: BSR stands for Boundary Scan Register.

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Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are

one of the following two types depending upon their loca-

tion. Scan cell TYPE1 is intended to solely observe system

data, while TYPE2 has the additional ability to control sys-

tem data.

Scan cell TYPE1 is located on each system input pin while

scan cell TYPE2 is located at each system output pin as

well as at each of the two internal active-high output enable

signals. AOE controls the activity of the A-outputs while

BOE controls the activity of the B-outputs. Each will acti-

vate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage

identical to scan cell TYPE1. It captures a fixed logic low.

Bypass Register Scan Chain Definition

Logic 0

The INSTRUCTION register is an 8-bit register which cap-

tures the default value of 10000001. The two least signifi-

cant bits of this captured value (01) are required by IEEE

Std 1149.1. The upper six bits are unique to the

SCAN18541T device. SCAN CMOS Test Access Logic

devices do not include the IEEE 1149.1 optional identifica-

tion register. Therefore, this unique captured value can be

used as a “pseudo ID” code to confirm that the correct

device is placed in the appropriate location in the boundary

scan chain.

Instruction Register Scan Chain Definition

MSB→LSB

Scan Cell TYPE1

Scan Cell TYPE2

Instruction Code Instruction

00000000EXTEST

10000001SAMPLE/PRELOAD

10000010CLAMP

00000011HIGH-Z

All Others BYPASS

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S C A N 18541T

Description of Boundary-Scan Circuitry

(Continued)

Boundary-Scan Register

Scan Chain Definition (42 Bits in Length)

SCAN18541T Description of Boundary-Scan Circuitry (Continued)

Boundary-Scan Register Definition Index

Bit No.Pin Name Pin No.Pin Type Scan Cell Type

41AOE13Input TYPE1Control

Signals

40AOE254Input TYPE1

39AOE Internal TYPE2

38BOE126Input TYPE1

37BOE231Input TYPE1

36BOE Internal TYPE2

35AI055Input TYPE1A–in

34AI153Input TYPE1

33AI252Input TYPE1

32AI350Input TYPE1

31AI449Input TYPE1

30AI547Input TYPE1

29AI646Input TYPE1

28AI744Input TYPE1

27AI843Input TYPE1

26BI042Input TYPE1B–in

25BI141Input TYPE1

24BI239Input TYPE1

23BI338Input TYPE1

22BI436Input TYPE1

21BI535Input TYPE1

20BI633Input TYPE1

19BI732Input TYPE1

18BI830Input TYPE1

17AO02Output TYPE2A–out

16AO14Output TYPE2

15AO25Output TYPE2

14AO37Output TYPE2

13AO48Output TYPE2

12AO510Output TYPE2

11AO611Output TYPE2

10AO713Output TYPE2

9AO814Output TYPE2

8BO015Output TYPE2B–out

7BO116Output TYPE2

6BO218Output TYPE2

5BO319Output TYPE2

4BO421Output TYPE2

3BO522Output TYPE2

2BO624Output TYPE2

1BO725Output TYPE2

0BO827Output TYPE2

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S C A N 18541T

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with-out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of SCAN circuits outside databook specifications.

DC Electrical Characteristics

Supply Voltage (V CC )?0.5V to +7.0V

DC Input Diode Current (I IK )V I = ?0.5V ?20 mA V I = V CC +0.5V

+20 mA

DC Output Diode Current (I OK )V O = ?0.5V ?20 mA V O = V CC +0.5V +20 mA

DC Output Voltage (V O )

?0.5V to V CC +0.5V

DC Output Source/Sink Current (I O )±70 mA DC V CC or Ground Current Per Output Pin ±70 mA Junction Temperature SSOP

+140°C

Storage Temperature ?65°C to +150°C

ESD (Min)

2000V Supply Voltage (V CC )SCAN Products 4.5V to 5.5V Input Voltage (V I )0V to V CC Output Voltage (V O )0V to V CC

Operating Temperature (T A )?40°C to +85°C

Minimum Input Edge Rate ?V/?t 125 mV/ns

V IN from 0.8V to 2.0V V CC @ 4.5V, 5.5V

Symbol Parameter

V CC T A = +25°C T A = ?40°C to +85°C Units Conditions (V)Typ Guaranteed Limits

V IH Minimum HIGH 4.5 1.5 2.0 2.0V V OUT = 0.1V Input Voltage 5.5 1.5 2.0 2.0or V CC ?0.1V V IL Maximum LOW 4.5 1.50.80.8V V OUT = 0.1V Input Voltage 5.5 1.5

0.80.8or V CC ?0.1V V OH

Minimum HIGH 4.5 3.15 3.15V I OUT = ?50 μA Output Voltage 5.5 4.15 4.15(Note 3)

4.5 2.4 2.4V V IN = V IL or V IH

5.5 2.4 2.4

I OH = ?32 mA 4.5 2.4V

V IN = V IL or V IH 5.5

2.4I OH = ?24 mA

V OL

Maximum LOW 4.50.10.1V I OUT = 50 μA Output Voltage 5.50.10.1(Note 3)

4.50.550.55V V IN = V IL or V IH

5.50.550.55

I OL = 64 mA 4.50.55V V IN = V IL or V IH 5.5

0.55I OL = 48 mA I IN Maximum Input Leakage Current 5.5±0.1±1.0μA V I = V CC , GND I IN Maximum Input 5.5

2.8

3.6μA V I = V CC TDI,TMS

Leakage ?385?385μA V I = GND Minimum Input 5.5?160?160μA V I = GND Leakage

I OLD Minimum Dynamic 5.59494mA V OLD = 0.8V Max I OHD Output Current (Note 2)

?40?40mA V OHD = 2.0V Min I OZ Maximum Output Leakage Current 5.5±0.5±5.0μA V I (OE) = V IL , V IH I OS Output Short 5.5?100

?100mA V O = 0V

Circuit Current (min)I CC

Maximum Quiescent 5.516.088μA V O = Open Supply Current

TDI, TMS = V CC 5.5

750

820

μA

V O = Open TDI, TMS = GND

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SCAN18541T

DC Electrical Characteristics (Continued)

Note 2: Maximum test duration 2.0 ms, one output loaded at a time.Note 3: All outputs loaded; thresholds associated with output under test.

Noise Specifications

Note 4: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW.Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH.Note 6: Worst case package.

Note 7: Maximum number of data inputs (n) switching. (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (V ILD ).

AC Electrical Characteristics

Normal Operation:

Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.

Symbol Parameter

V CC T A = +25°C T A = ?40°C to +85°C Units Conditions (V)Typ

Guaranteed Limits

I CCt

Maximum I CC 5.5

2.0

V I = V CC –2.1V Per Input

5.5

2.15

V I = V CC –2.1V TDI/TMS Pin,Test One with the Other Floating

Symbol Parameter

V CC T A = +25°C

T A = ?40°C to +85°C

Units (V)Typ Guaranteed Limits

V OLP Maximum HIGH Output Noise 5.0 1.0 1.5V (Note 4)(Note 5)

V OLV Minimum LOW Output Noise 5.0?0.6?1.2V (Note 4)(Note 5)V OHP Maximum Overshoot 5.0V OH +1.0V OH +1.5V (Note 4)(Note 6)V OHV Minimum V CC Droop 5.0V OH ?1.0V OH ?1.8V (Note 4)(Note 6)

V IHD Minimum HIGH Dynamic Input 5.5 1.6 2.0 2.0V Voltage Level (Note 6)(Note 7)V ILD

Maximum LOW Dynamic Input 5.5

1.4

0.8

Voltage Level (Note 6)(Note 7)

Symbol Parameter

V CC

T A = +25°C T A = ?40°C to +85°C

Units

(V)C L = 50 pF

C L = 50 pF (Note 8)Min Typ

Max Min Max t PLH ,Propagation Delay 5.0 2.59.0 2.59.8ns t PHL Data to Q 2.59.0 2.59.8t PLZ ,Disable Time 5.0 1.510.2 1.510.7ns t PHZ 1.510.2 1.510.7t PZL ,Enable Time

5.0

2.011.8 2.012.8ns t PZH

2.0

9.5

2.0

10.5

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S C A N 18541T

AC Electrical Characteristics

Scan Test Operation:

Note: All Propagation Delays involving TCK are measured from the falling edge of TCK.Note 9: Voltage Range 5.0 is 5.0V ± 0.5V.

Symbol Parameter

V CC

T A = +25°C T A = ?40°C to +85°C

Units

(V)C L = 50 pF

C L = 50 pF (Note 9)Min Typ

Max Min Max t PLH ,Propagation Delay 5.0 3.513.2 3.514.5ns t PHL TCK to TDO 3.513.2 3.514.5t PLZ ,Disable Time 5.0 2.511.5 2.511.9ns t PHZ TCK to TDO 2.511.5 2.511.9t PZL ,Enable Time 5.0

3.01

4.5 3.01

5.8ns t PZH TCK to TDO 3.014.5 3.015.8t PLH ,Propagation Delay 5.0

18.0 5.019.8t PHL TCK to Data Out 5.0 5.018.0 5.019.8ns During Update-DR State t PLH ,Propagation Delay 5.0

18.6 5.020.2t PHL TCK to Data Out 5.0 5.0

18.6

5.0

20.2

ns During Update-IR State t PLH ,Propagation Delay t PHL

TCK to Data Out 5.0 5.519.9 5.521.5ns

During Test Logic 5.519.9 5.521.5Reset State

t PLZ ,Propagation Delay 4.0

16.4 4.018.2t PHZ TCK to Data Out 5.0 4.016.4 4.018.2ns

During Update-DR State t PLZ ,Propagation Delay 5.0

19.5 5.020.8t PHZ TCK to Data Out 5.0 5.019.5

5.0

20.8

During Update-IR State t PLZ ,Propagation Delay t PHZ

TCK to Data Out 5.0 5.019.9 5.021.5ns

During Test Logic 5.019.9 5.021.5Reset State

t PZL ,Propagation Delay 5.0

18.9 5.020.9t PZH TCK to Data Out 5.0 5.018.9 5.020.9ns

During Update-DR State t PZL ,Propagation Delay 6.5

22.4 6.524.2t PZH TCK to Data Out 5.0 6.522.4

6.5

24.2

During Update-IR State t PZL ,Propagation Delay t PZH

TCK to Data Out 5.07.023.87.025.7ns

During Test Logic 7.0

23.8

7.0

25.7

Reset State

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SCAN18541T

AC Operating Requirements

Scan Test Operation:

Note: All Input Timing Delays involving TCK are measured from the rising edge of TCK.Note 10: Voltage Range 5.0 is 5.0V ± 0.5V.

Note 11: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35.Note 12: Timing pertains to BSR 37, 38, 40 and 41 only.

Note 13: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only.

Symbol Parameter

V CC

T A = +25°C T A = ?40°C to +85°C

Units

(V)C L = 50 pF

C L = 50 pF

(Note 10)Guaranteed Minimum

t S Setup Time, H or L 5.0 3.0 3.0ns Data to TCK (Note 11)t H Hold Time, H or L 5.0 4.5 4.5ns TCK to Data (Note 11)t S Setup Time, H or L

5.0 3.0 3.0ns AOE n , BOE n to TCK (Note 12)t H Hold Time, H or L

5.0 4.5 4.5ns TCK to AOE n , BOE n (Note 12)t S Setup Time, H or L

5.0 3.0 3.0ns Internal AOE, BOE, to TCK (Note 13)t H Hold Time, H or L

5.0 3.0 3.0ns TCK to Internal AOE, BOE (Note 13)t S Setup Time, H or L 5.08.08.0ns TMS to TCK t H Hold Time, H or L 5.0 2.0 2.0ns TCK to TMS t S Setup Time, H or L 5.0 4.0 4.0ns TDI to TCK t H Hold Time, H or L 5.0

4.5 4.5

TCK to TDI t W

Pulse Width TCK

5.0

H 15.015.0ns

5.0 5.0f MAX Maximum TCK 5.02525MHz Clock Frequency T PU Wait Time, Power Up 5.0100100ns to TCK

T DN

Power Down Delay

0.0100

100

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S C A N 18541T

Extended AC Electrical Characteristics

Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 15: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.Note 16: 3-STATE delays are load dominated and have been excluded from the datasheet.

Note 17: The Output Disable Time is dominated by the RC network (500?, 250 pF) on the output and has been excluded from the datasheet.

Note 18: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.The specification applies to any outputs switching HIGH-to-LOW (t OSHL ), LOW-to-HIGH (t OSLH ), or any combination switching LOW-to-HIGH and/or HIGH-to-LOW.

Capacitance

Symbol

Parameter

T A = +25°C Units

V CC = 5.0V

C L = 50 pF T A = ?40°C to +85°C 18 Outputs V CC = 5.0V ± 0.5V Switching C L = 250 pF (Note 14)

(Note 5)

Min

Typ

Max Min Max t PLH ,Propagation Delay 3.011.0 4.013.0ns t PHL Data to Output 3.011.0 4.0

15.0

t PZH ,Output Enable Time

2.511.5(Note 16)ns t PZL 2.514.0t PHZ ,Output Disable Time 2.011.5(Note 17)

ns t PLZ 2.0

11.5t OSHL Pin to Pin Skew 0.5 1.0 1.0ns (Note 18)HL Data to Output t OSLH Pin to Pin Skew 0.5 1.0

1.0

ns (Note 18)

LH Data to Output Symbol Parameter

Typ Units Conditions C IN Input Pin Capacitance 4.0pF V CC = 5.0V C OUT Output Pin Capacitance 13.0pF V CC = 5.0V C PD

Power Dissipation Capacitance

34.0

V CC = 5.0V

Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide

Package Number MS56A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1.Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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