SST29LE010-150-4C-E中文资料
Data Sheet FEATURES:
?Single Voltage Read and Write Operations – 5.0V-only for the 29EE010
– 3.0V-only for the 29LE010
– 2.7V-only for the 29VE010
?Superior Reliability
–Endurance: 100,000 Cycles (typical)
–Greater than 100 years Data Retention ?Low Power Consumption
–Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
–Standby Current: 10 μA (typical)
?Fast Page-Write Operation
–128 Bytes per Page, 1024 Pages
–Page-Write Cycle: 5 ms (typical)
–Complete Memory Rewrite: 5 sec (typical)–Effective Byte-write Cycle Time:39 μs (typical)?Fast Read Access Time
– 5.0V-only operation: 90 and 120 ns
– 3.0V-only operation: 150 and 200 ns
– 2.7V-only operation: 200 and 250 ns ?Latched Address and Data
?Automatic Write Timing
–Internal V pp Generation
?End of Write Detection
–Toggle Bit
–Data# Polling
?Hardware and Software Data Protection ?TTL I/O Compatibility
?JEDEC Standard Byte-wide EEPROM Pinouts ?Packages Available
–32-Pin TSOP (8x20 & 8x14 mm)
–32-Lead PLCC
–32 Pin Plastic DIP
PRODUCT DESCRIPTION
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS page mode EEPROMs manufactured with SST’s propri-etary, high performance CMOS SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The 29EE010/ 29LE010/29VE010 write with a single power supply. Internal Erase/Program is transparent to the user. The 29EE010/29LE010/29VE010 conform to JEDEC stan-dard pinouts for byte-wide memories.
Featuring high performance page write, the 29EE010/ 29LE010/29VE010 provide a typical byte-write time of 39 μsec. The entire memory, i.e., 128K bytes, can be written page by page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the 29EE010/29LE010/ 29VE010 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the 29EE010/ 29LE010/29VE010 are offered with a guaranteed page-write endurance of 104 or 103 cycles. Data retention is rated at greater than 100 years.
The 29EE010/29LE010/29VE010 are suited for applica-tions that require convenient and economical updating of program, configuration, or data memory. For all system applications, the 29EE010/29LE010/29VE010 signifi-cantly improve performance and reliability, while lower-ing power consumption, when compared with floppy disk or EPROM approaches. The 29EE010/29LE010/ 29VE010 improve flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the 29EE010/29LE010/29VE010 are offered in 32-pin TSOP and 32-lead PLCC packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1 and 2 for pinouts.
Device Operation
The SST page mode EEPROM offers in-circuit electrical write capability. The 29EE010/29LE010/29VE010 does not require separate erase and program operations. The internally timed write cycle executes both erase and program transparently to the user. The 29EE010/ 29LE010/29VE010 have industry standard optional Software Data Protection, which SST recommends al-ways to be enabled. The 29EE010/29LE010/29VE010 are compatible with industry standard EEPROM pinouts and functionality.
Read
The Read operations of the 29EE010/29LE010/ 29VE010 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the
chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3).
Write
The Page Write to the SST29EE010/29LE010/29VE010 should always use the JEDEC Standard Software Data Protection (SDP) 3-byte command sequence. The 29EE010/29LE010/29VE010 contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The 3-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, software data protec-tion is automatically assured. The first time the 3-byte SDP command is given, the device becomes SDP en-abled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired page write, the entire device remains protected. For additional descriptions, please see the application notes on “The Proper Use of JEDEC Standard Software Data Protection” and “Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories” in this data book.
The Write operation consists of three steps. Step 1 is the three byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the 29EE010/29LE010/29VE010. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile stor-age. During both the SDP 3-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the T BLCO timer after the rising edge of WE# or CE#, whichever occurs first. The write cycle, once initiated, will continue to completion, typically within 5 ms. See Fig-ures 4 and 5 for WE# and CE# controlled page write cycle timing diagrams and Figures 14 and 16 for flowcharts. The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection consists of a specific three byte load se-quence that allows writing to the selected page and will leave the 29EE010/29LE010/29VE010 protected at the end of the page write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the T BLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to 128 bytes of data into the page buffer of the 29EE010/ 29LE010/29VE010 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the page-write feature of 29EE010/ 29LE010/29VE010 allow the entire memory to be written in as little as 5 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FF.
See Figures 4 and 5 for the page-write cycle timing diagrams. If after the completion of the 3-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (T BLC) of 100 μs, the 29EE010/29LE010/29VE010 will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be termi-nated if no additional byte is loaded into the page buffer within 200 μs (T BLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 μs. The page to be loaded is determined by the page address of the last byte loaded. Software Chip-Erase
The 29EE010/29LE010/29VE010 provide a Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased.
The Software Chip-Erase operation is initiated by using a specific six byte-load sequence. After the load se-quence, the device enters into an internally timed cycle similar to the write cycle. During the erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 9 for timing diagram, and Figure 18 for the flowchart.
Write Operation Status Detection
The 29EE010/29LE010/29VE010 provide two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle.
The actual completion of the nonvolatile write is asyn-chronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the 29EE010/29LE010/29VE010 are in the inter-nal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the com-plement of the true data. Once the write cycle is com-pleted, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart.
Toggle Bit (DQ6)
During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s, i.e. toggling between 0 and 1. When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. The initial read of the Toggle Bit will typically be a “1”.
Data Protection
The 29EE010/29LE010/29VE010 provide both hard-ware and software features to protect nonvolatile data from inadvertent writes.Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
V CC Power Up/Down Detection: The write operation is inhibited when V CC is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the write operation. This prevents inad-vertent writes during power-up or power-down. Software Data Protection (SDP)
The 29EE010/29LE010/29VE010 provide the JEDEC approved optional software data protection scheme for all data alteration operations, i.e., Write and Chip erase. With this scheme, any write operation requires the inclu-sion of a series of three byte-load operations to precede the data loading operation. The three byte-load se-quence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. The 29EE010/29LE010/29VE010 are shipped with the soft-ware data protection disabled.
The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 4 and 5). The device will then be automatically set into the data protect mode. Any subsequent write operation will require the preceding three-byte sequence. See Table 4 for the specific soft-ware command codes and Figures 4 and 5 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 8 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 μs. SST recommends Software Data Protection always be enabled. See Figure 16 for flowcharts.
The 29EE010/29LE010/29VE010 Software Data Pro-tection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single page write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled.
Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) al-ways be enabled. The 29EE010/29LE010/29VE010should be programmed using the SDP command se-quence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing.Please refer to the following Application Notes located at the back of this databook for more information on using SDP:?Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories
?
The Proper Use of JEDEC Standard Software Data Protection
Product Identification
The product identification mode identifies the device as the 29EE010/29LE010/29VE010 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the 29EE010/29LE010/29VE010. Users may wish to use the software product identification operation to iden-tify the part (i.e. using the device code) when using
multiple manufacturers in the same socket. For details,see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. The manufacturer and device codes are the same for both operations.Product Identification Mode Exit
In order to return to the standard read mode, the Soft-ware Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset)operation, which returns the device to the read operation.The Reset operation may also be used to reset the device to the read mode after an inadvertent transient condition that apparently causes the device to behave abnormally , e.g. not read correctly. See Table 4 for software command codes, Figure 11 for timing wave-form and Figure 17 for a flowchart.
304 PGM T1.1
T ABLE 1: P RODUCT I DENTIFICATION T ABLE
Byte
Data
Manufacturer’s Code 0000 H BF H 29EE010 Device Code 0001 H 07 H 29LE010 Device Code 0001 H 08 H 29VE010 Device Code 0001 H
08 H
F IGURE 2: P IN A SSIGNMENTS FOR 32-PIN P LASTIC DIP S AND 32-LEAD PLCC S
T ABLE 2: P IN D ESCRIPTION
Symbol Pin Name Functions
A16-A7Row Address Inputs To provide memory addresses. Row addresses define a page for a
write cycle.
A6-A0Column Address Column Addresses are toggled to load page data.
Inputs
DQ7-DQ0Data Input/output To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
CE#Chip Enable To activate the device when CE# is low.
OE#Output Enable To gate the data output buffers.
WE#Write Enable To control the write operations
Vcc Power Supply To provide 5-volt supply (± 10%)for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010
Vss Ground
NC No Connection Unconnected pins.
304 PGM T2.0
T ABLE 3: O PERATION M ODES S ELECTION
Mode CE#OE#WE#DQ Address
Read V IL V IL V IH D OUT A IN
Page Write V IL V IH V IL D IN A IN
Standby V IH X X High Z X
Write Inhibit X V IL X High Z/ D OUT X
Write Inhibit X X V IH High Z/ D OUT X
Software Chip Erase V IL V IH V IL D IN A IN, See Table 4
Product Identification
Hardware Mode V IL V IL V IH Manufacturer Code (BF)A16 - A1 = V IL, A9 = V H, A0 = V IL
Device Code (see notes)A16 - A1 = V IL, A9 = V H, A0= V IH Software Mode V IL V IH V IL See Table 4
SDP Enable Mode V IL V IH V IL See Table 4
SDP Disable Mode V IL V IH V IL See Table 4
304 PGM T3.0
T ABLE 4: S OFTWARE C OMMAND C ODES
Command1st Bus2nd Bus3rd Bus4th Bus5th Bus6th Bus
Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr(1)Data Addr(1)Data Addr(1)Data Addr(1)Data Addr(1)Data Addr(1)Data Software Data5555H AAH2AAAH55H5555H A0H Addr(2)Data
Protect Enable
& Page Write
Software Data5555H AAH2AAAH55H5555H80H5555H AAH2AAAH55H5555H20H Protect Disable
Software Chip5555H AAH2AAAH55H5555H80H5555H AAH2AAAH55H5555H10H Erase
Software ID Entry5555H AAH2AAAH55H5555H90H
Software ID Exit5555H AAH2AAAH55H5555H F0H
Alternate Software5555H AAH2AAAH55H5555H80H5555H AAH2AAAH55H5555H60H ID Entry(3)
304 PGM T4.1 Notes:(1) Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”.
(2) Page Write consists of loading up to 128 bytes (A6 - A0).
(3) Alternate 6 byte software Product-ID Command Code
(4)The software chip erase function is not supported by the industrial temperature part.
Please contact SST, if you require this function for an industrial temperature part.
Notes for Software Product ID Command Code:
1. With A14 -A1 =0;SST Manufacturer Code = BFH, is read with A0 = 0,
29EE010 Device Code = 07H, is read with A0 = 1.
29LE010/29VE010 Device Code = 08H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
29EE010 O PERATING R ANGE
Range Ambient Temp V CC Commercial0°C to +70°C5V±10% Industrial-40°C to +85°C5V±10%AC C ONDITIONS OF T EST
Input Rise/Fall Time.........10 ns
Output Load.....................1 TTL Gate and C L = 100 pF See Figures 12 and 13
Absolute Maximum Stress Ratings(Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias.................................................................................................................-55°C to +125°C Storage Temperature......................................................................................................................-65°C to +150°C D. C. Voltage on Any Pin to Ground Potential.............................................................................-0.5V to V CC+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential.........................................................-1.0V to V CC+ 1.0V Voltage on A9 Pin to Ground Potential................................................................................................-0.5V to 14.0V Package Power Dissipation Capability (Ta = 25°C)...........................................................................................1.0W Through Hole Lead Soldering Temperature (10 Seconds)..............................................................................300°C Surface Mount Lead Soldering Temperature (3 Seconds)...............................................................................240°C Output Short Circuit Current(1).......................................................................................................................100 mA Note:(1) Outputs shorted for no more than one second. No more than one output shorted at a time.
29LE010 O PERATING R ANGE
Range Ambient Temp V CC
Commercial0°C to +70°C 3.0V to 3.6V
Industrial-40°C to +85°C 3.0V to 3.6V
29VE010 O PERATING R ANGE
Range Ambient Temp V CC
Commercial0°C to +70°C 2.7V to 3.6V
Industrial-40°C to +85°C 2.7V to 3.6V
T ABLE 5: 29EE010 DC O PERATING C HARACTERISTICS V CC = 5V±10%
Limits
Symbol Parameter Min Max Units Test Conditions
I CC Power Supply Current CE#=OE#=V IL,WE#=V IH , all I/Os open,
Read30mA Address input = V IL/V IH, at f=1/T RC Min.,
V CC=V CC Max
Write50mA CE#=WE#=V IL, OE#=V IH, V CC =V CC Max.
I SB1Standby V CC Current3mA CE#=OE#=WE#=V IH, V CC =V CC Max.
(TTL input)
I SB2Standby V CC Current50μA CE#=OE#=WE#=V CC -0.3V.
(CMOS input) V CC = V CC Max.
I LI Input Leakage Current1μA V IN =GND to V CC, V CC = V CC Max.
I LO Output Leakage Current10μA V OUT =GND to V CC, V CC = V CC Max.
V IL Input Low Voltage0.8V V CC = V CC Max.
V IH Input High Voltage 2.0V V CC = V CC Max.
V OL Output Low Voltage0.4V I OL = 2.1 mA, V CC = V CC Min.
V OH Output High Voltage 2.4V I OH = -400μA, V CC = V CC Min.
V H Supervoltage for A911.612.4V CE# = OE# =V IL, WE# = V IH
I H Supervoltage Current100μA CE# = OE# = V IL, WE# = V IH,
for A9 A9 = V H Max.
304 PGM T5.0
T ABLE 6: 29LE010/29VE010 DC O PERATING C HARACTERISTICS V CC = 3.0-3.6 FOR 29LE010, V CC = 2.7-3.6 FOR 29VE010
Limits
Symbol Parameter Min Max Units Test Conditions
I CC Power Supply Current CE#=OE#=V IL,WE#=V IH , all I/Os open,
Read12mA Address input = V IL/V IH, at f=1/T RC Min.,
V CC=V CC Max
Write15mA CE#=WE#=V IL, OE#=V IH, V CC =V CC Max.
I SB1Standby V CC Current1mA CE#=OE#=WE#=V IH, V CC =V CC Max.
(TTL input)
I SB2Standby V CC Current15μA CE#=OE#=WE#=V CC -0.3V.
(CMOS input)V CC = V CC Max.
I LI Input Leakage Current1μA V IN =GND to V CC, V CC = V CC Max.
I LO Output Leakage Current10μA V OUT =GND to V CC, V CC = V CC Max.
V IL Input Low Voltage0.8V V CC = V CC Max.
V IH Input High Voltage 2.0V V CC = V CC Max.
V OL Output Low Voltage0.4V I OL = 100 μA, V CC = V CC Min.
V OH Output High Voltage 2.4V I OH = -100 μA, V CC = V CC Min.
V H Supervoltage for A911.612.4V CE# = OE# =V IL, WE# = V IH
I H Supervoltage Current100μA CE# = OE# = V IL, WE# = V IH,
for A9 A9 = V H Max.
304 PGM T6.0
T ABLE 8: C APACITANCE (T a = 25 °C, f=1 MHz, other pins open)Parameter Description Test Condition Maximum
C I/O (1)I/O Pin Capacitance V I/O = 0V 12 pF C IN (1)Input Capacitance V IN = 0V
6 pF
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
304 PGM T8.0
T ABLE 9: R ELIABILITY C HARACTERISTICS Symbol Parameter Minimum Specification
Units Test Method
N END Endurance 10,000(2)
Cycles MIL-STD-883, Method 1033T DR (1)
Data Retention 100Years JEDEC Standard A103V ZAP_HBM (1)ESD Susceptibility 1000Volts JEDEC Standard A114Human Body Model V ZAP_MM (1)ESD Susceptibility 200Volts JEDEC Standard A115Machine Model I LTH (1)
Latch Up
100
mA
JEDEC Standard 78
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(2)See Ordering Information for desired type.
304 PGM T9.1
T ABLE 7: P OWER -UP T IMINGS
Symbol Parameter Maximum
Units T PU-READ (1)Power-up to Read Operation 100 μs T PU-WRITE (1)Power-up to Write Operation
5 ms
304 PGM T7.0
T ABLE 11: 29LE010 R EAD C YCLE T IMING P ARAMETERS 29LE010-150 29LE010-200
Symbol Parameter
Min Max Min Max Units
T RC Read Cycle time
150200
ns T CE Chip Enable Access Time 150200ns T AA Address Access Time
150200ns T OE Output Enable Access Time 60100
ns T CLZ (1)CE# Low to Active Output 00ns T OLZ (1)OE# Low to Active Output 00
ns T CHZ (1)CE# High to High-Z Output 30 50ns T OHZ (1)OE# High to High-Z Output
30 50
ns T OH (1)
Output Hold from Address Change
00
ns
304 PGM T11.0
T ABLE 12: 29VE010 R EAD C YCLE T IMING P ARAMETERS 29VE010-200 29VE010-250
Symbol Parameter
Min Max Min Max Units
T RC Read Cycle time
200250
ns T CE Chip Enable Access Time 200250ns T AA Address Access Time
200250ns T OE Output Enable Access Time 100120
ns T CLZ (1)CE# Low to Active Output 00ns T OLZ (1)OE# Low to Active Output 00
ns T CHZ (1)CE# High to High-Z Output 50 50ns T OHZ (1)OE# High to High-Z Output
50 50
ns T OH (1)
Output Hold from Address Change
00
ns
304 PGM T12.0
AC CHARACTERISTICS
T ABLE 10: 29EE010 R EAD C YCLE T IMING P ARAMETERS
29EE010-90 29EE010-120
Symbol Parameter Min Max
Min Max
Units T RC Read Cycle time
90
120
ns T CE Chip Enable Access Time 90120ns T AA Address Access Time 90120ns T OE Output Enable Access Time 40
50ns T CLZ (1)CE# Low to Active Output 00ns T OLZ (1)OE# Low to Active Output 0
ns T CHZ (1)CE# High to High-Z Output 30 30ns T OHZ (1)OE# High to High-Z Output 30
30
ns T OH (1)
Output Hold from Address 00
ns
Change
304 PGM T10.1
T ABLE 13: P AGE-W RITE C YCLE T IMING P ARAMETERS
29EE010 29LE/VE010
Symbol Parameter Min Max Min Max Units
T WC Write Cycle (erase and program)1010ms
T AS Address Setup Time00ns
T AH Address Hold Time5070ns
T CS WE# and CE# Setup Time00ns
T CH WE# and CE# Hold Time00ns
T OES OE# High Setup Time00ns
T OEH OE# High Hold Time00ns
T CP CE# Pulse Width70120ns
T WP WE# Pulse Width70120ns
T DS Data Setup Time3550ns
T DH Data Hold Time00ns
T BLC(1)Byte Load Cycle Time0.051000.05100μs
T BLCO(1)Byte Load Cycle Time200200μs
T IDA Software ID Access and Exit Time1010μs
T SCE Software Chip Erase2020ms
304 PGM T13.1 Note:(1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
F IGURE 3: R EAD C YCLE T IMIN
G D IAGRAM
F IGURE 4: WE# C ONTROLLED P AGE W RITE C YCLE T IMIN
G D IAGRAM 304 AC F03.0
304 AC F04.0
F IGURE 5: CE# C ONTROLLED P AGE W RITE C YCLE T IMIN
G D IAGRAM F IGURE 6: D ATA# P OLLING T IMING D IAGRAM 304 AC F05.0
304 AC F06.0
304 AC F07.0
304 AC F08.0
F IGURE 7: T OGGLE B IT T IMIN
G D IAGRAM
F IGURE 8: S OFTWARE D ATA P ROTECT D ISABLE T IMIN
G D
IAGRAM
304 AC F09.0
F IGURE 9: S OFTWARE C HIP E RASE T IMIN
G D IAGRAM
F IGURE 10: S OFTWARE ID E NTRY AND R
EAD
304 AC F10.0
= 08 for 29LE010/29VE010
F IGURE 11: S OFTWARE ID E XIT AND R ESET
304 AC F11.0
F IGURE 12: AC I NPUT /O UTPUT R EFERENCE W AVEFORMS
304 MSW F12.0
F IGURE 13: T EST L OAD E XAMPLE
AC test inputs are driven at V OH (2.4 V TTL ) for a logic “1” and V OL (0.4 V TTL ) for a logic “0”. Measurement reference points for inputs and outputs are V IH (2.0 V TTL ) and V IL (0.8 V TTL ). Inputs rise and fall times (10% ? 90%) are <10ns.
REFERENCE POINTS
2.0
0.8
2.0
0.8
OUTPUT
INPUT
2.4
0.4
F IGURE 14: W RITE A LGORITHM
F IGURE 15: W AIT O PTIONS
F IGURE 16: S OFTWARE D ATA P ROTECTION F LOWCHARTS