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CD4069UBCMX_NL中文资料

CD4069UBCMX_NL中文资料
CD4069UBCMX_NL中文资料

? 2002 Fairchild Semiconductor Corporation DS005975

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October 1987Revised April 2002

CD4069UBC Inverter Circuits

CD4069UBC Inverter Circuits

General Description

The CD4069UB consists of six inverter circuits and is man-ufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power consump-tion, high noise immunity, and symmetric controlled rise and fall times.

This device is intended for all general purpose inverter applications where the special characteristics of the MM74C901, MM74C907, and CD4049A Hex Inverter/Buff-ers are not required. In those applications requiring larger noise immunity the MM74C14 or MM74C914 Hex Schmitt Trigger is suggested.

All inputs are protected from damage due to static dis-charge by diode clamps to V DD and V SS .Features

s Wide supply voltage range: 3.0V to 15V s High noise immunity:0.45 V DD typ.s Low power TTL compatibility:Fan out of 2 driving 74L

or 1 driving 74LS s Equivalent to MM74C04

Ordering Code:

Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.

Connection Diagram Schematic Diagram

Order Number Package Number

Package Description

CD4069UBCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4069UBCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4069UBCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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C D 4069U B C

Absolute Maximum Ratings (Note 1)

(Note 2)

Recommended Operating Conditions (Note 2)

Note 1: “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recom-mended Operating Conditions ” and Electrical Characteristics table provide conditions for actual device operation.Note 2: V SS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

Note 3: V SS = 0V unless otherwise specified.Note 4: I OH and I OL are tested one output at a time.

DC Supply Voltage (V DD )?0.5V to +18 V DC

Input Voltage (V IN )

?0.5V to V DD +0.5 V DC

Storage Temperature Range (T S )?65°C to +150°C

Power Dissipation (P D )Dual-In-Line 700 mW Small Outline 500 mW

Lead Temperature (T L )(Soldering, 10 seconds)

260°C DC Supply Voltage (V DD )3V to 15V DC Input Voltage (V IN )

0V to

V DD V DC

Operating Temperature Range (T A )

?55°C to +125°C

Symbol Parameter

Conditions

?55°C +25°C +125°C Units

Min

Max Min

Typ

Max Min

Max I DD

Quiescent Device Current

V DD = 5V,0.250.257.5μA

V IN = V DD or V SS V DD = 10V,0.50.515V IN = V DD or V SS V DD = 15V, 1.0

1.0

30

V IN = V DD or V SS

V OL

LOW Level Output Voltage

|I O | < 1 μA V DD = 5V 0.0500.050.05V

V DD = 10V 0.0500.050.05V DD = 15V

0.05

00.05

0.05

V OH

HIGH Level Output Voltage

|I O | < 1 μA V DD = 5V 4.95 4.955 4.95V

V DD = 10V 9.959.95109.95V DD = 15V

14.95

14.95

15

14.95

V IL

LOW Level Input Voltage

|I O | < 1 μA

V DD = 5V, V O = 4.5V 1.0 1.0

1.0

V

V DD = 10V, V O = 9V 2.0 2.0 2.0V DD = 15V, V O = 13.5V

3.0

3.0

3.0

V IH

HIGH Level Input Voltage

|I O | < 1 μA

V DD = 5V, V O = 0.5V 4.0 4.0 4.0V

V DD = 10V, V O = 1V 8.08.08.0V DD = 15V, V O = 1.5V

12.012.012.0

I OL

LOW Level Output Current V DD = 5V, V O = 0.4V 0.640.510.880.36mA

(Note 4)

V DD = 10V, V O = 0.5V 1.6 1.3 2.250.9V DD = 15V, V O = 1.5V 4.2 3.48.8 2.4I OH

HIGH Level Output Current V DD = 5V, V O = 4.6V ?0.64?0.51?0.88?0.36mA

(Note 4)

V DD = 10V, V O = 9.5V ?1.6?1.3?2.25?0.9V DD = 15V, V O = 13.5V ?4.2

?3.4?8.8?2.4

I IN

Input Current

V DD = 15V, V IN = 0V ?0.1?10?5?0.1?1.0μA

V DD = 15V, V IN = 15V

0.1

10?5

0.1

1.0

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CD4069UBC

AC Electrical Characteristics (Note 5)

T A = 25°C, C L = 50 pF, R L = 200 k ?, t r and t f ≤ 20 ns, unless otherwise specified Note 5: AC Parameters are guaranteed by DC correlated testing.

Note 6: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note —AN-90.

AC Test Circuits and Switching Time Waveforms

Symbol Parameter

Conditions

Min

Typ Max Units

t PHL or t PLH

Propagation Delay Time from V DD = 5V 5090ns Input to Output

V DD = 10V 3060V DD = 15V 2550t THL or t TLH

Transition Time

V DD = 5V 80150ns V DD = 10V 50100V DD = 15V

4080C IN Average Input Capacitance Any Gate 615

pF C PD

Power Dissipation Capacitance

Any Gate (Note 6)

12

pF

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C D 4069U B C

Typical Performance Characteristics

Gate Transfer Characteristics

Power Dissipation vs. Frequency

Propagation Delay vs. Ambient Temperature

Propagation Delay vs. Ambient Temperature

Propagation Delay Time vs. Load Capacitance

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Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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C D 4069U B C

Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

CD4069UBC Inverter Circuits

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1.Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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