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MAX1271BCNG+中文资料

General Description

The MAX1270/MAX1271 are multirange, 12-bit data-acquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that can span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: ±10V, ±5V, 0 to +10V, 0 to +5V for the MAX1270; ±V REF , ±V REF /2, 0 to V REF , 0 to V REF /2 for the MAX1271. This range switch-ing increases the effective dynamic range to 14 bits and provides the flexibility to interface 4–20mA, ±12V, and ±15V powered sensors directly to a single +5V system.In addition, these converters are fault protected to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other fea-tures include a 5MHz bandwidth track/hold, software-selectable internal/external clock, 110ksps throughput rate, and internal 4.096V or external reference operation.The MAX1270/MAX1271 serial interface directly connects to SPI?/QSPI? and MICROWIRE? devices without external logic.

A hardware shutdown input (SHDN ) and two software-programmable power-down modes, standby (STBYPD)or full power-down (FULLPD), are provided for low-cur-rent shutdown between conversions. In standby mode,the reference buffer remains active, eliminating startup delays.

The MAX1270/MAX1271 are available in 24-pin narrow PDIP or space-saving 28-pin SSOP packages.

Applications

Features

?12-Bit Resolution, 0.5 LSB Linearity ?+5V Single-Supply Operation

?SPI/QSPI and MICROWIRE-Compatible 3-Wire Interface ?Four Software-Selectable Input Ranges

MAX1270: 0 to +10V, 0 to +5V, ±10V, ±5V MAX1271: 0 to V REF , 0 to V REF /2, ±V REF ,±V REF /2?Eight Analog Input Channels ?110ksps Sampling Rate

?±16.5V Overvoltage-Tolerant Input Multiplexer ?Internal 4.096V or External Reference ?Two Power-Down Modes ?Internal or External Clock

?24-Pin Narrow PDIP or 28-Pin SSOP Packages

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

________________________________________________________________Maxim Integrated Products 1

Typical Operating Circuit

Ordering Information

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.wendangku.net/doc/e89906163.html,.

Pin Configurations appear at end of data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Ordering Information continued at end of data sheet.

Industrial Control Systems Data-Acquisition Systems Battery-Powered Instruments

Automatic Testing Robotics Medical Instruments

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V DD = +5.0V ±5%; unipolar/bipolar range; external reference mode, V REF = +4.096V; 4.7μF at REF; external clock; f CLK = 2.0MHz, 50% duty cycle (MAX127_B); f = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, T = T to T , unless Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V DD to AGND............................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0–CH7 to AGND ......................................................... ±16.5V REF, REFADJ to AGND ..............................-0.3V to (V DD + 0.3V)SSTRB, DOUT to DGND.............................-0.3V to (V DD + 0.3V)SHDN , CS , DIN, SCLK to DGND..............................-0.3V to +6V Max Current into Any Pin ....................................................50mA Continuous Power Dissipation (T A = +70°C)

24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..1067mW 28-Pin SSOP (derate 9.52mW/°C above +70°C)..........762mW

Operating Temperature Ranges

MAX127_C_ _......................................................0°C to +70°C MAX127_E_ _......................................................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°C

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________3

ELECTRICAL CHARACTERISTICS (continued)

(V DD = +5.0V ±5%; unipolar/bipolar range; external reference mode, V REF = +4.096V; 4.7μF at REF; external clock; f CLK = 2.0MHz, 50% duty cycle (MAX127_B); f CLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, T A = T MIN to T MAX , unless otherwise noted. Typical values are T A = +25°C.)

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 4_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________5

ELECTRICAL CHARACTERISTICS (continued)

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 6_______________________________________________________________________________________

Note 2:External reference: V REF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.

Note 3:Ground “on” channel; sine wave applied to all “off” channels. V IN = ±5V (MAX1270), V IN = ±4V (MAX1271).Note 4:Guaranteed by design, not production tested.

Note 5:Use static external loads during conversion for specified accuracy.Note 6:Tested using internal reference.

Note 7:PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.

Note 8:Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).Note 9:Not production tested. Provided for design guidance only.

TIMING CHARACTERISTICS

(V DD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V REF = +4.096V; 4.7μF at REF; external clock; f CLK =2.0MHz (MAX127_B); f CLK = 1.8MHz (MAX127_A); T A = T MIN to T MAX , unless otherwise noted. Typical values are T A = +25°C.)(Figures 2, 5, 7, 10)

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________Typical Operating Characteristics

(Typical Operating Circuit, V DD = +5V; external reference mode, V REF = +4.096V; 4.7μF at REF; external clock, f CLK = 2MHz;110ksps; T A = +25°C, unless otherwise noted.)

01638819245732764095M A X 1270/1 t o DIGITAL CODE 020k 10k 30k 40k 50k

M A X 1270/1 t o c 09

FREQUENCY (Hz)

f IN = 10kHz

f SAMPLE = 110ksps

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs

Pin Description

0123456780.1

100

1000

AVERAGE SUPPLY CURRENT vs.CONVERSION RATE (USING STANDBY)

CONVERSION RATE (ksps)

A V E R A G E S U P P L Y C U R R E N T (m A )

012345678

0.1

100

1000

AVERAGE SUPPLY CURRENT vs.CONVERSION RATE (USING FULLPD)

CONVERSION RATE (ksps)

A V E R A G E S U P P L Y C U R R E N T (m A )

Typical Operating Characteristics (continued)

(Typical Operating Circuit, V DD = +5V; external reference mode, V REF = +4.096V; 4.7μF at REF; external clock, f CLK = 2MHz;110ksps; T A = +25°C, unless otherwise noted.)

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

_______________________________________________________________________________________

Detailed Description

Converter Operation

The MAX1270/MAX1271 multirange, fault-tolerant ADCs use successive approximation and internal track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. Figure 3 shows the block diagram of the MAX1270/MAX1271.

Analog-Input Track/Hold

The T/H enters tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word,and enters hold/conversion mode when the timed acquisition interval (six clock cycles, 3μs minimum)ends. In internal clock mode, the acquisition is timed by two external clock cycles and four internal clock cycles.

When operating in bipolar (MAX1270 and MAX1271) or unipolar mode (MAX1270) the signal applied at the input channel is rescaled through the resistor-divider network formed by R1, R2, and R3 (Figure 4); a low impedance (<4?) input source is recommended to minimize gain error. When the MAX1271 is configured for unipolar mode, the channel input resistance (R IN )becomes a fixed 5.12k ?(typ). Source impedances below 15k ?(0 to V REF ) and 5k ?(0 to V REF /2) do not significantly affect the AC performance of the ADC. The acquisition time (t ACQ ) is a function of the source output resistance, the channel input resistance, and the T/H capacitance. Higher source impedances can be used if an input capacitor is connected between the analog inputs and AGND. Note that the input capacitor forms an RC filter with the input source impedance, lim-iting the ADC’s signal bandwidth.

Figure 1. Reference-Adjust Circuit Figure 3. Block Diagram

Figure 2. Output Load Circuit for Timing Characteristics

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 10

______________________________________________________________________________________

Input Bandwidth

The ADC’s input small-signal bandwidth depends on the selected input range and varies from 1.5MHz to 5MHz (see Electrical Characteristics ). The MAX1270B/MAX1271B maximum sampling rate is 110ksps (100ksps for the MAX1270A/MAX1271A). By using undersampling techniques, it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate.

To avoid high-frequency signals being aliased into the frequency band of interest, anti-aliasing filtering is rec-ommended.

Input Range and Protection

The MAX1270/MAX1271 have software-selectable input ranges. Each analog input channel can be indepen-dently programmed to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table 1). The MAX1270 has selectable input ranges extending to ±10V (±V REF x 2.441), while the MAX1271has selectable input ranges extending to ±V REF . Figure 4 shows the equivalent input circuit.

A resistor network on each analog input provides ±16.5V fault protection for all channels. Whether or not the channel is on, this circuit limits the current going into or out of the pin to less than 2mA. This provides an added layer of protection when momentary overvolt-ages occur at the selected input channel, when a neg-ative signal is applied to the input, and when the device is configured for unipolar mode. The overvoltage pro-tection is active even if the device is in power-down mode or if V DD = 0.

Digital Interface

The MAX1270/MAX1271 feature a serial interface that is fully compatible with SPI/QSPI and MICROWIRE devices.For SPI/QSPI, set CPOL = 0, CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows detailed serial-interface timing information. See Table 1 for details on programming the input control byte.

Figure 5. Detailed Serial-Interface Timing

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________11

Table 1. Control-Byte Format

Table 2. Channel Selection

Table 4. Power-Down and Clock Selection

Table 3. Range and Polarity Selection for MAX1270/MAX1271

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 12

______________________________________________________________________________________

Input Data Format

Input data (control byte) is clocked in at DIN at the ris-ing edge of SCLK. CS enables communication with the MAX1270/MAX1271. After CS falls, the first arriving logic 1 bit represents the start bit (MSB) of the input control byte. The start bit is defined as:

The first high bit clocked into DIN with CS low anytime the converter is idle; e.g., after V DD is applied.

The first high bit clocked into DIN after bit 6 (D6) of a conversion in progress is clocked onto DOUT.

Output Data Format

Output data is clocked out on the falling edge of SCLK at DOUT, MSB first (D11). In unipolar mode, the output is straight binary. For bipolar mode, the output is two’s complement binary. For output binary codes, refer to the Transfer Function section.

How to Start a Conversion

The MAX1270/MAX1271 use either an external serial clock or the internal clock to complete an acquisition and perform a conversion. In both clock modes, the external clock shifts data in and out. See Table 4 for details on programming clock modes.

The falling edge of CS does not start a conversion on the MAX1270/MAX1271; a control byte is required for each conversion. Acquisition starts after the sixth bit is programmed in the input control byte. Conversion starts when the acquisition time, six clock cycles,expires.

Keep CS low during successive conversions. If a start-bit is received after CS transitions from high to low, but before the output bit 6 (D6) becomes available, the cur-rent conversion will terminate and a new conversion will begin.

External Clock Mode (PD1 = 0, PD0 = 1)

In external clock mode, the clock shifts data in and out of the MAX1270/MAX1271 and controls the acquisition and conversion timings. When acquisition is done,SSTRB pulses high for one clock cycle and conversion begins. Successive-approximation bit decisions appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). Additional SCLK falling edges will result in zeros appearing at DOUT. Figure 7 shows the SSTRB timing in external clock mode.

SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge,SSTRB and DOUT will output a logic low.

The conversion must be completed in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the clock period exceeds 10μs, or if serial-clock inter-ruptions could cause the conversion interval to exceed 120μs. The fastest the MAX1270/MAX1271 can run is 18 clocks per conversion in external clock mode, and with a clock rate of 2MHz, the maximum sampling rate is 111 ksps (Figure 8). In order to achieve maximum throughput, keep CS low, use external clock mode with a continuous SCLK, and start the following control byte after bit 6 (D6) of the conversion in progress is clocked onto DOUT.

If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 18 zeros.

Figure 6. External Clock Mode—25 Clocks/Conversion Timing

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________

Internal Clock Mode (PD1 = 0, PD0 = 0)

In internal clock mode, the MAX1270/MAX1271 gener-ate their conversion clock internally. This frees the microprocessor from the burden of running the acquisi-tion and the SAR conversion clock, and allows the con-version results to be read back at the processor’s convenience, at any clock rate from 0 to typically 10MHz.

SSTRB goes low after the falling edge of the last bit (PD0) of the control byte has been shifted in, and returns high when the conversion is complete.Acquisition is completed and conversion begins on the falling edge of the 4th internal clock pulse after the con-trol byte; conversion ends on the falling edge of the 16th internal clock pulse (12 internal clock cycle pulses are used for conversion). SSTRB will remain low for a maximum of 15μs, during which time SCLK should remain low for best noise performance. An internal reg-ister stores data while the conversion is in progress.The MSB of the result byte (D11) is present at DOUT starting at the falling edge of the last internal clock of conversion. Successive falling edges of SCLK will shift the remaining data out of this register (Figure 9).Additional SCLK edges will result in zeros on DOUT.When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high.Pulling CS high prevents data from being clocked in and tri-states DOUT, but does not adversely affect a

Figure 7. External Clock Mode—SSTRB Detailed Timing

Figure 8. External Clock Mode—18 Clocks/Conversion Timing

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 14______________________________________________________________________________________

conversion in progress. Figure 10 shows the SSTRB timing in internal clock mode.

Internal clock mode conversions can be completed with 13 external clocks per conversion but require a waiting period of 15μs for the conversion to be com-pleted (Figure 11).

Most microcontrollers require that conversions occur in multiples of 8 SCLK clock cycles. Sixteen clock cycles per conversion (as shown in Figure 12) is typically the most convenient way for a microcontroller to drive the MAX1270/MAX1271.

Applications Information

Power-On Reset

The MAX1270/MAX1271 power up in normal operation (all internal circuitry active) and internal clock mode,waiting for a start bit. The contents of the output data register are cleared at power-up.

Internal or External Reference

The MAX1270/MAX1271 operate with either an internal or external reference. An external reference is connect-ed to either REF or REFADJ (Figure 13). The REFADJ internal buffer gain is trimmed to 1.638V to provide 4.096V at REF from a 2.5V reference.

Figure 9. Internal Clock Mode—20 SCLK/Conversion Timing

Figure 10. Internal Clock Mode—SSTRB Detailed Timing

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________15

Internal Reference

The internally trimmed 2.50V reference is amplified through the REFADJ buffer to provide 4.096V at REF.Bypass REF with a 4.7μF capacitor to AGND and REFADJ with a 0.01μF capacitor to AGND (Figure 13a).The internal reference voltage is adjustable to ±1.5%(±65 LSBs) with the reference-adjust circuit of Figure 1.External Reference

To use the REF input directly, disable the internal buffer by tying REFADJ to V DD (Figure 13b). Using the REFADJ input eliminates the need to buffer the refer-ence externally. When a reference is applied at REFADJ, bypass REFADJ with a 0.01μF capacitor to AGND. Note that when an external reference is applied at REFADJ, the voltage at REF is given by:

V REF = 1.6384 x V REFADJ (2.4 < V REF < 4.18) (Figure 13c). At REF and REFADJ, the input impedance is a minimum of 10k ?for DC currents. During conver-sions, an external reference at REF must be able to deliv-er 400μA DC load currents and must have an output impedance of 10?or less. If the reference has higher output impedance or is noisy, bypass REF with a 4.7μF capacitor to AGND as close to the chip as possible.

With an external reference voltage of less than 4.096V at REF or less than 2.5V at REFADJ, the increase in the ratio of RMS noise to the LSB value (full-scale / 4096)results in performance degradation (loss of effective bits).

Figure 11. Internal Clock Mode—13 Clocks/Conversion Timing

Figure 12. Internal Clock Mode—16 Clocks/Conversion Timing

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 16

______________________________________________________________________________________

Power-Down Mode

To save power, configure the converter into low-current shutdown mode between conversions. Two program-mable power-down modes are available in addition to a hardware shutdown. Select STBYPD or FULLPD by pro-gramming PD0 and PD1 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. For example, if the control byte contains PD1 = 0, then the chip remains powered up. If PD1 = 1, then the chip powers down at the end of conversion. In all power-down modes, the interface remains active and conver-sion results can be read. Input overvoltage protection is active in all power-down modes.

The first logical 1 on DIN after CS falls is interpreted as a start condition, and powers up the MAX1270/MAX1271 from a software selected STBYPD or FULLPD condition.

For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted.

Choosing Power-Down Modes

The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7μF capacitor at REF. This is a DC state that does not degrade after power-down of any duration.

In FULLPD mode, only the bandgap reference is active.Connect a 33μF capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for ref-erence recovery prior to conversion. This allows con-version to begin immediately after power-up. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50μs for settling time.Auto-Shutdown

Selecting STBYPD on every conversion automatically shuts down the MAX1270/MAX1271 after each conversion without requiring any start-up time on the next conversion.

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________17

Transfer Function

Output data coding for the MAX1270/MAX1271 is bina-ry in unipolar mode with 1 LSB = (FS / 4096) and two’s

complement binary in bipolar mode with 1 LSB = [(2 x | FS | ) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 14a and 14b show the input/output (I/O) transfer functions for unipo-lar and bipolar operations, respectively. For full-scale values, refer to Table 3.

Layout, Grounding, and Bypassing

Careful PC board layout is essential for best system performance. Use a ground plane for best perfor-mance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Connect analog grounds and DGND in a star configuration to AGND.For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass V DD with 0.1μF and 4.7μF capacitors to AGND to minimize highand low-frequency fluctuations. If the supply is excessively noisy, connect a 5?resistor between the supply and V DD , as shown in Figure 15.

Figure 15. Power-Supply Grounding Connections

Figure 14a. Unipolar Transfer Function Figure 14b. Bipolar Transfer Function

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs 18______________________________________________________________________________________

Ordering Information (continued)

Pin Configurations

Chip Information

TRANSISTOR COUNT: 4219

SUBSTRATE CONNECTED TO AGND

MAX1270/MAX1271

Multirange, +5V , 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________________________________

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to https://www.wendangku.net/doc/e89906163.html,/packages .)

P D I P N .E P

M A X 1270/M A X 1271

Multirange, +5V , 8-Channel,Serial 12-Bit ADCs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600?2004 Maxim Integrated Products

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to https://www.wendangku.net/doc/e89906163.html,/packages .)

S S O P .E P S