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CD54HC367F3A中文资料

Data sheet acquired from Harris Semiconductor

SCHS181D

Features

?Buffered Inputs

?High Current Bus Driver Outputs

?Two Independent Three-State Enable Controls ?Typical Propagation Delay t PLH ,t PHL =8ns at V CC =5V ,C L = 15pF, T A = 25o C

?Fanout (Over Temperature Range)

-Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads -Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads ?Wide Operating Temperature Range . . .-55o C to 125o C ?Balanced Propagation Delay and Transition Times ?Signi?cant Power Reduction Compared to LSTTL Logic ICs ?HC Types

-2V to 6V Operation

-High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V ?HCT Types

- 4.5V to 5.5V Operation

-Direct LSTTL Input Logic Compatibility,V IL = 0.8V (Max), V IH = 2V (Min)

-CMOS Input Compatibility, I l ≤1μA at V OL , V OH

Description

The ’HC367,’HCT367,’HC368,and CD74HCT368silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers.They have high drive cur-rent outputs which enable high speed operation even when driving large bus capacitances.These circuits possess the low power dissipation of CMOS circuitry ,yet have speeds compara-ble to low power Schottky TTL circuits.Both circuits are capable of driving up to 15 low power Schottky inputs.

The ’HC367and ’HCT367are non-inverting buffers,whereas the ’HC368and CD74HCT368are inverting buffers.These devices have two output enables,one enable (OE1)controls 4gates and the other (OE2) controls the remaining 2 gates.The ’HCT367and CD74HCT368logic families are speed,func-tion and pin compatible with the standard LS logic family .

Ordering Information

PART NUMBER TEMP . RANGE

(o C)PACKAGE CD54HC367F3A -55 to 12516 Ld CERDIP CD54HC368F3A -55 to 12516 Ld CERDIP CD54HCT367F3A -55 to 12516 Ld CERDIP CD74HC367E -55 to 12516 Ld PDIP CD74HC367M -55 to 12516 Ld SOIC CD74HC367MT -55 to 12516 Ld SOIC CD74HC367M96-55 to 12516 Ld SOIC CD74HC368E -55 to 12516 Ld PDIP CD74HC368M -55 to 12516 Ld SOIC CD74HC368MT -55 to 12516 Ld SOIC CD74HC368M96-55 to 12516 Ld SOIC CD74HCT367E -55 to 12516 Ld PDIP CD74HCT367M -55 to 12516 Ld SOIC CD74HCT367MT -55 to 12516 Ld SOIC CD74HCT367M96-55 to 12516 Ld SOIC CD74HCT368E -55 to 12516 Ld PDIP CD74HCT368M -55 to 12516 Ld SOIC CD74HCT368MT -55 to 12516 Ld SOIC CD74HCT368M96

-55 to 125

16 Ld SOIC

NOTE:When ordering,use the entire part number.The suf?x 96denotes tape and reel.The suf?x T denotes a small-quantity reel of 250.

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.CD54/74HC367, CD54/74HCT367,

CD54/74HC368, CD74HCT368

High-Speed CMOS Logic Hex Buffer/Line Driver,

Three-State Non-Inverting and Inverting

[ /Title (CD74HC367,

CD74HCT367,CD74HC368,

CD74HCT368)/Sub-ject (High Speed

Functional Diagrams

TRUTH TABLE

Pinouts

CD54HC367, CD54HCT367

(CERDIP)

CD74HC367, CD74HCT367

(PDIP , SOIC)TOP VIEW

CD54HC368(CERDIP)

CD74HC368, CD74HCT368

(PDIP , SOIC)TOP VIEW

14151691312111012345768

OE11A 1Y 2A 2Y 3A GND 3Y V CC 6A 6Y 5A 5Y 4A 4Y

OE214151691312111012345768

OE11A 1Y 2A 2Y 3A GND 3Y V CC 6A 6Y 5A 5Y 4A 4Y

OE2HC367, HCT367

HC368, CD74HCT368

INPUTS OUTPUTS

(Y)

OE A HC/HCT367

HC/HCT368

L L L H L H H L H

(Z)

H = High Voltage Level L = Low Voltage Level X = Don’t Care

Z = High Impedance (OFF) State

15169

121110

4576

OE11A 1Y

2A 2Y 3A GND

3Y V CC 6A

5A 5Y 4A

OE214

15169

121110

4576

OE11A 1Y

2A 2Y 3A

GND

3Y V CC 6A

5A 5Y 4A

OE2

Logic Diagram

NOTE:

1.Inverter not included in HC/HCT367

FIGURE 1.LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF

THOSE SHOWN, i.e., 1Y, 2Y, ETC.)

3Y 7104A 4Y 9125A 5Y 11146A

13OE1

115OE2

ONE OF SIX IDENTICAL CIRCUITS

V CC

31Y

GND 8

(NOTE 1)

21A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, V CC. . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7V DC Input Diode Current, I IK

For V I < -0.5V or V I > V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, I OK

For V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, I O

For -0.5V < V O < V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC V CC or Ground Current, I CC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions

Temperature Range, T A . . . . . . . . . . . . . . . . . . . . . .-55o C to 125o C Supply Voltage Range, V CC

HC T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, V I, V O . . . . . . . . . . . . . . . . .0V to V CC Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400ns (Max)Thermal Resistance (T ypical, Note 2)θJA (o C/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .73 Maximum Junction T emperature. . . . . . . . . . . . . . . . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . .-65o C to 150o C Maximum Lead T emperature (Soldering 10s). . . . . . . . . . . . .300o C (SOIC - Lead Tips Only)

CAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied.

NOTE:

2.The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speci?cations

PARAMETER SYMBOL

TEST

CONDITIONS

V CC (V)

25o C-40o C TO 85o C-55o C TO 125o C

UNITS V I(V)I O(mA)MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input Voltage V IH--2 1.5-- 1.5- 1.5-V

4.5 3.15-- 3.15 - 3.15-V

6 4.2-- 4.2- 4.2-V

Low Level Input Voltage V IL--2--0.5-0.5-0.5V

4.5-- 1.35- 1.35- 1.35V

6-- 1.8- 1.8- 1.8V

High Level Output Voltage

CMOS Loads V OH V IH or

V IL

-0.022 1.9-- 1.9- 1.9-V

-0.02 4.5 4.4-- 4.4 - 4.4-V

-0.026 5.9-- 5.9- 5.9-V

High Level Output Voltage

TTL Loads

-6 4.5 3.98-- 3.84- 3.7-V -7.86 5.48-- 5.34- 5.2-V

Low Level Output Voltage

CMOS Loads V OL V IH or

V IL

0.022--0.1-0.1-0.1V

0.02 4.5--0.1-0.1-0.1V

0.026--0.1-0.1-0.1V

Low Level Output Voltage

TTL Loads

6 4.5--0.26-0.33-0.4V

7.86--0.26-0.33-0.4V

Input Leakage Current I I V CC or

GND

-6--±0.1-±1-±1μA

Quiescent Device Current I CC V CC or

GND

06--8-80-160μA

Three-State Leakage Current I OZ V IL or

V IH

V O =

V CC or

GND

6--±0.5-±5.0-±10μA

HCT TYPES High Level Input Voltage V IH -- 4.5 to 5.52--2-2-V Low Level Input Voltage

V IL -- 4.5 to 5.5--0.8-0.8-0.8V High Level Output Voltage

CMOS Loads V OH

V IH or V IL

-0.02

4.5

4.4

-- 4.4

- 4.4

-V

High Level Output Voltage TTL Loads -4 4.5 3.98-- 3.84- 3.7-V

Low Level Output Voltage

CMOS Loads V OL

V IH or V IL

0.02 4.5--0.1-0.1-0.1V

Low Level Output Voltage TTL Loads 4 4.5--0.26-0.33-0.4V

Input Leakage Current

I I V CC to GND 0 5.5--±0.1-±1-±1μA Quiescent Device Current

I CC V CC or GND 0 5.5--8-80-160μA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ?I CC (Note 3)V CC -2.1-

4.5 to

5.5-

100

360

450

490

μA

Three-State Leakage Current I OZ

V IL or V IH

V O =V CC or GND

5.5

--±0.5-±5.0-±10μA

NOTE:

3.For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA.

DC Electrical Speci?cations

(Continued)PARAMETER SYMBOL

TEST CONDITIONS

V CC (V)

25o C -40o C TO 85o C -55o C TO 125o C UNITS

V I (V)

I O (mA)MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT UNIT LOADS

OE10.6All Others

0.55

NOTE:Unit Load is ?I CC limit speci?ed in DC Electrical Speci?cations table, e.g., 360μA max at 25o C.

Switching Speci?cations

Input t r , t f = 6ns

PARAMETER

SYMBOL TEST CONDITIONS V CC (V)

25o C

-40o C TO 85o C

-55o C TO 125o C UNITS TYP MAX MAX MAX HC TYPES Propagation Delay,Data to Outputs HC/HCT367

t PLH , t PHL

C L = 50pF

2-105130160ns 4.5-212632ns 6

-182427ns C L = 15pF

---ns

Propagation Delay,Data to Outputs HC/HCT368

t PLH , t PHL

C L = 50pF

2-105130160ns 4.5-212632ns 6

-182427ns C L = 15pF

59---ns Propagation Delay,

Output Enable and Disable to Outputs

t PLH , t PHL

C L = 50pF

2-150190225ns 4.5-303845ns 6

-263338ns C L = 15pF

512---ns Output Transition Time

t TLH , t THL

C L = 50pF

2-607590ns 4.5-121518ns 6

-101315ns Input Capacitance C I ---101010pF Three-State Output Capacitance C O ---202020pF Power Dissipation Capacitance (Notes 4, 5)C PD

-5

---pF

HCT TYPES Propagation Delay,Data to Outputs HC/HCT367t PLH , t PHL

C L = 50pF 4.5-253138ns C L = 15pF

59---ns Propagation Delay,Data to Outputs HC/HCT368

t PLH , t PHL

C L = 50pF 4.5-303845ns C L = 15pF

511---ns Propagation Delay,

Output Enable and Disable to Outputs

t PLH , t PHL

C L = 50pF 4.5-354453ns C L = 15pF

514---ns Output Transition Time t TLH , t THL

C L = 50pF

4.5-121518ns Input Capacitance C IN ---101010pF Three-State Capacitance C O ---202020pF Power Dissipation Capacitance (Notes 4, 5)C PD

-5

---pF

NOTES:

4.C PD is used to determine the dynamic power consumption, per buffer.

5.P D = V CC 2f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, V CC = Supply Voltage.

Switching Speci?cations

Input t r , t f = 6ns (Continued)

PARAMETER

SYMBOL TEST CONDITIONS V CC (V)

25o C

-40o C TO 85o C

-55o C TO 125o C UNITS TYP MAX MAX MAX

Test Circuits and Waveforms

FIGURE 2.HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3.HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 4.HC THREE-STATE PROPAGATION DELAY

WAVEFORM FIGURE 5.HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE:Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left.The test circuit is Output R L =1k ?to V CC , C L = 50pF .

FIGURE 6.HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

t PHL

t PLH

t THL

t TLH 90%50%10%

50%10%

INVERTING OUTPUT

INPUT

GND

V CC

t r = 6ns

t f = 6ns

90%t PHL

t PLH

t THL

t TLH 2.7V 1.3V 0.3V

1.3V 10%INVERTING OUTPUT

INPUT

GND

t r = 6ns

t f = 6ns

90%

50%10%90%

GND

V CC 10%

90%

50%

OUTPUT DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS ENABLED

OUTPUTS DISABLED

OUTPUTS ENABLED

6ns 6ns

t PZH t PHZ

t PZL

t PLZ

0.32.7GND

10%

90%

1.3V

OUTPUT DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS ENABLED

OUTPUTS DISABLED

OUTPUTS ENABLED

t r

6ns

t PZH

t PHZ

t PZL

t PLZ

6ns

t f 1.3

IC WITH THREE-STATE OUTPUT OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE

V CC FOR t PLZ AND t PZL GND FOR t PHZ AND t PZH

OUTPUT

R L = 1k ?

C L 50pF

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