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pcie 1.0 总线规范

PCI Express?

Card Electromechanical Specification

Revision 1.1

March 28, 2005

Revision Revision

History Date

release. 7/22/02

1.0 Initial

1.0a Incorporated WG Errata C1-C7 and E1. 4/15/03

1.1 Incorporated approved Errata and ECNs. 03/28/05

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Contact the PCI-SIG office to obtain the latest revision of the specification.

Questions regarding this specification or membership in PCI-SIG may be forwarded to:

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DISCLAIMER

This PCI Express Card Electromechanical Specification is provided “as is” with no

warranties whatsoever, including any warranty of merchantability, noninfringement,

fitness for any particular purpose, or any warranty otherwise arising out of any proposal,

specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary

rights, relating to use of information in this specification. No license, express or implied,

by estoppel or otherwise, to any intellectual property rights is granted herein.

PCI Express is a trademark of PCI-SIG.

All other product names are trademarks, registered trademarks, or service marks of their

respective owners.

Contents

1.INTRODUCTION (7)

1.1.TERMS AND DEFINITIONS (7)

1.2.REFERENCE DOCUMENTS (9)

1.3.SPECIFICATION CONTENTS (9)

1.4.OBJECTIVES (10)

1.5.ELECTRICAL OVERVIEW (10)

1.6.MECHANICAL OVERVIEW (11)

2.AUXILIARY SIGNALS (13)

2.1.REFERENCE CLOCK (14)

2.1.1.Low Voltage Swing, Differential Clocks (14)

2.1.2.Spread Spectrum Clocking (SSC) (15)

2.1.3.REFCLK AC Specifications (16)

2.1.4.REFCLK Phase Jitter Specification (19)

2.2.PERST# SIGNAL (20)

2.2.1.Initial Power-Up (G3 to L0) (20)

2.2.2.Power Management States (S0 to S3/S4 to S0) (21)

2.2.3.Power Down (22)

2.3.WAKE# SIGNAL (24)

2.4.SMBUS (OPTIONAL) (27)

2.4.1.Capacitive Load of High-power SMBus Lines (27)

2.4.2.Minimum Current Sinking Requirements for SMBus Devices (28)

2.4.3.SMBus “Back Powering” Considerations (28)

2.4.4.Power-on Reset (28)

2.5.JTAG PINS (OPTIONAL) (29)

2.6.AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS (30)

2.6.1.DC Specifications (30)

2.6.2.AC Specifications (31)

3.HOT INSERTION AND REMOVAL (33)

3.1.SCOPE (33)

3.2.PRESENCE DETECT (33)

4.ELECTRICAL REQUIREMENTS (35)

4.1.POWER SUPPLY REQUIREMENTS (35)

4.2.POWER CONSUMPTION (36)

4.3.POWER SUPPLY SEQUENCING (37)

4.4.POWER SUPPLY DECOUPLING (38)

4.5.ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS (38)

4.5.1.Topologies (38)

4.5.2.Link Definition (40)

4.6.ELECTRICAL BUDGETS (41)

4.6.1.AC Coupling Capacitors (42)

4.6.2.Insertion Loss Values (Voltage Transfer Function) (42)

4.6.3.Jitter Values (44)

4.6.4.Crosstalk (46)

https://www.wendangku.net/doc/ea12993133.html,ne-to-Lane Skew (46)

4.6.6.Equalization (47)

4.6.7.Skew within the Differential Pair (47)

4.7.EYE DIAGRAMS AT THE ADD-IN CARD INTERFACE (47)

4.7.1.Add-in Card Transmitter Path Compliance Eye-Diagram (48)

4.7.2.Add-in Card Minimum Receiver Path Sensitivity Requirements (49)

4.7.3.System Board Transmitter Path Compliance Eye Diagram (50)

4.7.4.System Board Minimum Receiver Path Sensitivity Requirements (52)

5.CONNECTOR SPECIFICATION (53)

5.1.CONNECTOR PINOUT (53)

5.2.CONNECTOR INTERFACE DEFINITIONS (58)

5.3.SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES (62)

5.4.CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS (65)

5.4.1.Environmental Requirements (65)

5.4.2.Mechanical Requirements (67)

5.4.3.Current Rating Requirement (68)

5.4.4.Additional Considerations (69)

6.ADD-IN CARD FORM FACTORS AND IMPLEMENTATION (71)

6.1.ADD-IN CARD FORM FACTORS (71)

6.2.CONNECTOR AND ADD-IN CARD LOCATIONS (81)

6.3.CARD INTEROPERABILITY (87)

ACKNOWLEDGEMENTS (89)

Figures

FIGURE 1-1: VERTICAL EDGE-CARD CONNECTOR (11)

FIGURE 1-2: EXAMPLE SERVER I/O BOARD WITH PCI EXPRESS SLOTS ON A RISER (12)

FIGURE 2-1: DIFFERENTIAL REFCLK WAVEFORM (14)

FIGURE 2-2: EXAMPLE REFERENCE CLOCK SOURCE TERMINATION (15)

FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING (17)

FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT (17)

FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING (18)

FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD18 FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME (18)

FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK (18)

FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING (19)

FIGURE 2-10: POWER UP (21)

FIGURE 2-11: POWER MANAGEMENT STATES (22)

FIGURE 2-12: OUT-OF-TOLERANCE THRESHOLD WINDOWS (23)

FIGURE 2-13: POWER DOWN (23)

FIGURE 2-14: WAKE# RISE AND FALL TIME MEASUREMENT POINTS (31)

FIGURE 3-1: PRESENCE DETECT IN A HOT-PLUG ENVIRONMENT (34)

FIGURE 4-1: PCI EXPRESS ON THE SYSTEM BOARD (39)

FIGURE 4-2: PCI EXPRESS CONNECTOR ON SYSTEM BOARD WITH AN ADD-IN CARD.39 FIGURE 4-3: PCI EXPRESS CONNECTOR ON A RISER CARD WITH AN ADD-IN CARD (40)

FIGURE 4-4: LINK DEFINITION FOR TWO COMPONENTS (41)

FIGURE 4-5: EXAMPLE INTERCONNECT TERMINATED AT THE CONNECTOR INTERFACE (42)

FIGURE 4-6: INSERTION LOSS BUDGETS (43)

FIGURE 4-7: JITTER BUDGET (44)

FIGURE 4-8: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE DIAGRAM (48)

FIGURE 4-9: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR ADD-IN CARD RECEIVER PATH COMPLIANCE (49)

FIGURE 4-10: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE DIAGRAM (50)

FIGURE 4-11: TWO-PORT MEASUREMENT MODEL (51)

FIGURE 4-12: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR SYSTEM BOARD RECEIVER PATH COMPLIANCE (52)

FIGURE 5-1: CONNECTOR FORM FACTOR (58)

FIGURE 5-2: RECOMMENDED FOOTPRINT (59)

FIGURE 5-3: ADD-IN CARD EDGE-FINGER DIMENSIONS (60)

FIGURE 5-4: ILLUSTRATION OF ADJACENT PAIRS (65)

FIGURE 5-5: CONTACT RESISTANCE MEASUREMENT POINTS (66)

FIGURE 6-1: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET (72)

FIGURE 6-2: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET AND CARD RETAINER (73)

FIGURE 6-3: ADDITIONAL FEATURE AND KEEPOUTS ON THE X16 GRAPHICS CARD (74)

FIGURE 6-4: STANDARD ADD-IN CARD I/O BRACKET (75)

FIGURE 6-5: BRACKET DESIGN WITH THE MOUNTING TABS MOUNTED ON THE PRIMARY SIDE OF THE ADD-IN CARD (76)

FIGURE 6-6: ADD-IN CARD RETAINER (77)

FIGURE 6-7: LOW PROFILE PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET.78 FIGURE 6-8: LOW PROFILE PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET (79)

FIGURE 6-9: LOW PROFILE I/O BRACKET (80)

FIGURE 6-10: EXAMPLE OF A PC SYSTEM IN MICROATX FORM FACTOR (81)

FIGURE 6-11: INTRODUCTION OF A PCI EXPRESS CONNECTOR IN A MICROATX SYSTEM (82)

FIGURE 6-12: MORE PCI EXPRESS CONNECTORS ARE INTRODUCED ON A MICROATX SYSTEM BOARD (83)

FIGURE 6-13: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH ONE PCI EXPRESS CONNECTOR (84)

FIGURE 6-14: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH TWO PCI EXPRESS CONNECTORS (85)

FIGURE 6-15: CARD ASSEMBLED IN CONNECTOR (86)

Tables

TABLE 2-1: REFCLCK DC SPECIFICATIONS AND AC TIMING REQUIREMENTS (16)

TABLE 2-2: MAXIMUM ALLOWED PHASE JITTER WHEN APPLIED TO FIXED FILTER CHARACTERISTIC (20)

TABLE 2-3: AUXILIARY SIGNAL DC SPECIFICATIONS - PERST#, WAKE#, AND SMBUS30 TABLE 2-4: POWER SEQUENCING AND RESET SIGNAL TIMINGS (31)

TABLE 4-1: POWER SUPPLY RAIL REQUIREMENTS (35)

TABLE 4-2: ADD-IN CARD POWER DISSIPATION (36)

TABLE 4-3: ALLOCATION OF INTERCONNECT PATH INSERTION LOSS BUDGET (43)

TABLE 4-4: TOTAL SYSTEM JITTER BUDGET (45)

TABLE 4-5: ALLOCATION OF INTERCONNECT JITTER BUDGET (45)

TABLE 4-6: ALLOWABLE INTERCONNECT LANE-TO-LANE SKEW (47)

TABLE 4-7: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS..48 TABLE 4-8: ADD-IN CARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS49 TABLE 5-1: PCI EXPRESS CONNECTORS PINOUT (53)

TABLE 5-2: SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES (63)

TABLE 5-3: TEST DURATIONS (66)

TABLE 5-4: MECHANICAL TEST PROCEDURES AND REQUIREMENTS (67)

TABLE 5-5: END OF LIFE CURRENT RATING TEST SEQUENCE (68)

TABLE 5-6: ADDITIONAL REQUIREMENTS (69)

TABLE 6-1: ADD-IN CARD SIZES (71)

TABLE 6-2: CARD INTEROPERABILITY (87)

1. Introduction

This specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors.

Other form factors, such as PCI Express Mini Card are covered in other separate specifications.

1.1. Terms

Definitions

and

Add-in card A card that is plugged into a connector and mounted in a chassis

slot.

ATX A system board form factor. Refer to the ATX Specification,

2.2.

Revision.

ATX-based form factor Refers to the form factor that does not exactly conform to the

ATX specification, but uses the key features of the ATX, such as

the slot spacing, I/O panel definition, etc.

Auxiliary signals Signals not required by the PCI Express architecture but necessary

for certain desired functions or system implementation, for

example, the SMBus signals.

Basic bandwidth Contains one PCI Express Lane

x1, x4, x8, x16 x1 refers to one PCI Express Lane of basic bandwidth; x4 refers to a

collection of four PCI Express Lanes; etc.

Down-plugging Plugging a larger Link card into a smaller Link connector; for example, 20

plugging a x4 card into a x1 connector

Down-shifting Plugging a PCI Express card into a connector that is not fully

routed for all of the PCI Express Lanes; for example, plugging

a x4 card into a x8 capable connector with only four Lanes

routed

being

Evolutionary strategy A strategy to develop the PCI Express connector and card form

factors within today’s chassis and system board form factor

constraints.

infrastructure

High bandwidth Supports larger number of PCI Express Lanes, such as a x16 card

connector.

Hot-Plug Insertion and/or removal of a card into an active backplane or

system board as defined in PCI Standard Hot-Plug Controller and

Subsystem Specification, Revision. 1.0. No special card support is required.

Hot swap Insertion and/or removal of a card into a passive backplane. The

card must satisfy specific requirements to support Hot swap.

Interoperability Ability to plug a PCI Express card into different Link connectors

and the system works, for example, plugging a x1 PCI Express

I/O card into a x16 graphics slot.

Link A collection of one or more PCI Express Lanes

Low profile card An add-in card whose height is no more than 68.90 mm

(2.731 inches)

microATX An ATX-based system board form factor. Refer to the microATX

Motherboard Interface Specification, Revision 1.2.

PCI Express Mini Card PCI Express for mobile form factor, similar to Mini PCI

PCI Express Lane One PCI Express Lane contains two differential lines for

Transmitter and two differential lines for Receiver. A by-N Link

is composed of N Lanes.

sideband signaling A method for signaling events and conditions using physical

signals separate from signals forming the Link between two

components.

Standard height card An add-in card whose height is no more than 111.15 mm

inches)

(4.376

Up-plugging Plug a smaller Link card into a larger Link connector; for

example, plugging a x1 card into a x4 connector

wakeup A mechanism used by a component to request the reapplication of

main power when in the L2 Link state. Two such mechanisms are

defined in the PCI Express Base Specification, Revision 1.1: Beacon and

WAKE#. This specification requires the use of WAKE# on any add-in

card or system board that supports wakeup functionality.

Documents

1.2. Reference

This specification references the following documents:

PCI Express Base Specification, Revision 1.1

PCI Local Bus Specification, Revision 3.0

PCI Express Jitter Modeling

PCI Express Jitter and BER

ATX Specification, Revision 2.2

microATX Motherboard Interface Specification, Revision 1.2

SMBus Specification, Revision 2.0

JTAG Specification (IEEE1149.1)

PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0

Compact PCI Hot Swap Specification

EIA-364-1000.01: Environmental Test Methodology for Assessing the Performance of Electrical Connectors and Sockets Used in Business Office Applications

EIA-364: Electrical Connector/Socket Test Procedures Including Environmental Classifications

Contents

1.3. Specification

This specification contains the following information:

Auxiliary signals

Add-in card hot insertion and removal

Power delivery

Add-in card electrical budget

Connector specification

Card form factors and implementation

1.4. Objectives

The objectives of this specification are:

Support 2.5 Gb/s data rate (per direction) with headroom for future bandwidth increases

Enable Hot-Plug and hot swap where they are needed

Leverage desktop and server commonality

Facilitate smooth transitions

Allow co-existence of both PCI and PCI Express add-in cards

No chassis or other PC infrastructure changes

Forward looking for future scalability

Extensible for future bandwidth needs

Allows future evolution of PC architecture

Maximize card interoperability for user flexibility

Low cost

1.5. Electrical Overview

The electrical part of this specification covers auxiliary signals, hot insertion and removal, power

delivery, and add-in card interconnect electrical budgets for the evolutionary strategy. The PCI

Express Transmitter and Receiver electrical requirements are specified in the PCI Express Base

Specification, Revision 1.1.

Besides the signals that are required to transmit/receive data on the PCI Express interface, there are

also signals that may be necessary to implement the PCI Express interface in a system environment, 20

or to provide certain desired functions. These signals are referred to as the auxiliary signals. They include:

Reference clock (REFCLK), must be supplied by the system (see Section 2.1.1)

Add-in card presence detect pins (PRSNT1# and PRSNT2#), required

PERST#, required

JTAG, optional

SMBus, optional

Wake (WAKE#), required only if the device/system supports wakeup

+3.3Vaux, optional

REFCLK, JTAG, SMBus, PERST#, and WAKE# are described in Chapter 2; +3.3Vaux is

described in Chapter 4; and PRSNT1# and PRSNT2# are described in Chapter 3.

Both Hot-Plug and hot swap of PCI Express add-in cards are supported, but their implementation is

optional. Hot-Plug is supported with the evolutionary add-in card form factor. Hot swap is

supported with other form factors and will be described in other specifications.

To support Hot-Plug, presence detect pins (PRSNT1# and PRSNT2#) are defined in each end of the connectors and add-in cards. Those presence detect pins are staggered on the add-in cards such 5

that they are last-mate and first-break, detecting the presence of the add-in cards. Chapter 3

discusses the detailed implementation of PCI Express Hot-Plug.

Chapter 4 specifies the PCI Express add-in card electrical requirements, which include power

delivery and interconnect electrical budgets. Power is delivered to the PCI Express add-in cards via

add-in card connectors, using three voltage rails: +3.3V, +3.3Vaux, and +12V. Note that the

+3.3Vaux voltage rail is not required for all platforms (refer to Section 4.1 for more information on the required usage of 3.3Vaux). The maximum add-in card power definitions are based on the card size and Link widths, and are described in Section 4.2. Chapter 4 describes the interconnect

electrical budgets, focusing on the add-in card loss and jitter requirements.

Overview

1.6. Mechanical

PCI Express can be used in many different applications in desktop, mobile, server, as well as

networking and communication equipment. Consequently, multiple variations of form factors and connectors will exist to suit the unique needs of these different applications.

Figure 1-1 shows an example of the vertical edge-card PCI Express connector to be used in ATX or ATX-based systems. There will be a family of such connectors, containing one to 16 PCI Express

Lanes. The basic bandwidth (BW) version supports one PCI Express Lane and could be used as the 20

replacement for the PCI connector. The high bandwidth version will support 16 PCI Express Lanes and will be used for applications that require higher bandwidth, such as graphics.

OM14739

Figure 1-1: Vertical Edge-Card Connector

Vertical edge card connectors also have applications in the server market segment. Figure 1-2 shows an example of a server configuration using a PCI Express riser card.

OM14740

Figure 1-2: Example Server I/O Board with PCI Express Slots on a Riser Mobile applications require a right angle edge card connector. The definition of such a connector will be covered in a separate document.

For certain server and network applications there may also be a need for a Compact PCI-like PCI Express connector, or other backplane-type PCI Express connectors.

PCI Express cable connectors may also be needed for within-system applications, both internally 5

(inside the chassis) and externally (outside the chassis).

While the reality of multiple variations of PCI Express connectors and form factors is recognized, no attempt will be made to define every possible PCI Express connector and form factor variation in this specification. They will be defined later as the need arises in other specifications. This

specification, instead, focuses on the vertical edge card PCI Express connectors and form factor 10

requirements by covering the following:

Connector mating interfaces and footprints

Electrical, mechanical, and reliability requirements of the connectors, including the connector testing procedures

Add-in card form factors

Connector and add-in card locations, as well as keep-outs on a typical desktop system board (ATX/microATX form factor)

Connector definitions and requirements are addressed in Chapter 5 and add-in card form factors and implementation are discussed in Chapter 6.

2. Auxiliary Signals

The auxiliary signals are provided on the connector to assist with certain system level functionality or implementation. These signals are not required by the PCI Express architecture. The high-speed signal voltage levels are compatible with advanced silicon processes. The optional low speed signals are defined to use the +3.3V or +3.3Vaux supplies, as they are the lowest common voltage available. 5 Most ASIC processes have high voltage (thick gate oxide) I/O transistors compatible with 3.3 V. Use of the 3.3 V supply allows PCI Express signaling to be used with existing control bus structures, avoiding a buffered set of signals and bridges between the buses.

The PCI Express connector and add-in card interfaces support the following auxiliary signals: REFCLK-/REFCLK+ (required): low voltage differential signals.

10 PERST# (required): indicates when the applied main power is within the specified tolerance and

stable. PERST# goes inactive after a delay of T PVPERL time from the power rails achieving

specified tolerance on power up.

WAKE#: an open-drain, active low signal that is driven low by a PCI Express function to re-activate the PCI Express Link hierarchy’s main power rails and reference clocks. It is required

15 on any add-in card or system board that supports wakeup functionality compliant with this

specification.

SMBCLK (optional): the SMBus interface clock signal. It is an open-drain signal.

SMBDAT (optional): the SMBus interface address/data signal. It is an open-drain signal. JTAG (TRST#, TCLK, TDI, TDO, and TMS) (optional): the pins to support IEEE Standard 20

1149.1, Test Access Port and Boundary Scan Architecture (JTAG). They are included as an optional interface for PCI Express devices. IEEE Standard 1149.1 specifies the rules and permissions for designing an 1149.1-compliant IC.

PRSNT1# (required): Add-in card presence detect pin. See Chapter 3 for a detailed description. PRSNT2# (required): Add-in card presence detect pin. See Chapter 3 for a detailed description. 25 Note that the SMBus interface pins are collectively optional for both the add-in card and the system board. If the optional management features are implemented, SMBCLK and SMBDAT are both required. Similarly, the JTAG pins are collectively optional. If this test mode is implemented, all the JTAG pins are required. Refer to the PCI Local Bus Specification, Revision. 3.0, Section 4.3.3 for additional system requirements related to these signals. 30 2

2.1. Reference Clock

2.1.1. Low Voltage Swing, Differential Clocks

To reduce jitter and allow for future silicon fabrication process changes, low voltage swing,

differential clocks are being used, as illustrated in Figure 2-1. The nominal single-ended swing for each clock is 0 to 0.7 V and a nominal frequency of 100 MHz ±300 PPM. The clock has a defined 5

crossover voltage range and monotonic edges through the input threshold regions as specified in Chapter 4.

REFCLK–REFCLK+

OM14741

Figure 2-1: Differential REFCLK Waveform

The reference clock pair is routed point-to-point to each connector from the system board

according to best-known clock routing rules. The reference clock distribution to all devices must be matched to within 15 inches on the system board. The phase delay between the transmitter and 10 receiver clock is assumed to be less than 10 ns. The combination of the maximum reference clock mismatch and the maximum channel length will contribute approximately 7-8 ns and the remaining time is allocated to the difference in the insertion delays of the Tx and Rx devices. The routing of each signal in any given clock pair between the clock source and the connector must be well

matched in length (< 0.005 inch) and appropriately spaced away from other non-clock signals to 15 avoid excessive crosstalk.

The add-in card is not required to use the reference clock on the connector. However, the add-in card is required to maintain the 600-ppm data rate matching specified in Section 4.3.1.1 of the PCI Express Base Specification, Revision 1.1.

Any terminations required by the clock are to be on the system board. An example termination

20 topology for a current-mode clock generator is shown in Figure 2-2. EMI emissions will be reduced if clocks to open sockets are shut down at the clock source. The method for detecting the presence of a card in a slot and controlling the clock gating is platform specific and is not covered in this specification.

A-0439

Figure 2-2: Example Reference Clock Source Termination Termination on the add-in card is allowed, but is not covered by the specifications in Section 2.1.3.

While the same measurement techniques can be used as specified in that section, receiver

termination will reduce the nominal swing and rise and fall times by half. The low input swing and low slew rates need to be validated against the clock receiver requirements as they can cause

excessive jitter in some clock input buffer designs.

The reference clock timings are based on nominal 100 ?, differential pair routing with

approximately 5-mil trace widths. This timing budget allows for a maximum add-in card trace

length of 4.0 inches. No specific trace geometry, however, is explicitly defined in this specification.

2.1.2. Spread Spectrum Clocking (SSC)

The reference clocks may support spread spectrum clocking. Any given system design may or may 10

not use this feature due to platform-level timing issues. The minimum clock period cannot be

violated. The preferred method is to adjust the spread technique to not allow for modulation above the nominal frequency. This technique is often called “down-spreading.” The requirements for spread spectrum modulation rate and magnitude are given in the PCI Express Base Specification,

Revision 1.1.

2.1.

3. REFCLK AC Specifications

All specifications in Table 2-1 are to be measured using a test configuration as described in Note 11 with a circuit as shown in Figure 2-9.

Table 2-1: REFCLCK DC Specifications and AC Timing Requirements

100 MHz Input Unit Note Symbol Parameter

Min Max

Rise Edge Rate Rising Edge Rate 0.6 4.0 V/ns 2, 3

Fall Edge Rate Falling Edge Rate 0.6 4.0 V/ns 2, 3

V IH Differential Input High Voltage +150 mV 2

V IL Differential Input Low Voltage -150 mV 2

V CROSS Absolute crossing point voltage +250 +550 mV 1,4,5

V CROSS DELTA Variation of V CROSS over all rising

clock edges

+140 mV 1,4,9

V RB Ring-back Voltage Margin -100 +100 mV 2,12 T STABLE Time before V RB is allowed 500 ps 2,12 T PERIOD AVG Average Clock Period Accuracy -300 +2800 ppm 2,10,13

T PERIOD ABS Absolute Period (including Jitter

and Spread Spectrum)

9.847 10.203 ns 2,6

T CCJITTER Cycle to Cycle jitter 150 ps 2 V MAX Absolute Max input voltage +1.15 V 1,7 V MIN Absolute Min input voltage - 0.3 V 1,8 Duty Cycle Duty Cycle 40 60 % 2

Rise-Fall Matching Rising edge rate (REFCLK+) to

falling edge rate (REFCLK-)

matching

20 % 1,14

Z C-DC Clock source DC impedance 40 60 ?1,11

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus

REFCLK-). The signal must be monotonic through the measurement region for rise and fall time.

The 300 mV measurement window is centered on the differential zero crossing. See Figure 2-7.

4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+

equals the falling edge of REFCLK-. See Figure 2-3.

5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge

is crossing. Refers to all crossing points for this measurement. See Figure 2-3.

6. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle

jitter, relative PPM tolerance, and spread spectrum modulation. See Figure 2-6.

7. Defined as the maximum instantaneous voltage including overshoot. See Figure 2-3.

8. Defined as the minimum instantaneous voltage including undershoot. See Figure 2-3.

9. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-.

This is the maximum allowed variance in VCROSS for any particular system. See Figure 2-4.

10. Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information

5 regarding PPM considerations.

11. System board compliance measurements must use the test load card described in Figure 2-9.

REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must

be used for measurements requiring single ended measurements. Either single ended probes with

math or differential probe can be used for differential measurements. Test load C L = 2 pF.

10 12. T STABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after

rising/falling edges before it is allowed to droop back into the V RB ±100 mV differential range. See

Figure 2-8.

13. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is

1/1,000,000th of 100.000000 MHz exactly or 100 Hz. For 300 PPM then we have a error budget of

15 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency counter with

measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not

employ Spread Spectrum or that use common clock source. For systems employing Spread

Spectrum there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5%

down spread resulting in a maximum average period specification of +2800 PPM

20 14. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is

measured using a ±75 mV window centered on the median cross point where REFCLK+ rising

meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be

compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed

25 20% of the slowest edge rate. See Figure 2-5.

REFCLK–

A-0437

REFCLK+

V MAX = 1.15 V

V MIN = -0.30 V

V CROSS MAX = 550 mV

V CROSS MIN = 250 mV

Figure 2-3: Single-Ended Measurement Points for Absolute Cross Point and Swing

REFCLK–

A-0438REFCLK+

Figure 2-4: Single-Ended Measurement Points for Delta Cross Point

A-0434REFCLK-REFCLK+

V CROSS MEDIAN T

Figure 2-5: Single-Ended Measurement Points for Rise and Fall Time Matching

A-0435REFCLK+

minus

0.0 V

Figure 2-6: Differential Measurement Points for Duty Cycle and Period

A-0436Rise Edge Rate Fall Edge Rate

REFCLK+

minus

V IH = +150 mV

V IL = -150 mV

0.0 V

Figure 2-7: Differential Measurement Points for Rise and Fall Time

A-0432

ST ABLE

minus V

IH = +150 mV

V IL = -150 mV

0.0 V

V RB = +100 mV

V RB = -100 mV

Figure 2-8: Differential Measurement Points for Ringback

A-0433

Figure 2-9: Reference Clock System Measurement Point and Loading

2.1.4. REFCLK Phase Jitter Specification

The phase jitter of the reference clock is to be measured using the following clock recovery function

[])(*)()()(3_*21s H e s H s H s H delay t s ??=?

where:

2112211122)(ωζωωζω+++=

s s s s H , 2

22222

2222)(ωζωωζω+++=s s s s H , 33)(ω+=

s s s H , ()()s

delay t s

Rad s Rad s Rad 9632

2262222611010_/105.1**2/12121105.1**2/121211022**254

.0??=?=++++?=++++?=

=πωζζπωζζπωζ

The maximum allowed magnitude of the peak-peak reference clock jitter is given in Table 2-2. For information about the maximum peak-peak phase jitter value refer to PCI Express Jitter Modeling .

5 Multiple methods can be used to measure the maximum allowed peak-peak phase jitter value. Real time sampling scopes must use a sampling rate of 20 giga-samples per second or better and take enough data to guarantee the proper bit error rate (BER). Reference clock measurements for cards

should be taken with a differential, high-impedance probe using the circuit of Figure 2-9 at the load capacitors CL. Measurements for devices on the same board should be made using a differential, high-impedance probe as close to the REFCLK+ and REFCLK- input pins as possible.

Table 2-2: Maximum Allowed Phase Jitter When Applied to Fixed Filter Characteristic BER Maximum Peak-Peak Phase Jitter Value (ps)

10-6 86

10-12 108

2.2. PERST#

Signal

The PERST# signal is used to indicate when the power supply is within its specified voltage

tolerance and is stable. It also initializes a component’s state machines and other logic once power

supplies stabilize. On power up, the deassertion of PERST# is delayed 100 ms (T

PVPERL ) from the

power rails achieving specified operating limits. Also, within this time, the reference clocks

(REFCLK+, REFCLK-) also become stable, at least T

PERST-CLK before PERST# is deasserted.

PERST# is asserted in advance of the power being switched off in a power-managed state like S3.

PERST# is asserted when the power supply is powered down, but without the advanced warning of the transition.

2.2.1. Initial Power-Up (G3 to L0)

As long as PERST# is active, all PCI Express functions are held in reset. The main supplies ramp

up to their specified levels (3.3 V and 12 V). Some time during this stabilization time, the REFCLK 15

starts and stabilizes. After there has been time (T

PVPERL ) for the power and clock to become stable,

PERST# is deasserted high and the PCI Express functions can start up.

On initial power-up, the hardware default state of the Active State Power Management Control field in the Link Control Register must be set to 00b. The state of this field may be changed by the

system BIOS or the operating system only. Other software agents are not allowed to change this

field.