TPS51200
FEATURES APPLICATIONS
DESCRIPTION STANDARD DDR APPLICATION
VLDOIN
VTT VDDQ TPS51200
SLUS812–FEBRUARY 2008
https://www.wendangku.net/doc/eb13028793.html, SINK/SOURCE DDR TERMINATION REGULATOR
?
Memory Termination Regulator for DDR,?Input Voltage:Supports 2.5-V Rail and 3.3-V DDR2,DDR3,and Low Power DDR3/DDR4Rail ?
Notebook/Desktop/Server ?VLDOIN Voltage Range:1.1V to 3.5V ?Telecom/Datacom,GSM Base Station,?Sink/Source Termination Regulator Includes
LCD-TV/PDP-TV,Copier/Printer,Set-Top Box Droop Compensation
?Requires Minimum Output Capacitance of
20-μF (typically 3×10-μF MLCCs)for Memory
The TPS51200is a sink/source Double Data Rate Termination Applications (DDR)
(DDR)termination regulator specifically designed for ?PGOOD to Monitor Output Regulation
low input voltage,low-cost,low-noise systems where ?EN Input
space is a key consideration.?REFIN Input Allows for Flexible Input Tracking
The TPS51200maintains a fast transient response Either Directly or Through Resistor Divider
and only requires a minimum output capacitance of ?Remote Sensing (VOSNS)
20μF.The TPS51200supports a remote sensing function and all power requirements for DDR,DDR2,?±10-mA Buffered Reference (REFOUT)
DDR3,and Low Power DDR3/DDR4VTT bus ?Built-in Soft Start,UVLO and OCL
termination.?Thermal Shutdown
In addition,the TPS51200provides an open-drain ?Meets DDR,DDR2JEDEC Specifications;
PGOOD signal to monitor the output regulation and Supports DDR3and Low-Power DDR3/DDR4
an EN signal that can be used to discharge VTT VTT Applications
during S3(suspend to RAM)for DDR applications.?SON-10PowerPAD?Package The TPS51200is available in the thermally-efficient
SON-10PowerPAD package,and is rated both
Green and Pb-free.It is specified from -40°C to
+85°C.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
https://www.wendangku.net/doc/eb13028793.html, ABSOLUTE MAXIMUM RATINGS(1)
DISSIPATION RATINGS TABLE(1)
RECOMMENDED OPERATING CONDITIONS
TPS51200
SLUS812–FEBRUARY2008
These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T A PACKAGE DEVICE NUMBER PINS MEDIUM MINIMUM
QUANTITY
TPS51200DRCT250–40°C to85°C DRC Plastic Small Outline10Tape and Reel
TPS51200DRCR3000
Over operating free-air temperature range,unless otherwise noted.
VALUE UNIT
VIN,VLDOIN,VOSNS,REFIN–0.3to3.6 Input voltage range(2)EN–0.3to6.5V
PGND to GND–0.3to0.3
VO,REFOUT–0.3to3.6 Output voltage range(2)V
PGOOD–0.3to6.5
T stg Storage temperature–55to150°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)All voltage values are with respect to the network ground terminal unless otherwise noted.
DERATING FACTOR T A=85°C
T A=25°C
PACKAGE POWER RATING ABOVE T A=25°C POWER RATING
10-Pin SON 1.92W19mW/°C0.79W
(1)PowerPAD size:3.0×1.9mm,4standard thermal vias.Based on the above environment,junction to thermal pad resistanceθJP is
10.24°C/W.Junction to ambient thermal resistanceθJA is52.06°C/W.
PARAMETER MIN TYP MAX UNIT Supply voltages VIN 2.375 3.500
EN,VLDOIN,VOSNS–0.1 3.5
REFIN0.5 1.8
V Voltage range VO,PGOOD–0.1 3.5
REFOUT–0.1 1.8
PGND–0.10.1
Operating free-air temperature,T A–4085°C
https://www.wendangku.net/doc/eb13028793.html,
ELECTRICAL CHARACTERISTICS
TPS51200 SLUS812–FEBRUARY2008
Over recommended free-air temperature range,V VIN=3.3V,V VLDOIN=1.8V,V REFIN=0.9V,V VOSNS=0.9V,V EN=V VIN,C OUT =3×10μF and circuit shown in Section1.(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I IN Supply current T A=25°C,V EN=3.3V,No Load0.71mA
T A=25°C,V EN=0V,V REFIN=0,No Load6580
I IN(SDN)Shutdown currentμA
T A=25°C,V EN=0V,V REFIN>0.4V,No Load200400
I LDOIN Supply current ofVLDOIN T A=25°C,V EN=3.3V,No Load150μA
I LDOIN(SDN)Shutdown current of VLDOIN T A=25°C,V EN=0V,No Load0.150μA INPUT CURRENT
I REFIN Input current,REFIN V EN=3.3V1μA VO OUTPUT
1.25V
V REFOUT=1.25V(DDR1),I O=0A
–1515mV
0.9V
V VOSNS Output DC voltage,VO V REFOUT=0.9V(DDR2),I O=0A
–1515mV
0.75V
V LDOIN=1.5V,V REFOUT=0.75V(DDR3),I O=0A
–1515mV
Output voltage tolerance to
V VOTOL–2A
I VOSRCL VO source vurrent Limit With reference to REFOUT,V OSNS=90%×V REFOUT3 4.5A
I VOSNCL VO sink current Limit With reference to REFOUT,V OSNS=110%×V REFOUT 3.5 5.5A
I DSCHRG Discharge current,VO V REFIN=0V,V VO=0.3V,V EN=0V,T A=25°C1825?POWERGOOD COMPARATOR
PGOOD window lower threshold with respect to REFOUT–23.5%–20%–17.5%
V TH(PG)VO PGOOD threshold PGOOD window upper threshold with respect to REFOUT17.5%20%23.5%
PGOOD hysteresis5%
T PGSTUPDLY PGOOD startup delay Startup rising edge,VOSNS within15%of REFOUT2ms
V PGOODLOW Output low voltage I SINK=4mA0.4V
T PBADDLY PGOOD bad delay VOSNS is outside of the±20%PGOOD window10μs
V OSNS=V REFIN(PGOOD high impedance),
I PGOODLK Leakage current(1)1μA
PGOOD=V IN+0.2V
REFIN AND REFOUT
V REFIN REFIN voltage range0.5 1.8V
V REFINUVLO REFIN undervoltage lockout REFIN rising360390420mV
REFIN undervoltage lockout
V REFINUVHYS20mV hysteresis
V REFOUT REFOUT voltage REFIN V
–10mA
–10mA
V REFOUTTOL
V REFIN–10mA REFOUT <10mA,V REFIN=0.75V–1515 –10mA I REFOUTSRCL REFOUT source current limit V REFOUT=0V1040mA I REFOUTSNCL REFOUT sink current limit V REFOUT=0V1040mA (1)Ensured by design.Not production tested. https://www.wendangku.net/doc/eb13028793.html, TPS51200SLUS812–FEBRUARY 2008ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range,V VIN =3.3V,V VLDOIN =1.8V,V REFIN =0.9V,V VOSNS =0.9V,V EN =V VIN ,C OUT =3×10μF and circuit shown in Section 1.(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVLO /EN LOGIC THRESHOLD Wake up,T A =25°C 2.2 2.3 2.375V V VINUVVIN UVLO threshold Hysteresis 50mV V ENIH High-level input voltage Enable 1.7V ENIL Low-level input voltage Enable 0.3V V ENYST Hysteresis voltage Enable 0.5I ENLEAK Logic input leakage current EN,T A =25°C –11μA THERMAL SHUTDOWN Shutdown temperature 150T SON Thermal shutdown threshold (2)°C Hysteresis 25(2)Ensured by design.Not production tested. https://www.wendangku.net/doc/eb13028793.html, DEVICE INFORMATION DRC PACKAGE 12 3 4 5 109876VOSNS PGND VO VLDOIN REFIN REFOUT EN GND PGOOD VIN TPS51200 (Bottom View)TPS51200SLUS812–FEBRUARY 2008 TERMINAL FUNCTIONS TERMINAL NAME NO.I/O DESCRIPTION EN 7I For DDR VTT application,connect EN to SLP_S3.For any other application(s),use EN as the ON/OFF function.GND 8–Ground.Signal ground.Connect to negative terminal of the output capacitor.PGND 4–Power ground output for the LDO PGOOD 9O PGOOD output.Indicates regulation.REFIN 1I Reference input REFOUT 6O Reference output.Connect to GND through 0.1-μF ceramic capacitor.VIN 10I 2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is required.VLDOIN 2I Supply voltage for the LDO VO 3O Power output for the LDO VOSNS 5I Voltage sense output for the LDO.Connect to positive terminal of the output capacitor or the load. https://www.wendangku.net/doc/eb13028793.html, FUNCTIONAL BLOCK DIAGRAM REFIN VIN EN VOSNS GND VLDOIN REFOUT PGND VO PGOOD UDG-08019 TPS51200 SLUS812–FEBRUARY2008 https://www.wendangku.net/doc/eb13028793.html, DETAILED DESCRIPTION VO SINK/SOURCE REGULATOR REFERENCE INPUT(REFIN) REFERENCE OUTPUT(REFOUT) SOFT-START EN CONTROL(EN) POWERGOOD FUNCTION(PGOOD) VO CURRENT PROTECTION VIN UVLO PROTECTION TPS51200 SLUS812–FEBRUARY2008 The TPS51200is a sink/source tracking termination regulator specifically designed for low input voltage, low-cost,and low external component count systems where space is a key application parameter.The TPS51200integrates a high-performance,low-dropout(LDO)linear regulator that is capable of both sourcing and sinking current.The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response.To achieve tight regulation with minimum effect of trace resistance,a remote sensing terminal,VOSNS,should be connected to the positive terminal of the output capacitor(s)as a separate trace from the high current path from VO. The output voltage,VO,is regulated to REFOUT.When REFIN is configured for standard DDR termination applications,REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply bus(VDDQ).The TPS51200supports REFIN voltage from0.5V to1.8V,making it versatile and ideal for many types of low-power LDO applications. When it is configured for DDR termination applications,REFOUT generates the DDR VTT reference voltage for the memory application.It is capable of supporting both a sourcing and sinking load of10mA.REFOUT becomes active when REFIN voltage rises to0.390V and VIN is above the UVLO threshold.When REFOUT is less than0.375V,it is disabled and subsequently discharges to GND through an internal10-k?MOSFET. REFOUT is independent of the EN pin state. The soft-start function of the VO pin is achieved via a current clamp.The current clamp allows the output capacitors to be charged with low and constant current,providing a linear ramp-up of the output voltage.When VO is outside of the powergood window,the current clamp level is one-half of the full overcurrent limit(OCL) level.When VO rises or falls within the PGOOD window,the current clamp level switches to the full OCL level. The soft-start function is completely symmetrical;it works not only from GND to the REFOUT voltage,but also from VLDOIN to the REFOUT voltage. When EN is driven high,the TPS51200VO regulator begins normal operation.When EN is driven low,VO is discharges to GND through an internal18-?MOSFET.REFOUT remains on when EN is driven low. The TPS51200provides an open-drain PGOOD output that goes high when the VO output is within±20%of REFOUT.PGOOD de-asserts within10μs after the output exceeds the size of the powergood window.During initial VO startup,PGOOD asserts high2ms(typ)after the VO enters power good window.Because PGOOD is an open-drain output,a100-k?,pull-up resistor between PGOOD and a stable active supply voltage rail is required. The LDO has a constant overcurrent limit(OCL).Note that the OCL level reduces by one-half when the output voltage is not within the powergood window.This reduction is a non-latch protection. For VIN undervoltage lockout(UVLO)protection,the TPS51200monitors VIN voltage.When the VIN voltage is lower than the UVLO threshold voltage,both the VO and REFOUT regulators are powered off.This shutdown is a non-latch protection. https://www.wendangku.net/doc/eb13028793.html, THERMAL SHUTDOWN TPS51200SLUS812–FEBRUARY 2008The TPS51200monitors the its junction temperature.If the device junction temperature exceeds its threshold value,(typically 150°C),the VO and REFOUT regulators are both shut off,discharged by the internal discharge MOSFETs.This shutdown is a non-latch protection. https://www.wendangku.net/doc/eb13028793.html, APPLICATION INFORMATION VIN CAPACITOR VLDO INPUT CAPACITOR OUTPUT CAPACITOR Low VIN Applications S3and Pseudo-S5Support Tracking Startup and Shutdown TPS51200 SLUS812–FEBRUARY2008 Add a ceramic capacitor,with a value between1.0-μF and4.7-μF,placed close to the VIN pin,to stabilize the bias supply(2.5-V rail or3.3-V rail)from any parasitic impedance from the supply. Depending on the trace impedance between the VLDOIN bulk power supply to the device,a transient increase of source current is supplied mostly by the charge from the VLDOIN input https://www.wendangku.net/doc/eb13028793.html,e a10-μF(or greater) ceramic capacitor to supply this transient charge.Provide more input capacitance as more output capacitance is used at VO.In general,use one-half of the C OUT value for input. For stable operation,the total capacitance of the VO output terminal must be greater than20μF.Attach three, 10-μF ceramic capacitors in parallel to minimize the effect of equivalent series resistance(ESR)and equivalent series inductance(ESL).If the ESR is greater than2m?,insert an R-C filter between the output and the VOSNS input to achieve loop stability.The R-C filter time constant should be almost the same as or slightly lower than the time constant of the output capacitor and its ESR. TPS51200can be used in an application system where either a2.5-V rail or a3.3-V rail is available.If only a5-V rail is available,TPS51100can be used instead.The TPS51200minimum input voltage requirement is2.375V. If a2.5-V rail is used,ensure that the absolute minimum voltage(both DC and transient)at the device pin is be 2.375V or greater.The voltage tolerance for a2.5-V rail input is between–5%and5%accuracy,or better. The TPS51200provides S3support by an EN function.The EN pin could be connected to an SLP_S3signal in the end application.Both REFOUT and VO are on when EN=high(S0state).REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN=low(S3state).When EN=low and the REFIN voltage is less than0.390V,TPS51200enters pseudo-S5state.Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5support is engaged(S4/S5 state).Figure1shows a typical startup and shutdown timing diagram for an application that uses S3and The TPS51200also supports tracking startup and shutdown when EN is tied directly to the system bus and not used to turn on or turn off the device.During tracking startup,VO follows REFOUT once REFIN voltage is greater than0.39V.REFIN follows the rise of VDDQ rail via a voltage divider.The typical soft-start time for the VDDQ rail is approximately3ms,however it may vary depending on the system configuration.The SS time of the VO output no longer depends on the OCL setting,but it is a function of the SS time of the VDDQ rail. PGOOD is asserted2ms after VO is within±20%of REFOUT.During tracking shutdown,VO falls following REFOUT until REFOUT reaches0.37V.Once REFOUT falls below0.37V,the internal discharge MOSFETs are turned on and quickly discharge both REFOUT and VO to GND.PGOOD is deasserted once VO is beyond the ±20%range of REFOUT.Figure2shows the typical timing diagram for an application that uses tracking startup and shutdown. https://www.wendangku.net/doc/eb13028793.html, PGOOD VO REFIN REFOUT (VTTREF) VLDOIN 3.3VIN EN (S3_SLP) PGOOD t SS determined by the SS time of VLDOIN VO V VO =0.75V REFOUT (VTTREF) REFIN VLDOIN 3.3VIN EN TPS51200 SLUS812–FEBRUARY 2008Figure 1.Typical Timing Diagram for S3and pseudo-S5Support Figure 2.Typical Timing Diagram of Tracking Startup and Shutdown https://www.wendangku.net/doc/eb13028793.html, Output Tolerance Consideration for VTT DIMM Applications UDG-08022 V TT V DDQ Ouput Buffer (Driver) V SS UDG-08023 Q2 TPS51200 SLUS812–FEBRUARY2008 The TPS51200is specifically designed to power up the memory termination rail(as shown in Figure3).The DDR memory termination structure determines the main characteristics of the VTT rail,which is to to sink and source current while maintaining acceptable VTT tolerance.See Figure4for typical characteristics for a single memory cell. Figure3.Typical Application Diagram for DDR3VTT DIMM using TPS51200 Figure4.DDR Physical Signal System Bi-Directional SSTL Signaling In Figure4,when Q1is on and Q2is off: ?Current flows from VDDQ via the termination resistor to VTT ?VTT sinks current In Figure4,when Q2is on and Q1is off: ?Current flows from VTT via the termination resistor to GND ?VTT sources current https://www.wendangku.net/doc/eb13028793.html, UGBW OUT Gm F 2C = ′p ′(1)TPS51200SLUS812–FEBRUARY 2008Because VTT accuracy has a direct impact on the memory signal integrity,it is imperative to understand the tolerance requirement on VTT.Based on JEDEC VTT specifications for DDR and DDR2(JEDEC standard:DDR JESD8-9B May 2002;DDR2JESD8-15A Sept 2003). VTTREF –40mV The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning. The TPS51200ensures the regulator output voltage to be: VTTREF –25mV The regulator output voltage is measured at the regulator side,not the load side.The tolerance is applicable to DDR,DDR2,DDR3and Low Power DDR3/DDR4applications (see Table 1for detailed information).To meet the stability requirement,a minimum output capacitance of 20μF is the actual tolerance on the MLCC capacitors,three 10-μF ceramic capacitors are sufficient to meet the above requirement. Table 1.DDR,DDR2,DDR3and LP DDR3Termination Technology and Their Differences Low Power DDR DDR2DR3DDR3FSB Data Rates 200,266,333and 400MHz 400,533,677and 800MHz 800,1066,1330and 1600MHz Same as DDR3On-die termination for data group.On-die termination for data group.Motherboard termination to Termination VTT termination for address, VTT termination for address,Same as DDR3VTT for all signals command and control signals command and control signals Not as demanding Not as demanding Same as DDR3Only 34signals (address,Only 34signals (address,Max source/sink transient ?command,control)tied to ?command,control)tied to Termination currents of up to 2.6A to VTT VTT Current Demand 2.9A ?ODT handles data signals ?ODT handles data signals Less than 1A of burst current Less than 1A of burst current 2.5V Core and I/O 1.25V 1.2V Core and Voltage Level 1.8V Core and I/O 0.9V VTT 1.5V Core and I/O 0.75V VTT VTT I/O 0.6V VTT The TPS51200is designed as a Gm driven LDO.The voltage droop between the reference input and the output regulator is determined by the transconductance and output current of the device.The typical Gm is 250S at 2A and changes with respect to the load in order to conserve the quiescent current (that is,the Gm is very low at no load condition).The Gm LDO regulator is a single pole system.Its unity gain bandwidth for the voltage loop is only determined by the output capacitance,as a result of the bandwidth nature of the Gm (see Equation 1). where ? F UGBW is the unity gain bandwidth ? Gm is transconductance ?C OUT is the output capacitance There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement.In order to maintain stablility,the zero location contributed by the ESR of the output capacitors should be greater than the -3-dB point of the current loop.This constraint means that higher ESR capacitors should not be used in the design.In addition,the impedance characteristics of the ceramic capacitor should be well understood in order to prevent the gain peaking effect around the Gm –3-dB point because of the large ESL,the output capacitor and parasitic inductance of the VO trace. https://www.wendangku.net/doc/eb13028793.html, TPS51200 SLUS812–FEBRUARY2008 Figure5.Bode Plot for a Typical DDR3Configuration Figure5shows the bode plot simulation for a typical DDR3configuration of the TPS51200,where: ?V IN=3.3V ?V VLDOIN=1.5V ?V VO=0.75V ?I IO=2A ?3×10-μF capacitors included ?ESR=2.5m? ?ESL=800pH The unity-gain bandwidth is approximately1MHz and the phase margin is52°.The0-dB level is crossed,the gain peaks because of the ESL effect.However,the peaking is kept well below0dB. Figure6shows the load regulation and Figure7shows the transient response for a typical DDR3configuration. regulator is subjected to step and release,the output voltage measurement shows no difference between the dc and ac conditions. https://www.wendangku.net/doc/eb13028793.html, -3-1-201 23 I OUT –Output Current –A 730 700 720 760 740 750 790 770 780 V O U T –O u t p u t V o l t a g e –m V 710 LDO Design Guidelines TPS51200SLUS812–FEBRUARY 2008OUTPUT VOLTAGE vs OUTPUT CURRENT Figure 6.DC Regulaltion Figure 7.Transient The minimum input to output voltage difference (headroom)decides the lowest usable supply voltage Gm-driven to drive a certain load.For TPS51200,a minimum of 300mV (VLDOIN MIIN –VO MAX )is needed in order to support a Gm driven sourcing current of 2A based on a design of V IN =3.3V and C OUT =3×10μF.Because the TPS51200is essentially a Gm driven LDO,its impedance characteristics are both a function of the 1/Gm and R DS(on)of the sourcing MOSFET (see Figure 8).The current inflection point of the design is between 2A and 3A.When I SRC is less than the inflection LDO is considered to be operating in the Gm region;when I SRC is greater than the inflection point but less than the overcurrent limit point,the LDO is operating in the R DS(on)region.The maximum sourcing R DS(on)is 0.144?with V IN =3.0V and T J =125°C. https://www.wendangku.net/doc/eb13028793.html, I SRC -Source Current - A UDG-08026 V –O u t p u t V o l t a g e –V TPS51200SLUS812–FEBRUARY 2008 Figure 8.TPS51200Impedance Characteristics https://www.wendangku.net/doc/eb13028793.html, THERMAL DESIGN ()DISS _SRC VLDOIN VO O _SRC P V -V x I =(2)DISS _SNK VO O _SNK P V I =′(3)()J(max)A(max)PKG JA T T P ′= q (4) mm Thermal Die Pad, mm x 1.74mm UDG-08018TPS51200SLUS812–FEBRUARY 2008Because the TPS51200is a linear regulator,the VO current flows in both source and sink directions,thereby dissipating power from the device.When the device is sourcing current,the voltage difference between VLDOIN and VO times IO (I IO )current becomes the power dissipation as shown in Equation 2. In this case,if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage,overall power loss can be reduced.For the sink phase,VO voltage is applied across the internal LDO regulator,and the power dissipation,P DISS_SNK can be calculated by Equation 3. Because the device does not sink and source current at the same time and the IO current may vary rapidly with time,the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system.Another source of power consumption is the current used for the internal current control circuitry from the VIN supply and the VLDOIN supply.This can be estimated as 5mW or less during normal operatiing conditions.This power must be effectively dissipated from the package. Maximum power dissipation allowed by the package is calculated by Equation 4. P PKG =[T J(MAX)–T A(MAX)]/θJA where ? T J(MAX)is +125°C ? T A(MAX)is the maximum ambient temperature in the system ?θJA is the thermal resistance from junction to ambient The thermal performance of an LDO is greatly depends on the printed circuit board (PCB)layout.The TPS51200is housed in a thermally-enhanced PowerPAD?package that has an exposed die pad underneath the body.For improved thermal performance,this die pad must be attached to ground via thermal land on the PCB.This ground trace acts as a both a heatsink and heatspreader.The typical thermal resistance,θJA ,52.06°C/W,is achieved based on a land pattern of 3mm ×1.9mm with four vias (0.33-mm via diameter,the standard thermal via size)without air flow (see Figure 9). Figure 9.Recommend Land Pad Pattern for TPS51200 To further improve the thermal performance of this device,using a larger than recommended thermal land as well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad.The typical thermal resistance from junction to thermal pad,θJP ,is 10.24°C/W (based on the recommend land pad and four standard thermal vias). https://www.wendangku.net/doc/eb13028793.html, LAYOUT CONSIDERATIONS TPS51200 SLUS812–FEBRUARY2008 For further information regarding the PowerPAD?package and the recommended board layout,refer to the PowerPAD?package application note(SLMA002).This document is available at https://www.wendangku.net/doc/eb13028793.html,. Consider the following points before starting the TPS51200layout design. ?The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide connections. ?The output capacitor for VO should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL trace inductance. ?VOSNS should be connected to the positive node of VO output capacitor(s)as a separate trace from the high current power line.This configuration is strongly recommended to avoid additional ESR and/or ESL.If sensing the voltage at the point of the load is required,it is recommended to attach the output capacitor(s)at that point.Also,it is recommended to minimize any additional ESR and/or ESL of ground trace between the GND pin and the output capacitor(s). ?Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitor(s)is larger than2m?.?REFIN can be connected separately from VLDOIN.Remember that this sensing potential is the reference voltage of REFOUT.Avoid any noise-generating lines. ?The negative node of the VO output capacitor(s)and the REFOUT capacitor should be tied together by avoiding common impedance to the high current path of the VO source/sink current. ?The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple vias connecting to the internal system ground planes(for better result,use at least two internal ground planes). Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane. Also,place bulk caps close to the DIMM load point,route the VOSNS to the DIMM load sense point. ?In order to effectively remove heat from the package,properly prepare the thermal land.Apply solder directly to the package’s thermal pad.The wide traces of the component and the side copper connected to the thermal land pad help to dissipate heat.Numerous vias0,33mm in diameter connected from the thermal land to the internal/solder side ground plane(s)should also be used to help dissipation. ?Please consult the TPS51200-EVM User's Guide(SLUUxxx)for detailed layout recommendations. https://www.wendangku.net/doc/eb13028793.html, TYPICAL CHARACTERISTICS -31.18-1-20123I OUT –Output Current –A 1.201.261.22 1.241.30 1.28V O U T –O u t p u t V o l t a g e –V 890870880920900910940930-3-1-201 23I OUT –Output Current –A V O U T –O u t p u t V o l t a g e –m V -3-1-20123I OUT –Output Current –A 730 700 720 760 740 750 790 770 780 V O U T –O u t p u t V o l t a g e –m V 710 590550 570630610670650V O U T –O u t p u t V o l t a g e –m V -3-1-201 23I OUT –Output Current –A TPS51200SLUS812–FEBRUARY 2008For Figure 10through Figure 24,3×10-μF MLCCs (0805)are used on the output. OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT Figure 10. Figure 11.OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT Figure 12.Figure 13. https://www.wendangku.net/doc/eb13028793.html, 1.00 0.90 0.95 1.151.05 1.101.30 1.201.25V O U T –O u t p u t V o l t a g e –V -3-1-201 23I OUT –Output Current –A -3-1-20123 I OUT –Output Current –A 0.800.700.750.900.850.95V O U T –O u t p u t V o l t a g e –V 1.00-3650-1-20123I OUT –Output Current –A 750700800 V O U T –O u t p u t V o l t a g e –V 500550600650750700 V O U T –O u t p u t V o l t a g e –m V -3-1-201 23I OUT –Output Current –A TPS51200 SLUS812–FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10through Figure 24,3×10-μF MLCCs (0805)are used on the output. OUTPUT VOLTAGE OUTPUT CURRENT vs vs OUTPUT CURRENT OUTPUT VOLTAGE Figure 14. Figure 15.OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT Figure 16.Figure 17. https://www.wendangku.net/doc/eb13028793.html, 1.249 1.247 I REFOUT –Output Current –mA 1.248 1.252 1.250 1.251 1.255 1.253 1.254 V R E F O U T –O u t p u t V o l t a g e –V -15-5 -10051015I REFOUT –Output Current –mA 899897898902900901905903904V R E F O U T –O u t p u t V o l t a g e –m V -15599 598 -5-10051015I REFOUT –Output Current –mA 598602600601605603604V R E F O U T –O u t p u t V o l t a g e –m V -15749747 -5-1005I REFOUT –Output Current –mA 748 752750751755 753754 V R E F O U T –O u t p u t V o l t a g e –m V TPS51200 SLUS812–FEBRUARY 2008TYPICAL CHARACTERISTICS (continued) For Figure 10through Figure 24,3×10-μF MLCCs (0805)are used on the output. REFOUT VOLTAGE REFOUT VOLTAGE vs vs REFOUT CURRENT REFOUT CURRENT Figure 18. Figure 19.REFOUT VOLTAGE REFOUT VOLTAGE vs vs REFOUT CURRENT REFOUT CURRENT Figure 20.Figure 21.