M25P64-VME6中文资料
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PRELIMINARY DATA
February 2005This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M25P64
64 Mbit, Low Voltage, Serial Flash Memory
With 50MHz SPI Bus Interface
FEATURES SUMMARY
■64Mbit of Flash Memory
■Page Program (up to 256 Bytes) in 1.4ms (typical)
■Sector Erase (512Kbit)■Bulk Erase (64Mbit)
■ 2.7 to 3.6V Single Supply Voltage ■SPI Bus Compatible Serial Interface ■50MHz Clock Rate (maximum)■
Electronic Signatures
–JEDEC Standard Two-Byte Signature
(2017h)
–RES Instruction, One-Byte, Signature
(16h), for backward compatibility
■More than 100000 Erase/Program Cycles per Sector
■
More than 20-Year Data Retention
M25P64
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 1.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 3.VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Figure 4.SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Serial Clock (C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 5.Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 6.SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATING FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Active Power and Standby Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 2.Protected Area Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 7.Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8.Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 3.Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 4.Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Figure 9.Write Enable (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
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M25P64
Figure 10.Write Disable (WRDI) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 5.Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Figure 11.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . .16 Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 6.Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Figure 12.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . .17 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 7.Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Figure 13.Write Status Register (WRSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .19 Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 14.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence. . . . . . . . . . .20 Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 15.Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence21 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 17.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 18.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Read Electronic Signature (RES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 19.Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence. . . . .25
POWER-UP AND POWER-DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 20.Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 8.Power-Up Timing and VWI Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 9.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 10.Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 11.AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 21.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 12.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 13.DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 14.AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 22.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 23.Write Protect Setup and Hold Timing during WRSR when SRWD=1. . . . . . . . . . . . . . .32 Figure 24.Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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M25P64
4/38Figure 25.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 26.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . .34 Table 15.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 27.SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . .35 Table 16.SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . .35
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Table 17.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 18.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
M25P64
SUMMARY DESCRIPTION
The M25P64 is a 64Mbit (8M x 8) Serial Flash Memory, with advanced write protection mecha-nisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 128 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 32768 pages, or 8388608 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.
Table 1. Signal Names
Note: 1.There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to V SS, and
must not be allowed to be connected to any other voltage
or signal line on the PCB.
2.See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
Note: 1.DU = Don’t Use
2.See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
C Serial
Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write
Protect
HOLD Hold
V CC Supply Voltage
V SS Ground
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SIGNAL DESCRIPTION
Serial Data Output (Q).This output signal is used to transfer data serially out of the device.Data is shifted out on the falling edge of Serial Clock (C).
Serial Data Input (D).This input signal is used to transfer data serially into the device. It receives in-structions, addresses, and the data to be pro-grammed. Values are latched on the rising edge of Serial Clock (C).
Serial Clock (C).This input signal provides the timing of the serial interface. Instructions, address-es, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S).When this input signal is High,the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Pro-gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the de-vice, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S)is required prior to the start of any instruction. Hold (HOLD).The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D)and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-lected, with Chip Select (S) driven Low.
Write Protect (W).The main purpose of this in-put signal is to freeze the size of the area of mem-ory that is protected against program or erase instructions (as specified by the values in the BP2,BP1 and BP0 bits of the Status Register).
M25P64 SPI MODES
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
–CPOL=0, CPHA=0
–CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6., is the clock polarity when the bus master is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
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OPERATING FEATURES
Page Programming
To program one data byte, two instructions are re-quired: Write Enable (WREN), which is one byte,and a Page Program (PP) sequence, which con-sists of four bytes plus data. This is followed by the internal Program cycle (of duration t PP ).
To spread this overhead, the Page Program (PP)instruction allows up to 256 bytes to be pro-grammed at a time (changing bits from 1 to 0), pro-vided that they lie in consecutive addresses on the same page of memory.Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration t SE or t BE ).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (t W , t PP , t SE , or t BE ). The Write In Progress (WIP) bit is provided in the Status Regis-ter so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is com-plete.
Active Power and Standby Power Modes When Chip Select (S) is Low, the device is select-ed, and in the Active Power mode.
When Chip Select (S) is High, the device is dese-lected, but could remain in the Active Power mode until all internal cycles have completed (Program,Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to I CC1.Status Register
The Status Register contains a number of status and control bits that can be read or set (as appro-priate) by specific instructions.
WIP bit.The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle.
WEL bit.The Write Enable Latch (WEL) bit indi-cates the status of the internal Write Enable Latch.BP2, BP1, BP0 bits.The Block Protect (BP2,BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions.
SRWD bit.The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0)become read-only bits.
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M25P64
Protection Modes
The environments where non-volatile memory de-vices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P64 features the following data protection mechanisms:■Power On Reset and an internal timer (t PUW )
can provide protection against inadvertant changes while the power supply is outside the operating specification.■Program, Erase and Write Status Register
instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.■All instructions that modify data must be
preceded by a Write Enable (WREN) instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state by the following events:–Power-up
–
Write Disable (WRDI) instruction completion
–Write Status Register (WRSR) instruction
completion
–Page Program (PP) instruction completion –Sector Erase (SE) instruction completion –Bulk Erase (BE) instruction completion ■
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM).
■
The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM).
Table 2. Protected Area Sizes
Note: 1.The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Status Register
Content Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0 0 0 none All sectors 1 (128 sectors: 0 to 127)0 0 1 Upper 64th (2 sectors: 126 and 127)Lower 63/64ths (126 sectors: 0 to 125)0 1 0 Upper 32nd (4 sectors: 124 to 127)Lower 31/32nds (124 sectors: 0 to 123)0 1 1 Upper sixteenth (8 sectors: 120 to 127)Lower 15/16ths (120 sectors: 0 to 119)1 0 0 Upper eighth (16 sectors: 112 to 127)Lower seven-eighths (112 sectors: 0 to 111)1 0 1 Upper quarter (32 sectors: 96 to 127)Lower three-quarters (96 sectors: 0 to 95)1 1 0 Upper half (64 sectors: 64 to 127)Lower half (64 sectors: 0 to 63)1
1
1
All sectors (128 sectors: 0 to 127)
none
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Hold Condition
The Hold (HOLD) signal is used to pause any se-rial communications with the device without reset-ting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Fig-ure 7.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts af-ter Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C)being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 7.).
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D)and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the mo-ment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart commu-nication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition.
M25P64 MEMORY ORGANIZATION
The memory is organized as:
■8388608 bytes (8 bits each)
■128 sectors (512Kbits, 65536 bytes each)■32768 pages (256 bytes each).Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
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M25P64
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Table 3. Memory Organization
Sector Address Range 1277F0000h 7FFFFFh 1267E0000h 7EFFFFh 1257D0000h 7DFFFFh 124
7C0000h
7CFFFFh 123 7B0000h 7BFFFFh 122 7A0000h 7AFFFFh 121 790000h 79FFFFh 120 780000h 78FFFFh 119770000h 77FFFFh 118760000h 76FFFFh 117750000h 75FFFFh 116
740000h
74FFFFh 115 730000h 73FFFFh 114 720000h 72FFFFh 113 710000h 71FFFFh 112 700000h 70FFFFh 1116F0000h 6FFFFFh 1106E0000h 6EFFFFh 1096D0000h 6DFFFFh 108
6C0000h
6CFFFFh 107 6B0000h 6BFFFFh 106 6A0000h 6AFFFFh 105 690000h 69FFFFh 104 680000h 68FFFFh 103670000h 67FFFFh 102660000h 66FFFFh 101650000h 65FFFFh 100
640000h
64FFFFh 99 630000h 63FFFFh 98 620000h 62FFFFh 97
610000h
61FFFFh 96 600000h 60FFFFh 955F0000h 5FFFFFh 945E0000h 5EFFFFh 93
5D0000h
5DFFFFh
92
5C0000h
5CFFFFh 91 5B0000h 5BFFFFh 90 5A0000h 5AFFFFh 89 590000h 59FFFFh 88 580000h 58FFFFh 87570000h 57FFFFh 86560000h 56FFFFh 85550000h 55FFFFh 84
540000h
54FFFFh 83 530000h 53FFFFh 82 520000h 52FFFFh 81 510000h 51FFFFh 80 500000h 50FFFFh 794F0000h 4FFFFFh 784E0000h 4EFFFFh 774D0000h 4DFFFFh 76
4C0000h
4CFFFFh 75 4B0000h 4BFFFFh 74 4A0000h 4AFFFFh 73 490000h 49FFFFh 72 480000h 48FFFFh 71470000h 47FFFFh 70460000h 46FFFFh 69450000h 45FFFFh 68
440000h
44FFFFh 67 430000h 43FFFFh 66 420000h 42FFFFh 65 410000h 41FFFFh 64 400000h 40FFFFh 633F0000h 3FFFFFh 623E0000h 3EFFFFh 613D0000h 3DFFFFh 60
3C0000h
3CFFFFh 59 3B0000h 3BFFFFh 58 3A0000h 3AFFFFh 57 390000h
39FFFFh
Sector Address Range
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M25P64
56 380000h 38FFFFh 55370000h 37FFFFh 54360000h 36FFFFh 53350000h 35FFFFh 52
340000h
34FFFFh 51 330000h 33FFFFh 50 320000h 32FFFFh 49 310000h 31FFFFh 48 300000h 30FFFFh 472F0000h 2FFFFFh 462E0000h 2EFFFFh 452D0000h 2DFFFFh 44
2C0000h
2CFFFFh 43 2B0000h 2BFFFFh 42 2A0000h 2AFFFFh 41 290000h 29FFFFh 40 280000h 28FFFFh 39270000h 27FFFFh 38260000h 26FFFFh 37250000h 25FFFFh 36
240000h
24FFFFh 35 230000h 23FFFFh 34 220000h 22FFFFh 33
210000h
21FFFFh 32 200000h 20FFFFh 311F0000h 1FFFFFh 301E0000h 1EFFFFh 291D0000h 1DFFFFh 28
1C0000h
1CFFFFh 27 1B0000h 1BFFFFh 26 1A0000h 1AFFFFh 25 190000h 19FFFFh 24 180000h 18FFFFh 23170000h 17FFFFh 22160000h 16FFFFh 21
150000h
15FFFFh
Sector Address Range 20
140000h
14FFFFh 19 130000h 13FFFFh 18 120000h 12FFFFh 17 110000h 11FFFFh 16 100000h 10FFFFh 150F0000h 0FFFFFh 140E0000h 0EFFFFh 130D0000h 0DFFFFh 12
0C0000h
0CFFFFh 11 0B0000h 0BFFFFh 10 0A0000h 0AFFFFh 9 090000h 09FFFFh 8 080000h 08FFFFh 7070000h 07FFFFh 6060000h 06FFFFh 5050000h 05FFFFh 4
040000h
04FFFFh 3 030000h 03FFFFh 2 020000h 02FFFFh 1 010000h 01FFFFh 0 000000h
00FFFFh
Sector Address Range
M25P64
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INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first.Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C).The instruction set is listed in Table 4..
Every instruction sequence starts with a one-byte instruction code. Depending on the instruction,this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR), Read Identification (RDID) or Read Electronic Signature (RES) in-struction, the shifted-in instruction sequence is fol-lowed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out se-quence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be driven High ex-actly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Se-lect (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cy-cle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction Code
Address
Bytes Dummy
Bytes
Data Bytes
WREN Write Enable 0000 011006h 0 0 0 WRDI Write Disable 0000 010004h 0 0 0 RDID Read Identification 1001 11119Fh 0 0 1 to 3RDSR Read Status Register 0000 010105h 0 0 1 to ∞WRSR Write Status Register 0000 000101h 0 0 1 READ
Read Data Bytes
0000 001103h 30 1 to ∞FAST_READ Read Data Bytes at Higher Speed
0000 10110Bh 31 1 to ∞PP Page Program 0000 001002h 30 1 to 256
SE
Sector Erase
1101 1000D8h 3
BE Bulk Erase 1100 0111C7h 0 0 0 RES
Read Electronic Signature
1010 1011
ABh
3
1 to ∞
M25P64
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 9.) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-or to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the in-struction code, and then driving Chip Select (S) High.
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 10.) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruc-tion code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions: –Power-up
–Write Disable (WRDI) instruction completion –Write Status Register (WRSR) instruction completion
–Page Program (PP) instruction completion –Sector Erase (SE) instruction completion
–Bulk Erase (BE) instruction completion
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M25P64
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Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, fol-lowed by two bytes of device identification. The manufacturer identification is assigned by JEDEC,and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (17h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the in-struction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit be-ing shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 11..The Read Identification (RDID) instruction is termi-nated by driving Chip Select (S) High at any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be se-lected, so that it can receive, decode and execute instructions.
Table 5. Read Identification (RDID) Data-Out Sequence
Manufacturer Identification
Device Identification
Memory Type
Memory Capacity
20h
20h
17h
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M25P64
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-lows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress,it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Reg-ister continuously, as shown in Figure 12..Table 6. Status Register Format
The status and control bits of the Status Register are as follows:
WIP bit.The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1,such a cycle is in progress, when reset to 0 no such cycle is in progress.
WEL bit.The Write Enable Latch (WEL) bit indi-cates the status of the internal Write Enable Latch.When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits.The Block Protect (BP2,BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) in-struction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant mem-ory area (as defined in Table 2.) becomes protect-ed against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1,BP0) bits can be written provided that the Hard-ware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. SRWD bit.The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1,BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.
b7 b0SRWD
0 BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits Write Enable Latch Bit
Write In Progress Bit
M25P64
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Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-lows new values to be written to the Status Regis-ter. Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex-ecuted. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 13..The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Reg-ister. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driv-en High, the self-timed Write Status Register cycle (whose duration is t W ) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-lows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as de-fined in Table 2.. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD)bit in accordance with the Write Protect (W) signal.The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not execut-ed once the Hardware Protected Mode (HPM) is entered.
Table 7. Protection Modes
Note: 1.As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2..
The protection features of the device are summa-rized in Table 7.
When the Status Register Write Disable (SRWD)bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) in-struction, regardless of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD)bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W):
–If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable (WREN) instruction.
–If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:
W Signal SRWD Bit Mode
Write Protection of the
Status Register
Memory Content
Protected Area 1
Unprotected Area 1
10Software Protected (SPM)Status Register is Writable (if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits can be changed Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
001
1
01
Hardware Protected (HPM)Status Register is
Hardware write protected The values in the SRWD, BP2, BP1 and BP0 bits
cannot be changed
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
M25P64
–by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low –or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
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M25P64
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Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the mem-ory contents, at that address, is shifted out on Se-rial Data Output (Q), each bit being shifted out, at a maximum frequency f R , during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14..The first byte addressed can be at any location.The address is automatically incremented to the
next higher address after each byte of data is shift-ed out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction.When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-nated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data out-put. Any Read Data Bytes (READ) instruction,while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Note: 1.Address bit A23 is Don’t Care.