ucc27524中文资料
ENA INA GND INB
ENB OUTA VDD OUTB
Dual Inverting Inputs
ENA INA GND INB
ENB OUTA VDD OUTB
Dual Non-Inverting Inputs
ENA INA GND INB
ENB OUTA VDD OUTB
One Inverting and One Non-Inverting Input
INA-
INB-GND OUTB
INA+
INB+OUTA VDD
Dual Input Configuration
UCC27523,UCC27524,UCC27525,UCC27526
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ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
双5A 高速低侧栅极驱动器
查询样品:UCC27523,UCC27524,UCC27525,UCC27526
特性
应用范围
?工业标准引脚分配
?开关模式电源
?两个独立的栅极驱动通道?直流(DC)到DC 转换器?5A 峰值驱动源电流和灌电流?电机控制，太阳能
?针对每个输出的独立使能功能
?
用于诸如GaN 等新上市的宽带隙电源器件的栅极驱动器
?与电源电压无关的TTL 和CMOS 兼容逻辑阀值?针对高抗扰度的滞后逻辑阀值
说明
?
输入和使能引脚电压电平不受VDD 引脚偏置电源UCC2752x 系列器件是双通道、高速、低侧栅极驱动电压限制
器，此器件能够有效地驱动MOSFET 和绝缘栅极型功? 4.5V 至18V 单电源范围
率管(IGBT)电源开关。使用能够从内部大大降低击穿?在VDD 欠压闭锁(UVLO)期间，输出保持低电电流的设计，UCC2752x 能够将高达5A 拉电流和5A 平，（以确保加电和断电时的无毛刺脉冲运行）灌电流的高峰值电流脉传送到电容负载，此器件还具有?快速传播延迟（典型值13ns ）
轨到轨驱动能力和典型值为13ns 的极小传播延迟。?快速上升和下降时间（典型值7ns 和6ns ）除此之外，此驱动器特有两个通道间相匹配的内部传播?两通道间典型值为1ns 的延迟匹配时间延迟，这一特性使得此驱动器非常适合于诸如同步整流?针对更高的驱动电流，两个输出可以并联器等对于双栅极驱动有严格计时要求的应用。这还使?当输入悬空时输出保持在低电平
得两个通道可以并连，以有效地增加电流驱动能力或者?
环氧树脂双列直插式(PDIP)-8，小外形尺寸集成电使用一个单一输入信号驱动两个并联在一起的开关。路(SOIC)-8，表面贴装小外形尺寸(MSOP)-8封装PowerPAD?和3mm x 3mm 超薄型小外形尺寸输入引脚阀值基于TTL 和CMOS 兼容低压逻辑，此逻(WSON)-8封装选项
辑是固定的并且与VDD 电源电压无关。高低阀值间?
-40°C 至+140°C 的运行温度范围
的宽滞后提供了出色的抗扰度。
产品矩阵
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED https://www.wendangku.net/doc/e417734711.html,
这些装置包含有限的内置ESD保护。
存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止MOS门极遭受静电损伤。
说明（继续）
UCC2752x系列产品提供了三个标准逻辑选项的组合-双路反相，双路非反相，一路反相和一路非反相驱动器。UCC27526特有一个双输入设计，此设计为每个通道提供了反相（IN-引脚）和非反相（IN+引脚）配置的灵活性。IN+或IN-引脚中的任何一个控制驱动器输出状态。未使用的输入引脚可被用于启用和禁用功能。出于安全的考虑，UCC2752x系列内所有器件输入引脚上的内部上拉和下拉电阻器可在输入引脚处于悬空条件下时确保输出保持低电平。为了能够更好地控制驱动器应用的运行，UCC27323，UCC27324和UCC27325均特有一个使能引脚（ENA和ENB）。针对高电平有效逻辑，这些引脚被内部上拉至VDD并可针对标准运行而保持断开。
UCC2752x系列器件采用SOIC-8(D)，带有外露焊垫的MSOP-8(DGN)和带有外露焊垫的3mm x3mm WSON-
8(DSD)封装。UCC27524也可采用PDIP-8(P)封装。对于UCC27526，只提供3mm x3mm WSON(DSD)封装。
ORDERING INFORMATION(1)(2)
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE,T A
SOIC8-Pin(D),MSOP8-pin(DGN),
UCC27523
WSON8-pin(DSD)
SOIC8-Pin(D),MSOP8-pin(DGN),
UCC27524
WSON8-pin(DSD),PDIP8-pin(P)-40°C to140°C
SOIC8-Pin(D),MSOP8-pin(DGN),
UCC27525
WSON8-pin(DSD)
UCC27526WSON8-pin(DSD)
(1)For the most current package and ordering information,see Package Option Addendum at the end of this document.
(2)All packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level1at255°C to260°C peak reflow temperature to be
compatible with either lead free or Sn/Pb soldering operations.DSD package is rated MSL level2.
TOPSIDE MARKING INFORMATION
PART NUMBER WITH PACKAGE DESIGNATOR TOP MARKINGS
UCC27524D27524
UCC27524DGN27524
UCC27524DSD SBA
UCC27524P27524
UCC27523D27523
UCC27523DGN27523
UCC27523DSD27523
UCC27525D27525
UCC27525DGN27525
UCC27525DSD27525
UCC27526DSD SCB
UCC27523,UCC27524,UCC27525,UCC27526 https://www.wendangku.net/doc/e417734711.html, ZHCS502F–NOVEMBER2011–REVISED MAY2013
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range(unless otherwise noted)
MIN MAX UNIT Supply voltage range VDD-0.3to20.0
DC-0.3to VDD+0.3V OUTA,OUTB voltage
Repetitive pulse<200ns(3)-2.0to VDD+0.3
Output continuous source/sink
I OUT_DC0.3
current
A Output pulsed source/sink current
I OUT_pulsed5
(0.5μs)
INA,INB,INA+,INA-,INB+,INB-,ENA,ENB voltage(4)-0.320
Human body model,HBM4000V ESD(5)
Charge device model,CDM1000
Operating virtual junction temperature,T J range-40150
Storage temperature range,T stg-65150
°C
Soldering,10sec.300
Lead temperature
Reflow260
(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)All voltages are with respect to GND unless otherwise noted.Currents are positive into,negative out of the specified terminal.See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3)Values are verified by characterization on bench.
(4)The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
(5)These devices are sensitive to electrostatic discharge;follow proper device handling procedures.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range(unless otherwise noted)
MIN TYP MAX UNIT Supply voltage range,VDD 4.51218V Operating junction temperature range-40140°C
Input voltage,INA,INB,INA+,INA-,INB+,INB-018V Enable voltage,ENA and ENB018
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED https://www.wendangku.net/doc/e417734711.html,
THERMAL INFORMATION
UCC27523,UCC27523,
UCC27524,UCC27524,
UCC27525UCC27525
THERMAL METRIC UNITS
SOIC(D)MSOP(DGN)(1)
8PINS8PINS
θJA Junction-to-ambient thermal resistance(2)130.971.8
θJCtop Junction-to-case(top)thermal resistance(3)80.065.6
θJB Junction-to-board thermal resistance(4)71.47.4
°C/W
ψJT Junction-to-top characterization parameter(5)21.97.4
ψJB Junction-to-board characterization parameter(6)70.931.5
θJCbot Junction-to-case(bottom)thermal resistance(7)n/a19.6
(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-
standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specific
JEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.
THERMAL INFORMATION
UCC27524UCC27523,
UCC27524,
UCC27525,
THERMAL METRIC UNITS
UCC27526
PDIP(P)WSON(DSD)(1)
8PINS8PINS
θJA Junction-to-ambient thermal resistance(2)62.146.7
θJCtop Junction-to-case(top)thermal resistance(3)52.746.7
θJB Junction-to-board thermal resistance(4)39.122.4
°C/W
ψJT Junction-to-top characterization parameter(5)31.00.7
ψJB Junction-to-board characterization parameter(6)39.122.6
θJCbot Junction-to-case(bottom)thermal resistance(7)n/a9.5
(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.
(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as
specified in JESD51-7,in an environment described in JESD51-2a.
(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-
standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.
(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature,as described in JESD51-8.
(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).
(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specific
JEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.
UCC27523,UCC27524,UCC27525,UCC27526 https://www.wendangku.net/doc/e417734711.html, ZHCS502F–NOVEMBER2011–REVISED MAY2013
ELECTRICAL CHARACTERISTICS
V DD=12V,T A=T J=-40°C to140°C,1-μF capacitor from V DD to GND.Currents are positive into,negative out of the specified terminal(unless otherwise noted,)
PARAMETER TEST CONDITION MIN TYP MAX UNITS Bias Currents
VDD=3.4V,
INA=VDD,55110175 Startup current,INB=VDD
I DD(off)(based on UCC27524InputμA
VDD=3.4V,
configuration)
INA=GND,2575145
INB=GND
Under Voltage LockOut(UVLO)
T J=25°C 3.91 4.20 4.50
V ON Supply start threshold
T J=-40°C to140°C 3.70 4.20 4.65
V Minimum operating voltage
V OFF 3.40 3.90 4.40 after supply start
VDD_H Supply voltage hysteresis0.200.300.50
Inputs(INA,INB,INA+,INA-,INB+,INB-),UCC2752X(D,DGN,DSD)
Output high for non-inverting input pins
V IN_H Input signal high threshold 1.9 2.1 2.3
Output low for inverting input pins
Output low for non-inverting input pins V
V IN_L Input signal low threshold 1.0 1.2 1.4
Output high for inverting input pins
V IN_HYS Input hysteresis0.700.90 1.10
INPUTS(INA,INB,INA+,INA-,INB+,INB-)UCC27524P ONLY
Output high for non-inverting input pins
V IN_H Input signal high threshold 2.3
Output low for inverting input pins
Output low for non-inverting input pins V
V IN_L Input signal low threshold 1.0
Output high for inverting input pins
V IN_HYS Input hysteresis0.9
Enable(ENA,ENB)UCC2752X(D,DGN,DSD)
V EN_H Enable signal high threshold Output enabled 1.9 2.1 2.3
V EN_L Enable signal low threshold Output disabled0.95 1.15 1.35V
V EN_HYS Enable hysteresis0.700.95 1.10
ENABLE(ENA,ENB)UCC27524P ONLY
V EN_H Enable signal high threshold Output enabled 2.3
V EN_L Enable signal low threshold Output disabled0.95V
V EN_HYS Enable hysteresis0.95
Outputs(OUTA,OUTB)
I SNK/SRC Sink/source peak current(1)C LOAD=0.22μF,F SW=1kHz±5A
V DD-V OH High output voltage I OUT=-10mA0.075
V
V OL Low output voltage I OUT=10mA0.01
R OH Output pullup resistance(2)I OUT=-10mA 2.557.5Ω
R OL Output pulldown resistance I OUT=10mA0.150.51ΩSwitching Time
(1)Ensured by design.
(2)R OH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC2752X output stage.
Enable
Output
Input
Enable
Output
Input
Enable
Output
Input
Enable
Output
Input
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
https://www.wendangku.net/doc/e417734711.html,
ELECTRICAL CHARACTERISTICS (continued)
V DD =12V,T A =T J =-40°C to 140°C,1-μF capacitor from V DD to GND.Currents are positive into,negative out of the specified terminal (unless otherwise noted,)
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNITS
t R Rise time
(3)
C LOA
D =1.8nF 718t F Fall time (3)
C LOA
D =1.8nF
610Delay matching between 2INA =INB,OUTA and OUTB at 50%transition t M 14channels
point
Minimum input pulse width ns
t PW 15
25that changes the output state Input to output propagation t D1,t D2C LOAD =1.8nF,5-V input pulse 61323delay (3)
EN to output propagation t D3,t D4C LOAD =1.8nF,5-V enable pulse
6
13
23
delay (3)
(3)
See timing diagrams in Figure 1,Figure 2,Figure 3and Figure 4
Timing Diagrams
Figure 1.Enable Function
Figure 2.Enable Function
(For Non-Inverting Input Driver Operation)(For Inverting Input Driver Operation)
Figure 3.Non-Inverting Input Driver Operation Figure 4.Inverting Input Driver Operation
UCC27523,4,5(D,DGN) &
INA INB ENB OUTA VDD OUTB
UCC27524P
UCC2752(3,4,5)DSD
ENA INA INB
ENB OUTA VDD OUTB
UCC27526 DSD INA-INB-OUTB
INA+INB+OUTA VDD
UCC27523,UCC27524,UCC27525,UCC27526
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ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
DEVICE INFORMATION
Figure 5.
TERMINAL FUNCTIONS (UCC27523/UCC27524/UCC27525)
TERMINAL
I/O FUNCTION
NUMBER
NAME 1
ENA
I
Enable input for Channel A:ENA biased LOW Disables Channel A output
regardless of INA state,ENA biased HIGH or floating Enables Channel A output,ENA allowed to float hence the pin-to-pin compatibility with UCC2732X N/C pin.2INA I Input to Channel A:Inverting Input in UCC27523,Non-Inverting Input in UCC27524,Inverting Input in UCC27525,OUTA held LOW if INA is unbiased or floating.3GND -Ground:All signals referenced to this pin.
4INB I Input to Channel B:Inverting Input in UCC27523,Non-Inverting Input in UCC27524,Non-Inverting Input in UCC27525,OUTB held LOW if INB is unbiased or floating.5OUTB O Output of Channel B 6VDD I Bias supply input 7OUTA O Output of Channel A
8
ENB
I
Enable input for Channel B:ENB biased LOW Disables Channel B output
regardless of INB state,ENB biased HIGH or floating Enables Channel B output,ENB allowed to float hence the pin-to-pin compatibility with UCC2732X N/C pin.
TERMINAL FUNCTIONS (UCC27526)
TERMINAL
I/O FUNCTION
NUMBER
NAME 1
INA-I
Inverting Input to Channel A:When Channel A is used in Non-Inverting
configuration,connect INA-to GND in order to Enable Channel A output,OUTA held LOW if INA-is unbiased or floating.
2INB-I
Inverting Input to Channel B:When Channel B is used in Non-Inverting
configuration,connect INB-to GND in order to Enable Channel B output,OUTB held LOW if INB-is unbiased or floating.3GND -Ground:All signals referenced to this pin.4OUTB I Output of Channel B 5VDD O Bias Supply Input 6OUTA I Output of Channel A
7
INB+
O
Non-Inverting Input to Channel B:When Channel B is used in Inverting
configuration,connect INB+to VDD in order to Enable Channel B output,OUTB held LOW if INB+is unbiased or floating.
8INA+I
Non-Inverting Input to Channel A:When Channel A is used in Inverting
configuration,connect INA+to VDD in order to Enable Channel A output,OUTA held LOW if INA+is unbiased or floating.
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED https://www.wendangku.net/doc/e417734711.html, Table1.Device Logic Table(UCC27523/UCC27524/UCC27525)
UCC27523UCC27524UCC27525 ENA ENB INA INB OUTA OUTB OUTA OUTB OUTA OUTB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L Any Any L L L L L L Any Any x(1)x(1)L L L L L L x(1)x(1)L L H H L L H L x(1)x(1)L H H L L H H H x(1)x(1)H L L H H L L L x(1)x(1)H H L L H H L H (1)Floating condition.
Table2.Device Logic Table(UCC27526)
INx+(x=A or B)INx-(x=A or B)OUTx(x=A or B)
L L L
L H L
H L H
H H L
x(1)Any L
Any x(1)L
(1)x=Floating condition.
ENA INA
GND INB ENB OUTA OUTB
ENA
INA GND
INB
ENB
OUTA
VDD
OUTB
UDG-11221
UCC27523,UCC27524,UCC27525,UCC27526
https://www.wendangku.net/doc/e417734711.html, ZHCS502F–NOVEMBER2011–REVISED MAY2013
Functional Block Diagrams
Figure6.UCC27523Block Diagram
Figure7.UCC27524Block Diagram
INA+
INA-GND INB+
OUTA
VDD
OUTB UDG-11222
INB-
ENA INA GND INB ENB OUTA VDD OUTB
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED https://www.wendangku.net/doc/e417734711.html,
Figure8.UCC27525Block Diagram
Figure9.UCC27526Block Diagram
0.51
1.5
22.5
Temperature (°C)
I n p u t T h r e s h o l d (V )
G004
0.51
1.5
2
2.5
Temperature (°C)
E n a b l e T h r e s h o l d (V )
G005
0.20.3
0.40.5
0.6
?500
50
100
150
Temperature (°C)
S u p p l y C u r r e n t (m A )
G012
33.5
4
4.5
5
?50
50
100150
Temperature (°C)
U V L O T h r e s h o l d (V )
G003
0.06
0.08
0.1
0.120.14?50
50
100
150
Temperature (°C)
S t a r t u p C u r r e n t (m A )
G001
2.53
3.5
4
?50
50
100
150
Temperature (°C)
O p
e r a t i n g S u p p l y C u r r e n t (m A )
G002
UCC27523,UCC27524,UCC27525,UCC27526
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ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
TYPICAL CHARACTERISTICS
START-UP CURRENT
OPERATING SUPPLY CURRENT
vs
vs
TEMPERATURE
Figure 10.
Figure 11.SUPPLY CURRENT
UVLO THRESHOLD
vs
vs
TEMPERATURE (Outputs in DC on/off condition)
TEMPERATURE
Figure 12.Figure 13.INPUT THRESHOLD
ENABLE THRESHOLD
vs
vs
TEMPERATURE
TEMPERATURE
Figure 14.Figure 15.
810
121416
18
Temperature (°C)
I n p u t t o O u t p u t P r o p a g a t i o n D e l a y (n s )
G010
810
12
14
16
18
Temperature (°C)
E N t o O u t p u t P r o p a g a t i o n D e l a y (n s )
G011
56
7
8
9
10Temperature (°C)
R i s e T i m e
(n s )
G008
56
7
8
9
Temperature (°C)
F a l l T i m e (n s )
G009
34567Temperature (°C)
O u t p u t P u l l ?u p R e s i s t a n c e (?)
G006
0.20.4
0.6
0.8
1
Temperature (°C)
O u t p u t P u l l ?d o w n R e s i s t a n c e (?)
G007
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
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TYPICAL CHARACTERISTICS (continued)
OUTPUT PULLUP RESISTANCE
OUTPUT PULLDOWN RESISTANCE
vs
vs
TEMPERATURE
TEMPERATURE
Figure 16.Figure 17.RISE TIME
FALL TIME
vs
vs
TEMPERATURE
TEMPERATURE
Figure 18.
Figure 19.
INPUT TO OUTPUT PROPAGATION DELAY
EN TO OUTPUT PROPAGATION DELAY
vs
vs
TEMPERATURE
TEMPERATURE
Figure 20.Figure 21.
0.51
1.5
2
2.5
Temperature (°C)
E n a b l e T h r e s h o l d (V )
G017
610
1418Supply Voltage (V)
R i s e T i m e (n s )
G015
4
6
8
10
Supply Voltage (V)
F a l l T i m e (n s )
G016
102030405060
Frequency (kHz)O p e r a t i n g S u p p l y C u r r e n t (m A )
G013
6
10
14
18
22
Supply Voltage (V)
P r o p a g a t i o n D e l a y s (n s )
G014
UCC27523,UCC27524,UCC27525,UCC27526
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ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
OPERATING SUPPLY CURRENT
PROPAGATION DELAYS
vs
vs
FREQUENCY
SUPPLY VOLTAGE
Figure 22.Figure 23.RISE TIME
FALL TIME
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Figure 24.
Figure 25.
ENABLE THRESHOLD
vs
TEMPERATURE
Figure 26.
UCC27523,UCC27524,UCC27525,UCC27526
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APPLICATION INFORMATION
High-current gate-driver devices are required in switching power applications for a variety of reasons.In order to effect fast switching of power devices and reduce associated switching-power losses,a powerful gate-driver device employs between the PWM output of control devices and the gates of the power semiconductor devices. Further,gate-driver devices are indispensable when having the PWM controller device directly drive the gates of the switching devices is sometimes not feasible.With advent of digital power,this situation is often encountered because the PWM signal from the digital controller is often a3.3-V logic signal which is not capable of effectively turning on a power switch.A level-shifting circuitry is needed to boost the3.3-V signal to the gate-drive voltage (such as12V)in order to fully turn on the power device and minimize conduction losses.Traditional buffer-drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement,being emitter-follower configurations, prove inadequate with digital power because they lack level-shifting capability.Gate-driver devices effectively combine both the level-shifting and buffer-drive functions.Gate-driver devices also find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch,driving gate-drive transformers and controlling floating power-device gates,reducing power dissipationx and thermal stress in controller devices by moving gate-charge power losses into the controller. Finally,emerging wide band-gap power-device technologies such as GaN based switches,which are capable of supporting very high switching frequency operation,are driving special requirements in terms of gate-drive capability.These requirements include operation at low VDD voltages(5V or lower),low propagation delays, tight delay matching and availability in compact,low-inductance packages with good thermal capability.In summary gate-driver devices are an extremely important component in switching power combining benefits of high-performance,low-cost,component-count,board-space reduction and simplified system design.
UDG-11225
Figure27.UCC2752x Typical Application Diagram(x=3,4Or5)
UCC27523,UCC27524,UCC27525,UCC27526
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ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
Figure 28.UCC27526Channel A in Inverting And Channel B In Non-Inverting Configuration,
(Enable Function Not Used)
Figure 29.UCC27526Channel A in Inverting And Channel B In Non-Inverting Configuration,
(Enable Function Implemented)
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED https://www.wendangku.net/doc/e417734711.html, Introduction
The UCC2752x family of products represent Texas Instruments’latest generation of dual-channel low-side high-speed gate-driver devices featuring5-A source/sink current capability,industry best-in-class switching characteristics and a host of other features listed in Table3all of which combine to ensure efficient,robust and reliable operation in high-frequency switching power circuits.
Table3.UCC2752x Family of Features and Benefits
FEATURE BENEFIT
Best-in-class13-ns(typ)propagation delay Extremely low-pulse transmission distortion
1-ns(typ)delay matching between channels Ease of paralleling outputs for higher(2times)current capability,
ease of driving parallel-power switches
Expanded VDD Operating range of4.5to18V Flexibility in system design
Expanded operating temperature range of–40°C to+140°C
(See ELECTRICAL CHARACTERISTICS table)
VDD UVLO Protection Outputs are held Low in UVLO condition,which ensures predictable,
glitch-free operation at power-up and power-down
Outputs held Low when input pins(INx)in floating condition Safety feature,especially useful in passing abnormal condition tests
during safety certification
Outputs enable when enable pins(ENx)in floating condition Pin-to-pin compatibility with UCC2732X family of products from TI,in
designs where pin#1,8are in floating condition
CMOS/TTL compatible input and enable threshold with wide Enhanced noise immunity,while retaining compatibility with hysteresis microcontroller logic level input signals(3.3V,5V)optimized for
digital power
Ability of input and enable pins to handle voltage levels not restricted System simplification,especially related to auxiliary bias supply
by VDD pin bias voltage architecture
UDG-11228
UCC27523,UCC27524,UCC27525,UCC27526
https://www.wendangku.net/doc/e417734711.html, ZHCS502F–NOVEMBER2011–REVISED MAY2013 VDD and Under Voltage Lockout
The UCC2752x devices have internal undervoltage-lockout(UVLO)protection feature on the VDD pin supply circuit blocks.When VDD is rising and the level is still below UVLO threshold,this circuit holds the output LOW, regardless of the status of the inputs.The UVLO is typically 4.25V with350-mV typical hysteresis.This hysteresis prevents chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase in I DD.The capability to operate at low voltage levels such as below5V,along with best in class switching characteristics,is especially suited for driving emerging GaN power semiconductor devices.
For example,at power up,the UCC2752x driver-device output remains LOW until the V DD voltage reaches the UVLO threshold if Enable pin is active or floating.The magnitude of the OUT signal rises with V DD until steady-state V DD is reached.The non-inverting operation in Figure30shows that the output remains LOW until the UVLO threshold is reached,and then the output is in-phase with the input.The inverting operation in Figure31 shows that the output remains LOW until the UVLO threshold is reached,and then the output is out-phase with the input.With UCC27526the output turns to high-state only if INX+is high and INX–is low after the UVLO threshold is reached.
Because the device draws current from the VDD pin to bias all internal circuits,for the best high-speed circuit performance,two VDD bypass capacitors are recommended to prevent noise problems.The use of surface mount components is highly recommended.A0.1-μF ceramic capacitor must be located as close as possible to the VDD to GND pins of the gate-driver device.In addition,a larger capacitor(such as1-μF)with relatively low ESR must be connected in parallel and close proximity,in order to help deliver the high-current peaks required by the load.The parallel combination of capacitors presents a low impedance characteristic for the expected current levels and switching frequencies in the application.
Figure30.Power-Up Non-Inverting Driver Figure31.Power-Up Inverting Driver
Operating Supply Current
The UCC2752x products feature very low quiescent I DD currents.The typical operating-supply current in UVLO state and fully-on state(under static and switching conditions)are summarized in Figure10,Figure11and Figure12.The I DD current when the device is fully on and outputs are in a static state(DC high or DC low,refer Figure11)represents lowest quiescent I DD current when all the internal logic circuits of the device are fully operational.The total supply current is the sum of the quiescent I DD current,the average I OUT current due to switching and finally any current related to pullup resistors on the enable pins and inverting input pins.For example when the inverting Input pins are pulled low additional current is drawn from VDD supply through the pullup resistors(refer to Figure6though Figure9).Knowing the operating frequency(f SW)and the MOSFET gate (Q G)charge at the drive voltage being used,the average I OUT current can be calculated as product of Q G and f SW.
A complete characterization of the I DD current as a function of switching frequency at different V DD bias voltages under1.8-nF switching load in both channels is provided in Figure22.The strikingly linear variation and close correlation with theoretical value of average I OUT indicates negligible shoot-through inside the gate-driver device attesting to its high-speed characteristics.
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F–NOVEMBER2011–REVISED https://www.wendangku.net/doc/e417734711.html, Input Stage
The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic that is independent of the VDD supply voltage.With typically high threshold=2.1V and typically low threshold= 1.2V,the logic level thresholds are conveniently driven with PWM control signals derived from3.3-V and5-V digital power-controller devices.Wider hysteresis(typ0.9V)offers enhanced noise immunity compared to traditional TTL logic implementations,where the hysteresis is typically less than0.5V.UCC2752x devices also feature tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature(refer to Figure14).The very low input capacitance on these pins reduces loading and increases switching speed.
The UCC2752x devices feature an important safety feature wherein,whenever any of the input pins is in a floating condition,the output of the respective channel is held in the low state.This is achieved using V DD pullup resistors on all the Inverting inputs(INA,INB in UCC27523,INA in UCC27525and INA-,INB-in UCC27526)or GND pulldown resistors on all the non-inverting input pins(INA,INB in UCC27524,INB in UCC27525and INA+, INB+in UCC27526),as shown in the device block diagrams.
While UCC27523/4/5devices feature one input pin per channel,the UCC27526features a dual input configuration with two input pins available to control the output state of each channel.With the UCC27526device the user has the flexibility to drive each channel using either a non-inverting input pin(INx+)or an inverting input pin(INx-).The state of the output pin is dependent on the bias on both the INx+and INx-pins(where x=A,B). Once an Input pin is chosen to drive a channel,the other input pin of that channel(the unused input pin)must be properly biased in order to enable the output of the channel.The unused input pin cannot remain in a floating condition because,as mentioned earlier,whenever any input pin is left in a floating condition,the output of that channel is disabled using the internal pullup or pulldown resistors for safety purposes.Alternatively,the unused input pin is used effectively to implement an enable/disable function,as explained below.
?In order to drive the channel x(x=A or B)in a non-inverting configuration,apply the PWM control input signal to INx+pin.In this case,the unused input pin,INx-,must be biased low(eg.tied to GND)in order to enable the output of this channel.
–Alternately,the INx-pin can be used to implement the enable/disable function using an external logic signal.OUTx is disabled when INx-is biased High and OUTx is enabled when INX-is biased low.
?In order to drive the channel x(x=A or B)in an Inverting configuration,apply the PWM control input signal to INX-pin.In this case,the unused input pin,INX+,must be biased high(eg.tied to VDD)in order to enable the output of the channel.
–Alternately,the INX+pin can be used to implement the enable/disable function using an external logic signal.OUTX is disabled when INX+is biased low and OUTX is enabled when INX+is biased high.?Finally,it is worth noting that the UCC27526output pin can be driven into high state only when INx+pin is biased high and INx-input is biased low.
Refer to the input/output logic truth table and typical application diagram,(Figure28and Figure29),for additional clarification.
The input stage of each driver is driven by a signal with a short rise or fall time.This condition is satisfied in typical power supply applications,where the input signals are provided by a PWM controller or logic gates with fast transition times(<200ns)with a slow changing input voltage,the output of the driver may switch repeatedly at a high frequency.While the wide hysteresis offered in UCC2752x definitely alleviates this concern over most other TTL input threshold devices,extra care is necessary in these implementations.If limiting the rise or fall times to the power device is the primary goal,then an external resistance is highly recommended between the output of the driver and the power device.This external resistor has the additional benefit of reducing part of the gate-charge related power dissipation in the gate driver device package and transferring it into the external resistor itself.
UCC27523,UCC27524,UCC27525,UCC27526 https://www.wendangku.net/doc/e417734711.html, ZHCS502F–NOVEMBER2011–REVISED MAY2013
Enable Function
The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative current circulation and to improve light-load efficiency.
UCC27523/4/5devices are provided with independent enable pins ENx for exclusive control of each driver-channel operation.The enable pins are based on a non-inverting configuration(active-high operation).Thus when ENx pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are disabled.Like the input pins,the enable pins are also based on a TTL and CMOS compatible input-threshold logic that is independent of the supply voltage and are effectively controlled using logic signals from3.3-V and5-V microcontrollers.The UCC2752X devices also feature tight control of the Enable-function threshold-voltage levels which eases system design considerations and ensures stable operation across temperature(refer to Figure15).The ENx pins are internally pulled up to VDD using pullup resistors as a result of which the outputs of the device are enabled in the default state.Hence the ENx pins are left floating or Not Connected(N/C)for standard operation,where the enable feature is not needed.Essentially,this floating allows the UCC27523/4/5 devices to be pin-to-pin compatible with TI’s previous generation drivers UCC27323/4/5respectively,where pins #1,8are N/C pins.If the channel A and Channel B inputs and outputs are connected in parallel to increase the driver current capacity,ENA and ENB are connected and driven together.
The UCC27526device does not feature dedicated enable pins.However,as mentioned earlier,an enable/disable function is easily implemented in UCC27526using the unused input pin.When INx+is pulled-down to GND or INx-is pulled-down to VDD,the output is disabled.Thus INx+pin is used like an enable pin that is based on active high logic,while INx-is used like an enable pin that is based on active low logic.Note that while the ENA,ENB pins in UCC27523/4/5are allowed to be in floating condition during standard operation and the outputs will be enabled,the INx+,INx-pins in UCC27526are not allowed to be floating because this will disable the outputs.
OUT
UCC27523,UCC27524,UCC27525,UCC27526
ZHCS502F –NOVEMBER 2011–REVISED MAY 2013
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Output Stage
The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon transition (when the power switch drain or collector voltage experiences dV/dt).The output stage pullup structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel.The function of the N-Channel MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon.This is accomplished by briefly turning-on the N-Channel MOSFET during a narrow instant when the output is changing state from Low to High.
Figure 32.UCC2752X Gate Driver Output Structure
The R OH parameter (see ELECTRICAL CHARACTERISTICS )is a DC measurement and it is representative of the on-resistance of the P-Channel device only.This is because the N-Channel device is held in the off state in DC condition and is turned-on only for a narrow instant when output changes state from low to high.Note that effective resistance of UCC2752x pullup stage during the turnon instant is much lower than what is represented by R OH parameter.
The pulldown structure in UCC2752x is simply composed of a N-Channel MOSFET.The R OL parameter (see ELECTRICAL CHARACTERISTICS ),which is also a DC measurement,is representative of the impedance of the pulldown stage in the device.In UCC2752x,the effective resistance of the hybrid pullup structure during turnon is estimated to be approximately 1.5×R OL ,estimated based on design considerations.
Each output stage in UCC2752x is capable of supplying 5-A peak source and 5-A peak sink current pulses.The output voltage swings between VDD and GND providing rail-to-rail operation,thanks to the MOS-output stage which delivers very low drop-out.The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots which means that in many cases,external Schottky-diode clamps may be eliminated.The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.
The UCC2752x devices are particularly suited for dual-polarity,symmetrical drive-gate transformer applications where the primary winding of transformer driven by OUTA and OUTB,with inputs INA and INB being driven complementary to each other.This situation is due to the extremely low drop-out offered by the MOS output stage of these devices,both during high (V OH )and low (V OL )states along with the low impedance of the driver output stage,all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance.The low propagation delays also ensure accurate reset for high-frequency applications.
For applications that have zero voltage switching during power MOSFET turnon or turnoff interval,the driver supplies high-peak current for fast switching even though the miller plateau is not present.This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before power MOSFET is switched on.