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TMS32C6415CZLZA6E3中文资料

? 4000, 4800, 5760 MIPS

? Fully Software-Compatible With C62x ?? C6414/15/16 Devices Pin-Compatible D

VelociTI.2? Extensions to VelociTI ?Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x ? DSP Core

? Eight Highly Independent Functional Units With VelociTI.2? Extensions:

? Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle ? Two Multipliers Support Four 16 x 16-Bit Multiplies

(32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies

(16-Bit Results) per Clock Cycle ? Non-Aligned Load-Store Architecture ? 64 32-Bit General-Purpose Registers ? Instruction Packing Reduces Code Size ? All Instructions Conditional D

Instruction Set Features

? Byte-Addressable (8-/16-/32-/64-Bit Data)? 8-Bit Overflow Protection ? Bit-Field Extract, Set, Clear

? Normalization, Saturation, Bit-Counting ? VelociTI.2? Increased Orthogonality

D Viterbi Decoder Coprocessor (VCP) [C6416]? Supports Over 600 7.95-Kbps AMR ? Programmable Code Parameters

Turbo Decoder Coprocessor (TCP) [C6416]? Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations)? Programmable Turbo Code and Decoding Parameters D

L1/L2 Memory Architecture

? 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)

? 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)

? 1280M-Byte Total Addressable External Memory Space

D Enhanced Direct-Memory-Access (EDMA)Controller (64 Independent Channels)D Host-Port Interface (HPI)

? User-Configurable Bus Width (32-/16-Bit)D

32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2[C6415/C6416 ]

? Three PCI Bus Address Registers:

Prefetchable Memory

Non-Prefetchable Memory I/O ? Four-Wire Serial EEPROM Interface ? PCI Interrupt Request Under DSP Program Control

? DSP Interrupt Via PCI I/O Cycle

Three Multichannel Buffered Serial Ports ? Direct I/F to T1/E1, MVIP , SCSA Framers ? Up to 256 Channels Each

? ST-Bus-Switching-, AC97-Compatible ? Serial Peripheral Interface (SPI)Compatible (Motorola ?)

D Three 32-Bit General-Purpose Timers D

Universal Test and Operations PHY

Interface for ATM (UTOPIA) [C6415/C6416]? UTOPIA Level 2 Slave ATM Controller ? 8-Bit Transmit and Receive Operations up to 50 MHz per Direction

? User-Defined Cell Format up to 64 Bytes D Sixteen General-Purpose I/O (GPIO) Pins D Flexible PLL Clock Generator D IEEE-1149.1 (JTAG ?)

Boundary-Scan-Compatible

D 532-Pin Ball Grid Array (BGA) Package (GLZ, ZLZ and CLZ Suffixes), 0.8-mm Ball Pitch

D 0.13-μm/6-Level C u Metal Process (CMOS)D 3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz) D

3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication d ate.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.Motorola is a trademark of Motorola, Inc.

?IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS146M device-specific data sheet to make it an SPRS146N revision.

Scope: Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416 devices, have been incorporated.

PAGE(S)

NO.ADDITIONS/CHANGES/DELETIONS

Global:

Added “CLZ” (532-pin plastic BGA, Pb?free bump and Pb?free soldered balls) mechanical package information

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

GLZ, ZLZ and CLZ BGA packages (bottom view)

GLZ, ZLZ and CLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGE

(BOTTOM VIEW )?

13456789

1011121314151617181920212223242526

C D E F G H J K L M N P R T U V W Y AA AB AC AD

AE AF ?

The ZLZ mechanical package designator represents the version of the GLZ package with lead-free soldered balls. For more detailed information, see the Mechanical Data section of this document.

?The CLZ mechanical package designator represents the version of the GLZ package with lead-free bump and lead ?free soldered balls.For more detailed information, see the Mechanical Data section of this document.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

description

The TMS320C64x? DSPs (including the TMS320C6414, TMS320C6415, and TMS320C6416 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000? DSP platform. The TMS320C64x?(C64x??) device is based on the second-generation high-performance, advanced VelociTI?very-long-instruction-word (VLIW) architecture (VelociTI.2?) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x? is a code-compatible member of the C6000? DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x? DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2? extensions. The VelociTI.2? extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI? architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000? DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 600 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to forty-three 384-Kbps or seven 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal T est and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only];

a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces

(64-bit EMIFA and 16-bit EMIFB?), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows? debugger interface for visibility into source code execution.

TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.

Windows is a registered trademark of the Microsoft Corporation.

All trademarks are the property of their respective owners.

?Throughout the remainder of this document, the TMS320C6414, TMS320C6415, and TMS320C6416 shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416.?These C64x? devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 device characteristics

Table 1 provides an overview of the C6414, C6415, and C6416 DSPs. The table shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.

Table 1. Characteristics of the C6414, C6415, and C6416 Processors

HARDWARE FEATURES C6414, C6415, AND C6416

EMIFA (64-bit bus width)

(default clock source = AECLKIN)1 Peripherals EMIFB (16-bit bus width)

(default clock source = BECLKIN)1 Not all peripherals pins EDMA (64 independent channels)1

are available at the

HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32) same time. (For more

PCI (32-bit) [DeviceID Register value 0xA106] 1 [C6415/C6416 only] details, see the Device

Configuration section.) Peripheral performance McBSPs (default internal clock source =

CPU/4 clock frequency)3 UTOPIA (8-bit mode) 1 [C6415/C6416 only]

is dependent on

chip-level configuration.32-Bit Timers (default internal clock source =

CPU/8 clock frequency)3

General-Purpose Input/Output 0 (GP0)16

VCP 1 (C6416 only) Decoder Coprocessors

TCP 1 (C6416 only)

Size (Bytes)1056K

On-Chip Memory

Organization 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache

1024KB Unified Mapped RAM/Cache (L2)

CPU ID + CPU Rev ID Control Status Register (CSR.[31:16])0x0C01

Device_ID Silicon Revision Identification Register

(DEVICE_REV [19:16])

Address: 0x01B0 0200

DEVICE_REV[19:16]Silicon Revision

1111 1.03 or earlier

0001 1.03

0010 or 0000 1.1

0011 2.0

Frequency MHz500, 600, 720

Cycle Time ns

2 ns (C6414-5E0, C6415-5E0, C6416-5E0) and

(C6414A-5E0, C6415A-5E0, C6416A-5E0) [500-MHz CPU, 100-MHz EMIF]?

1.67 ns (C6414-6E3, C6415-6E3, C6416-6E3) and

(C6414A-6E3, C6415A-6E3, C6416A-6E3) [600-MHz CPU, 133-MHz EMIFA]?

1.39 ns (C6414-7E3, C6415-7E3, C6416-7E3)

[720-MHz CPU, 133-MHz EMIFA]?

Voltage Core (V)

1.2 V (-5E0)

1.25 V (A-5E0)

1.4 V (-6E3, A-6E3, -7E3) I/O (V) 3.3 V

PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12

BGA Package23 x 23 mm532-Pin BGA (GLZ, ZLZ and CLZ) Process Technologyμm0.13 μm

Product Status Product Preview (PP), Advance Information

(AI), Production Data (PD)PD

?On these C64x? devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data sheet.

?All devices are now at the Production Data (PD) stage of development.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

device compatibility

The C64x? generation of devices has a diverse and powerful set of peripherals. The common peripheral set and pin-compatibility that the C6414, C6415, and C6416 devices offer lead to easier system designs and faster time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414, C6415, and C6416 devices.

The C6414, C6415, and C6416 devices are pin-for-pin compatible, provided the following conditions are met:

D All devices are using the same peripherals.

The C6414 is pin-for-pin compatible with the C6415/C6416 when the PCI and UTOPIA peripherals on the C6415/C6416 are disabled.

The C6415 is pin-for-pin compatible with the C6416 when they are in the same peripheral selection mode.

[For more information on peripheral selection, see the Device Configurations section of this data sheet.]

D The BEA[9:7] pins are properly pulled up/down.

[For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of this data sheet.]

Table 2. Peripherals and Coprocessors Available on the C6414, C6415, and C6416 Devices??

PERIPHERALS/COPROCESSORS C6414C6415C6416

EMIFA (64-bit bus width)√√√

EMIFB (16-bit bus width)√√√

EDMA (64 independent channels)√√√

HPI (32- or 16-bit user selectable)√√√

PCI (32-bit) [Specification v2.2]—√√

McBSPs (McBSP0, McBSP1, McBSP2)√√√

UTOPIA (8-bit mode) [Specification v1.0]—√√

Timers (32-bit) [TIMER0, TIMER1, TIMER2]√√√

GPIOs (GP[15:0])√√√

VCP/TCP Coprocessors——√

?— denotes peripheral/coprocessor is not available on this device.

?Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.)

For more detailed information on the device compatibility and similarities/differences among the C6414, C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718).

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 functional block and CPU (DSP core) diagram

?VCP and TCP decoder coprocessors are applicable to the C6416 device only.

?For the C6415 and C6416 devices, the UTOPIA peripheral is muxed with McBSP1, and the PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

CPU (DSP core) description

The CPU fetches VelociTI? advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI? VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x? VelociTI.2? extensions add enhancements to the TMS320C62x? DSP VelociTI? architecture. These enhancements include:

D Register file enhancements

D Data path extensions

D Quad 8-bit and dual 16-bit extensions with data flow enhancements

D Additional functional unit hardware

D Increased orthogonality of the instruction set

D Additional instructions that reduce code size and increase register flexibility

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x? VelociTI? VLIW architecture, the C64x? register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle.

In addition to the C62x? DSP fixed-point instructions, the C64x? DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2? extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency.

Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction.

And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically “true”).

TMS320C62x is a trademark of Texas Instruments.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 CPU (DSP core) description (continued)

The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two

16 × 16-bit multiplies or four 8 ×8-bit multiplies per clock cycle. The .M unit can also perform 16 ×32-bit multiply

operations, dual 16 ×16-bit multiplies with add/subtract operations, and quad 8 ×8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x? DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x?/TMS320C67x? DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x?DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable.

For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)

TMS320C64x Technical Overview (literature number SPRU395)

How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718)

TMS320C67x is a trademark of Texas Instruments.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

CPU (DSP core) description (continued)

DA1 (Address)

ST1b (Store Data)ST2a (Store Data)Data Path A

DA2 (Address)LD2a (Load Data)Data Path B

ST2b (Store Data)

LD1b (Load Data)

ST1a (Store Data)

LD1a (Load Data)LD2b (Load Data)

NOTE A:Figure 1. TMS320C64x ? CPU (DSP Core) Data Paths

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 memory map summary

Table 3 shows the memory map address ranges of the TMS320C64x device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

memory map summary (continued)

Table 3. TMS320C64x Memory Map Summary

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES)HEX ADDRESS RANGE

Internal RAM (L2)1M0000 0000 – 000F FFFF Reserved23M0010 0000 – 017F FFFF External Memory Interface A (EMIFA) Registers256K0180 0000 – 0183 FFFF

L2 Registers256K0184 0000 – 0187 FFFF

HPI Registers256K0188 0000 – 018B FFFF McBSP 0 Registers256K018C 0000 – 018F FFFF McBSP 1 Registers256K0190 0000 – 0193 FFFF

Timer 0 Registers256K0194 0000 – 0197 FFFF

Timer 1 Registers256K0198 0000 – 019B FFFF Interrupt Selector Registers256K019C 0000 – 019F FFFF EDMA RAM and EDMA Registers256K01A0 0000 – 01A3 FFFF McBSP 2 Registers256K01A4 0000 – 01A7 FFFF EMIFB Registers256K01A8 0000 – 01AB FFFF

Timer 2 Registers256K01AC 0000 – 01AF FFFF

GPIO Registers256K01B0 0000 – 01B3 FFFF UTOPIA Registers (C6415 and C6416 only)?256K01B4 0000 – 01B7 FFFF

TCP/VCP Registers (C6416 only)?256K01B8 0000 – 01BB FFFF Reserved256K01BC 0000 – 01BF FFFF

PCI Registers (C6415 and C6416 only)?256K01C0 0000 – 01C3 FFFF Reserved4M – 256K01C4 0000 – 01FF FFFF QDMA Registers520200 0000 – 0200 0033 Reserved736M – 520200 0034 – 2FFF FFFF McBSP 0 Data64M3000 0000 – 33FF FFFF McBSP 1 Data64M3400 0000 – 37FF FFFF McBSP 2 Data64M3800 0000 – 3BFF FFFF UTOPIA Queues (C6415 and C6416 only)?64M3C00 0000 – 3FFF FFFF Reserved256M4000 0000 – 4FFF FFFF

TCP/VCP (C6416 only)?256M5000 0000 – 5FFF FFFF EMIFB CE064M6000 0000 – 63FF FFFF EMIFB CE164M6400 0000 – 67FF FFFF EMIFB CE264M6800 0000 – 6BFF FFFF EMIFB CE364M6C00 0000 – 6FFF FFFF Reserved256M7000 0000 – 7FFF FFFF EMIFA CE0256M8000 0000 – 8FFF FFFF EMIFA CE1256M9000 0000 – 9FFF FFFF EMIFA CE2256M A000 0000 – AFFF FFFF EMIFA CE3256M B000 0000 – BFFF FFFF Reserved1G C000 0000 – FFFF FFFF

?For the C6414 device, these memory address locations are reserved. The C6414 device does not support the UTOPIA and PCI peripherals.?Only the C6416 device supports the VCP/TCP Coprocessors. For the C6414 and C6415 devices, these memory address locations are reserved.

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 L2 architecture expanded

Figure 2 shows the detail of the L2 architecture on the TMS320C6414, TMS320C6415, and TMS320C6416 devices. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610).

0x0000 0000

011

010

001111

0x000C 0000

000

L2MODE L2 Memory Block Base Address

0x000F 0000

0x000E 0000 3

(

)

(

)

(

)

(

)

(

)

0x000F FFFF

0x000F 8000 Figure 2. TMS320C6414/C6415/C6416 L2 Architecture Memory Configuration

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

peripheral register descriptions

Table 4 through Table 23 identify the peripheral registers for the C6414, C6415, and C6416 devices by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).

Table 4. EMIFA Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0180 0000GBLCTL EMIFA global control

0180 0004CECTL1EMIFA CE1 space control

0180 0008CECTL0EMIFA CE0 space control

0180 000C?Reserved

0180 0010CECTL2EMIFA CE2 space control

0180 0014CECTL3EMIFA CE3 space control

0180 0018SDCTL EMIFA SDRAM control

0180 001C SDTIM EMIFA SDRAM refresh control

0180 0020SDEXT EMIFA SDRAM extension

0180 0024 ? 0180 003C?Reserved

0180 0040PDTCTL Peripheral device transfer (PDT) control

0180 0044CESEC1EMIFA CE1 space secondary control

0180 0048CESEC0EMIFA CE0 space secondary control

0180 004C?Reserved

0180 0050CESEC2EMIFA CE2 space secondary control

0180 0054CESEC3EMIFA CE3 space secondary control

0180 0058 ? 0183 FFFF–Reserved

Table 5. EMIFB Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01A8 0000GBLCTL EMIFB global control

01A8 0004CECTL1EMIFB CE1 space control

01A8 0008CECTL0EMIFB CE0 space control

01A8 000C?Reserved

01A8 0010CECTL2EMIFB CE2 space control

01A8 0014CECTL3EMIFB CE3 space control

01A8 0018SDCTL EMIFB SDRAM control

01A8 001C SDTIM EMIFB SDRAM refresh control

01A8 0020SDEXT EMIFB SDRAM extension

01A8 0024 ? 01A8 003C?Reserved

01A8 0040PDTCTL Peripheral device transfer (PDT) control

01A8 0044CESEC1EMIFB CE1 space secondary control

01A8 0048CESEC0EMIFB CE0 space secondary control

01A8 004C?Reserved

01A8 0050CESEC2EMIFB CE2 space secondary control

01A8 0054CESEC3EMIFB CE3 space secondary control

01A8 0058 ? 01AB FFFF–Reserved

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 peripheral register descriptions (continued)

Table 6. L2 Cache Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0184 0000CCFG Cache configuration register

0184 0004 ? 0184 0FFC?Reserved

0184 1000EDMAWEIGHT L2 EDMA access control register

0184 1004 ? 0184 1FFC?Reserved

0184 2000L2ALLOC0L2 allocation register 0

0184 2004L2ALLOC1L2 allocation register 1

0184 2008L2ALLOC2L2 allocation register 2

0184 200C L2ALLOC3L2 allocation register 3

0184 2010 ? 0184 3FFC?Reserved

0184 4000L2WBAR L2 writeback base address register

0184 4004L2WWC L2 writeback word count register

0184 4010L2WIBAR L2 writeback invalidate base address register

0184 4014L2WIWC L2 writeback invalidate word count register

0184 4018L2IBAR L2 invalidate base address register

0184 401C L2IWC L2 invalidate word count register

0184 4020L1PIBAR L1P invalidate base address register

0184 4024L1PIWC L1P invalidate word count register

0184 4030L1DWIBAR L1D writeback invalidate base address register

0184 4034L1DWIWC L1D writeback invalidate word count register

0184 4038 ? 0184 4044?Reserved

0184 4048L1DIBAR L1D invalidate base address register

0184 404C L1DIWC L1D invalidate word count register

0184 4050 ? 0184 4FFC?Reserved

0184 5000L2WB L2 writeback all register

0184 5004L2WBINV L2 writeback invalidate all register

0184 5008 ? 0184 7FFC?Reserved

0184 8000 ? 0184 817C MAR0 to

MAR95Reserved

0184 8180MAR96Controls EMIFB CE0 range 6000 0000 ? 60FF FFFF

0184 8184MAR97Controls EMIFB CE0 range 6100 0000 ? 61FF FFFF

0184 8188MAR98Controls EMIFB CE0 range 6200 0000 ? 62FF FFFF

0184 818C MAR99Controls EMIFB CE0 range 6300 0000 ? 63FF FFFF

0184 8190MAR100Controls EMIFB CE1 range 6400 0000 ? 64FF FFFF

0184 8194MAR101Controls EMIFB CE1 range 6500 0000 ? 65FF FFFF

0184 8198MAR102Controls EMIFB CE1 range 6600 0000 ? 66FF FFFF

0184 819C MAR103Controls EMIFB CE1 range 6700 0000 ? 67FF FFFF

0184 81A0MAR104Controls EMIFB CE2 range 6800 0000 ? 68FF FFFF

0184 81A4MAR105Controls EMIFB CE2 range 6900 0000 ? 69FF FFFF

0184 81A8MAR106Controls EMIFB CE2 range 6A00 0000 ? 6AFF FFFF

0184 81AC MAR107Controls EMIFB CE2 range 6B00 0000 ? 6BFF FFFF

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

peripheral register descriptions (continued)

Table 6. L2 Cache Registers (Continued)

ACRONYM

HEX ADDRESS RANGE COMMENTS 0184 81B0MAR108Controls EMIFB CE3 range 6C00 0000 ? 6CFF FFFF

0184 81B4MAR109Controls EMIFB CE3 range 6D00 0000 ? 6DFF FFFF

0184 81B8MAR110Controls EMIFB CE3 range 6E00 0000 ? 6EFF FFFF

0184 81BC MAR111Controls EMIFB CE3 range 6F00 0000 ? 6FFF FFFF

0184 81C0 ? 0184 81FC MAR112 to

MAR127Reserved

0184 8200MAR128Controls EMIFA CE0 range 8000 0000 ? 80FF FFFF

0184 8204MAR129Controls EMIFA CE0 range 8100 0000 ? 81FF FFFF

0184 8208MAR130Controls EMIFA CE0 range 8200 0000 ? 82FF FFFF

0184 820C MAR131Controls EMIFA CE0 range 8300 0000 ? 83FF FFFF

0184 8210MAR132Controls EMIFA CE0 range 8400 0000 ? 84FF FFFF

0184 8214MAR133Controls EMIFA CE0 range 8500 0000 ? 85FF FFFF

0184 8218MAR134Controls EMIFA CE0 range 8600 0000 ? 86FF FFFF

0184 821C MAR135Controls EMIFA CE0 range 8700 0000 ? 87FF FFFF

0184 8220MAR136Controls EMIFA CE0 range 8800 0000 ? 88FF FFFF

0184 8224MAR137Controls EMIFA CE0 range 8900 0000 ? 89FF FFFF

0184 8228MAR138Controls EMIFA CE0 range 8A00 0000 ? 8AFF FFFF

0184 822C MAR139Controls EMIFA CE0 range 8B00 0000 ? 8BFF FFFF

0184 8230MAR140Controls EMIFA CE0 range 8C00 0000 ? 8CFF FFFF

0184 8234MAR141Controls EMIFA CE0 range 8D00 0000 ? 8DFF FFFF

0184 8238MAR142Controls EMIFA CE0 range 8E00 0000 ? 8EFF FFFF

0184 823C MAR143Controls EMIFA CE0 range 8F00 0000 ? 8FFF FFFF

0184 8240MAR144Controls EMIFA CE1 range 9000 0000 ? 90FF FFFF

0184 8244MAR145Controls EMIFA CE1 range 9100 0000 ? 91FF FFFF

0184 8248MAR146Controls EMIFA CE1 range 9200 0000 ? 92FF FFFF

0184 824C MAR147Controls EMIFA CE1 range 9300 0000 ? 93FF FFFF

0184 8250MAR148Controls EMIFA CE1 range 9400 0000 ? 94FF FFFF

0184 8254MAR149Controls EMIFA CE1 range 9500 0000 ? 95FF FFFF

0184 8258MAR150Controls EMIFA CE1 range 9600 0000 ? 96FF FFFF

0184 825C MAR151Controls EMIFA CE1 range 9700 0000 ? 97FF FFFF

0184 8260MAR152Controls EMIFA CE1 range 9800 0000 ? 98FF FFFF

0184 8264MAR153Controls EMIFA CE1 range 9900 0000 ? 99FF FFFF

0184 8268MAR154Controls EMIFA CE1 range 9A00 0000 ? 9AFF FFFF

0184 826C MAR155Controls EMIFA CE1 range 9B00 0000 ? 9BFF FFFF

0184 8270MAR156Controls EMIFA CE1 range 9C00 0000 ? 9CFF FFFF

0184 8274MAR157Controls EMIFA CE1 range 9D00 0000 ? 9DFF FFFF

0184 8278MAR158Controls EMIFA CE1 range 9E00 0000 ? 9EFF FFFF

0184 827C MAR159Controls EMIFA CE1 range 9F00 0000 ? 9FFF FFFF

0184 8280MAR160Controls EMIFA CE2 range A000 0000 ? A0FF FFFF

0184 8284MAR161Controls EMIFA CE2 range A100 0000 ? A1FF FFFF

0184 8288MAR162Controls EMIFA CE2 range A200 0000 ? A2FF FFFF

0184 828C MAR163Controls EMIFA CE2 range A300 0000 ? A3FF FFFF

0184 8290MAR164Controls EMIFA CE2 range A400 0000 ? A4FF FFFF

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 peripheral register descriptions (continued)

Table 6. L2 Cache Registers (Continued)

ACRONYM

HEX ADDRESS RANGE COMMENTS

0184 8294MAR165Controls EMIFA CE2 range A500 0000 ? A5FF FFFF

0184 8298MAR166Controls EMIFA CE2 range A600 0000 ? A6FF FFFF

0184 829C MAR167Controls EMIFA CE2 range A700 0000 ? A7FF FFFF

0184 82A0MAR168Controls EMIFA CE2 range A800 0000 ? A8FF FFFF

0184 82A4MAR169Controls EMIFA CE2 range A900 0000 ? A9FF FFFF

0184 82A8MAR170Controls EMIFA CE2 range AA00 0000 ? AAFF FFFF

0184 82AC MAR171Controls EMIFA CE2 range AB00 0000 ? ABFF FFFF

0184 82B0MAR172Controls EMIFA CE2 range AC00 0000 ? ACFF FFFF

0184 82B4MAR173Controls EMIFA CE2 range AD00 0000 ? ADFF FFFF

0184 82B8MAR174Controls EMIFA CE2 range AE00 0000 ? AEFF FFFF

0184 82BC MAR175Controls EMIFA CE2 range AF00 0000 ? AFFF FFFF

0184 82C0MAR176Controls EMIFA CE3 range B000 0000 ? B0FF FFFF

0184 82C4MAR177Controls EMIFA CE3 range B100 0000 ? B1FF FFFF

0184 82C8MAR178Controls EMIFA CE3 range B200 0000 ? B2FF FFFF

0184 82CC MAR179Controls EMIFA CE3 range B300 0000 ? B3FF FFFF

0184 82D0MAR180Controls EMIFA CE3 range B400 0000 ? B4FF FFFF

0184 82D4MAR181Controls EMIFA CE3 range B500 0000 ? B5FF FFFF

0184 82D8MAR182Controls EMIFA CE3 range B600 0000 ? B6FF FFFF

0184 82DC MAR183Controls EMIFA CE3 range B700 0000 ? B7FF FFFF

0184 82E0MAR184Controls EMIFA CE3 range B800 0000 ? B8FF FFFF

0184 82E4MAR185Controls EMIFA CE3 range B900 0000 ? B9FF FFFF

0184 82E8MAR186Controls EMIFA CE3 range BA00 0000 ? BAFF FFFF

0184 82EC MAR187Controls EMIFA CE3 range BB00 0000 ? BBFF FFFF

0184 82F0MAR188Controls EMIFA CE3 range BC00 0000 ? BCFF FFFF

0184 82F4MAR189Controls EMIFA CE3 range BD00 0000 ? BDFF FFFF

0184 82F8MAR190Controls EMIFA CE3 range BE00 0000 ? BEFF FFFF

0184 82FC MAR191Controls EMIFA CE3 range BF00 0000 ? BFFF FFFF

0184 8300 ? 0184 83FC MAR192 to

MAR255Reserved

0184 8400 ? 0187 FFFF?Reserved

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

peripheral register descriptions (continued)

Table 7. EDMA Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME 01A0 FF9C EPRH Event polarity high register

01A0 FFA4CIPRH Channel interrupt pending high register

01A0 FFA8CIERH Channel interrupt enable high register

01A0 FFAC CCERH Channel chain enable high register

01A0 FFB0ERH Event high register

01A0 FFB4EERH Event enable high register

01A0 FFB8ECRH Event clear high register

01A0 FFBC ESRH Event set high register

01A0 FFC0PQAR0Priority queue allocation register 0

01A0 FFC4PQAR1Priority queue allocation register 1

01A0 FFC8PQAR2Priority queue allocation register 2

01A0 FFCC PQAR3Priority queue allocation register 3

01A0 FFDC EPRL Event polarity low register

01A0 FFE0PQSR Priority queue status register

01A0 FFE4CIPRL Channel interrupt pending low register

01A0 FFE8CIERL Channel interrupt enable low register

01A0 FFEC CCERL Channel chain enable low register

01A0 FFF0ERL Event low register

01A0 FFF4EERL Event enable low register

01A0 FFF8ECRL Event clear low register

01A0 FFFC ESRL Event set low register 01A1 0000 ? 01A3 FFFF–Reserved

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005 peripheral register descriptions (continued)

Table 8. EDMA Parameter RAM?

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 01A0 0000 ? 01A0 0017?Parameters for Event 0 (6 words)

01A0 0018 ? 01A0 002F?Parameters for Event 1 (6 words)

01A0 0030 ? 01A0 0047?Parameters for Event 2 (6 words)

01A0 0048 ? 01A0 005F?Parameters for Event 3 (6 words)

01A0 0060 ? 01A0 0077?Parameters for Event 4 (6 words)

01A0 0078 ? 01A0 008F?Parameters for Event 5 (6 words)

01A0 0090 ? 01A0 00A7?Parameters for Event 6 (6 words)

01A0 00A8 ? 01A0 00BF?Parameters for Event 7 (6 words)

01A0 00C0 ? 01A0 00D7?Parameters for Event 8 (6 words)

01A0 00D8 ? 01A0 00EF?Parameters for Event 9 (6 words)

01A0 00F0 ? 01A0 00107?Parameters for Event 10 (6 words)

01A0 0108 ? 01A0 011F?Parameters for Event 11 (6 words)

01A0 0120 ? 01A0 0137?Parameters for Event 12 (6 words)

01A0 0138 ? 01A0 014F?Parameters for Event 13 (6 words)

01A0 0150 ? 01A0 0167?Parameters for Event 14 (6 words)

01A0 0168 ? 01A0 017F?Parameters for Event 15 (6 words)

01A0 0150 ? 01A0 0167?Parameters for Event 16 (6 words)

01A0 0168 ? 01A0 017F?Parameters for Event 17 (6 words)

......

01A0 05D0 ? 01A0 05E7?Parameters for Event 62 (6 words)

01A0 05E8 ? 01A0 05FF?Parameters for Event 63 (6 words)

01A0 0600 ? 01A0 0617?Reload/link parameters for Event M (6 words)

01A0 0618 ? 01A0 062F?Reload/link parameters for Event N (6 words)

......

01A0 07E0 ? 01A0 07F7?Reload/link parameters for Event Z (6 words)

01A0 07F8 ? 01A0 07FF?Scratch pad area (2 words)

?The C6414/C6415/C6416 device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.

Table 9. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0200 0000QOPT QDMA options parameter register

0200 0004QSRC QDMA source address register

0200 0008QCNT QDMA frame count register

0200 000C QDST QDMA destination address register

0200 0010QIDX QDMA index register

0200 0014 ? 0200 001C Reserved

0200 0020QSOPT QDMA pseudo options register

0200 0024QSSRC QDMA pseudo source address register

0200 0028QSCNT QDMA pseudo frame count register

0200 002C QSDST QDMA pseudo destination address register

0200 0030QSIDX QDMA pseudo index register

SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005

peripheral register descriptions (continued)

Table 10. Interrupt Selector Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

019C 0000MUXH Interrupt multiplexer high Selects which interrupts drive CPU

interrupts 10?15 (INT10?INT15)

019C 0004MUXL Interrupt multiplexer low Selects which interrupts drive CPU

interrupts 4?9 (INT04?INT09)

019C 0008EXTPOL External interrupt polarity Sets the polarity of the external

interrupts (EXT_INT4?EXT_INT7)

019C 000C ? 019C 01FF?Reserved

Table 11. McBSP 0 Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

018C 0000DRR0McBSP0 data receive register via Configuration Bus The CPU and EDMA controller can only read this register; they cannot write to it.

0x3000 0000 ? 0x33FF FFFF DRR0McBSP0 data receive register via Peripheral Bus 018C 0004DXR0McBSP0 data transmit register via Configuration Bus 0x3000 0000 ? 0x33FF FFFF DXR0McBSP0 data transmit register via Peripheral Bus 018C 0008SPCR0McBSP0 serial port control register

018C 000C RCR0McBSP0 receive control register

018C 0010XCR0McBSP0 transmit control register

018C 0014SRGR0McBSP0 sample rate generator register

018C 0018MCR0McBSP0 multichannel control register

018C 001C RCERE00McBSP0 enhanced receive channel enable register 0 018C 0020XCERE00McBSP0 enhanced transmit channel enable register 0 018C 0024PCR0McBSP0 pin control register

018C 0028RCERE10McBSP0 enhanced receive channel enable register 1 018C 002C XCERE10McBSP0 enhanced transmit channel enable register 1 018C 0030RCERE20McBSP0 enhanced receive channel enable register 2 018C 0034XCERE20McBSP0 enhanced transmit channel enable register 2 018C 0038RCERE30McBSP0 enhanced receive channel enable register 3 018C 003C XCERE30McBSP0 enhanced transmit channel enable register 3 018C 0040 ? 018F FFFF–Reserved