ICS843004AGI-04LFT中文资料
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
G ENERAL D ESCRIPTION
The ICS843004I-04 is a 4 output LVPECL
Synthesizer optimized to generate clock frequencies for a variety of high performance
applications and is a member of the HiPerClocks TM family of high performance
clock solutions from ICS. This device can select its input reference clock from either a crystal input or a single-ended clock signal. It can be configured to generate 4outputs with individually selectable divide-by-one or divide-by-four function via the 4 frequency select pins (F _S E L [3:0]). T h e I C S 843004I -04 u s e s I C S ’ 3r d generation low phase noise VCO technology and can achieve 1ps or lower typical r ms phase jitter. This ensures that it will easily meet clocking requirements for SD H (STM-1/STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This device is suitable for multi-rate and multiple port line card applications. The ICS843004I-04is conveniently packaged in a small 24-pin TSSOP package.
F EATURES
?Four L VPECL outputs
?Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
?Supports the following applications: SONET/SDH, SA TA,or 10Gb Ethernet ?Output frequency range: 140MHz - 170MHz,560MHz - 680MHz ?VCO range: 560MHz - 680MHz
?Crystal oscillator and CLK range: 17.5MHz - 21.25MHz ?RMS phase jitter @ 622.08MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.82ps (typical)?RMS phase jitter @ 156.25MHz output, using a 19.53125MHz crystal (1.875MHz - 20MHz): 0.57ps (typical)?RMS phase jitter @ 155.52MHz output, using a 19.44MHz crystal (12kHz - 20MHz): 0.94ps (typical)?Full 3.3V supply mode
?-40°C to 85°C ambient operating temperature
?Available in both standard and lead-free RoHS compliant packages
P IN A SSIGNMENT
ICS843004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body G Package T op View
nQ1Q1V CC o Q0nQ0M R F_SEL3
nc V CCA F_SEL0
V CC F_SEL1
123456789101112nQ2Q2V CCO Q3nQ3V EE
F_SEL2INPUT_SEL CLK V EE
XTAL_IN XTAL_OUT
242322212019181716151413
B LOCK D IAGRAM
Q0nQ0
Q1nQ1
Q2nQ2
Q3nQ3
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
T ABLE 1. P IN D ESCRIPTIONS
T ABLE 2. P IN C HARACTERISTICS
l o b m y S r e t e m a r a P s
n o i t i d n o C t s e T m
u m i n i M l a c i p y T m
u m i x a M s t i n U C N
I e c n a t i c a p a C t u p n I 4F p R N W O D L L U P r o t s i s e R n w o d l l u P t u p n I 15k ΩR P
U L L U P r
o t s i s e R p u l l u P t u p n I 1
5k Ω
T ABLE 3. O UTPUT C ONFIGURATION AND F REQUENCY R ANGE F UNCTION T ABLE
s
t u p n I O C V )z H M (e
u l a V r e d i v i D )
z H M (y c n e u q e r F t u p t u O n o i t a c i l p p A x
L E S _F )
z H M (L A T X 3
Q n /3Q :0Q n /0Q 044.9180.2261÷80.226H
D S /T
E N O S 144.9180.2264÷25.551057.810061÷006A
T A S 157.810064÷051052135.915261÷526t e n r e h t E t i b a g i G 01152135.915264÷52.6510106141.022135.4461÷2135.446t e n r e h t E t i b a g i G 01C
E F B 46/B 661
1
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÷3
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p y T n
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E r e w o P .
s n i p y l p p u s e v i t a g e N 61K L C t u p n I n w o d l l u P .
t u p n i k c o l c L T T V L /S O M C V L 71L E S _T U P N I t u p n I n w o d l l u P .
e c r u o s e c n e r e
f e R L L P e h t e h t s a s t u p n i K L C r o l a t s y r c n e e w t e b s t c e l e S .
H G I H n e h w K L C s t c e l e S .W O L n e h w s t u p n i L A T X s t c e l e S .
s l e v e l e c a f r e t n i L T T V L /S O M C V L 12,023Q ,3Q n t u p t u O .
s l e v e l e c a f r e t n i L C E P V L .r i a p t u p t u o l a i t n e r e f f i D 4
2,322
Q n ,2Q t
u p t u O .
s l e v e l e c a f r e t n i L C E P V L .r i a p t u p t u o l a i t n e r e f f i D :E T O N p u l l u P d n a n w o d l l u P .
s e u l a v l a c i p y t r o f ,s c i t s i r e t c a r a h C n i P ,2e l b a T e e S .s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be-yond those listed in the DC Characteristics or AC Character-istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
T ABLE 4A. P OWER S UPPLY DC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, T A = -40°C TO 85°C
T ABLE 4B. LVCMOS / LVTTL DC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = -40°C TO 85°C
T ABLE 4C. LVPECL DC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = -40°C TO 85°C
l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l a c i p y T m u m i x a M s t i n U V C C e g a t l o V y l p p u S e r o C 531.33.3564.3V V A C C e g a t l o V y l p p u S g o l a n A 531.33.3564.3V V O C C e g a t l o V y l p p u S t u p t u O 5
31.33
.3564.3V I E E t n e r r u C y l p p u S r e w o P 021A m I A C C t n e r r u C y l p p u S g o l a n A 01A m I O
C C t
n e r r u C y l p p u S t u p t u O 0
21A
m l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l
a c i p y T m u m i x a M s t i n U V H I e g a t l o V h g i H t u p n I 2V C C 3
.0+V V L I e g a t l o V w o L t u p n I 3
.0-8.0V I H
I t
n e r r u C h g i H t u p n I ,
K L C L E S _T U P N I ,R M V C C V =N I 564.3=051A μ3
L E S _F :0L E S _F V C C V =N I 564.3=5
A μI L
I t
n e r r u C w o L t u p n I ,
K L C L E S _T U P N I ,R M V C C V ,V 564.3=N I V 0=5-A μ3
L E S _F :0L E S _F V C C V ,V 564.3=N I V
0=0
51-A
μA BSOLUTE M AXIMUM R A TINGS
Supply Voltage, V CC 4.6V
Inputs, V I
-0.5V to V CC + 0.5V Outputs, I O
Continuous Current 50mA Surge Current
100mA Package Thermal Impedance, θJA 70°C/W (0 mps)
Storage Temperature, T STG
-65°C to 150°C
l o b m y S r
e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l
a c i p y T m u m i x a M s t i n U V H O 1E T O N ;e g a t l o V h g i H t u p t u O V O C C 4.1-V O C C 9.0-V V L O 1E T O N ;e g a t l o V w o L t u p t u O V O C C 0.2-V O C C 7.1-V V G
N I W S g
n i w S e g a t l o V t u p t u O k a e P -o t -k a e P 6
.00
.1V
05h t i w d e t a n i m r e t s t u p t u O :1E T O N ΩV o t O C C .
V 2-
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
T ABLE 6. AC C HARACTERISTICS , V CC = V CCA = V CCO = 3.3V±5%, TA = -40°C TO 85°C
T ABLE 5. C RYSTAL C HARACTERISTICS
r e t e m a r a P s
n o i t i d n o C t s e T m u m i n i M l
a c i p y T m u m i x a M s t i n U n o i t a l l i c s O f o e d o M l
a t n e m a d n u F y
c n e u q e r F 5
.7152.12z H M )R S E (e c n a t s i s e R s e i r e S t n e l a v i u q E 05Ωe c n a t i c a p a C t n u h S 7F p l
e v e L e v i r D 1
W
m .
l a t s y r c t n a n o s e r l e l l a r a p F p 81n a g n i s u d e z i r e t c a r a h C :E T O N l o b m y S r e t e m a r a P s n o i t i d n o C t s e T m u m i n i M l
a c i p y T m u m i x a M s t i n U f T U O y
c n e u q e r F t u p t u O 1÷=r e
d i v i D t u p t u O 065086z H M 4
÷=r e d i v i D t u p t u O 0
41071z H M t )
o (k s 3
,2,1E T O N ;w e k S t u p t u O 5
7s p t )
?(t i j ;)m o d n a R (r e t t i J e s a h P S M R 4
E T O N ,
z H M 25.551z
H M 02-z H k 21:e g n a R n o i t a r g e t n I 49.0s p ,
z H M 52.651z
H M 02-z H M 578.1:e g n a R n o i t a r g e t n I 75.0s p ,
z H M 80.226z
H M 02-z H k 21:e g n a R n o i t a r g e t n I 2
8s p t R t /F e m i T l l a F /e s i R t u p t u O %
08o t %025
71576s p c
d o e
l c y C y t u D t u p t u O 4÷=r e d i v i D t u p t u O 8425%1÷=r e d i v i D t u p t u O 0
40
6%
.s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e D :1E T O N V t a d e r u s a e M O C C .
2/.
56d r a d n a t S C E D E J h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h T :2E T O N .n o i t a r u g i f n o c e d i v i d e m a s e h t n i s t u p t u o l l a h t i w n e k a t s t n e m e r u s a e m w e k s t u p t u O :3E T O N .
t o l P e s i o N e s a h P e h t o t r e f e r e s a e l P :4E T O N
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
P ARAMETER M EASUREMENT I NFORMATION
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
C RYSTAL I NPUT I NTERFACE
The ICS843004I-04 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 19.44MHz,
18pF parallel resonant crystal and were chosen to mini-mize the ppm error.
A PPLICATION I NFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843004I-04 pro-vides separate power supplies to isolate any high switch-ing noise from the outputs to the internal PLL. V CC , V CCA , and V DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance,power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA .
P OWER S UPPL Y F ILTERING T ECHNIQUES
F IGURE 1. P OWER S UPPLY F
ILTERING
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
LVCMOS TO XTAL I NTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
F IGURE 3.
G ENERAL D IAGRAM FOR LVCMOS D RIVER TO XTAL I NPUT I NTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition,matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First,R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω.
I NPUTS :C RYSTAL I NPUT :
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating.Though not required, but for additional protection, a 1k Ωresistor can be tied from XT AL_IN to ground.
CLK I NPUT :
For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from the CLK input to ground.
LVCMOS C ONTROL P INS :
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used.
R ECOMMENDATIONS FOR U NUSED I NPUT AND O UTPUT P INS O UTPUTS :
LVPECL O UTPUT
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
T ERMINATION FOR 3.3V LVPECL O UTPUT
The clock layout topology shown below is a typical ter-mination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. There-fore, terminating resistors (D C current path to ground)or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines.
F IGURE 4B. L VPECL O UTPUT T ERMINATION
F IGURE 4A. L VPECL O UTPUT T ERMINATION Matched impedance techniques should be used to maxi-mize operating frequency and minimize signal distor-tion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compat-ibility across all printed circuit and clock component pro-cess variations.
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
S CHEMATIC E XAMPLE
Figure 5 shows a schematic example for ICS843004I-04. In this example, the input is a 19.44MHz parallel resonant crystal with load capacitor CL=18pF . The 22pF frequency fine tuning capacitors are used C1 and C2. This example also shows general logic control input handling. For decoupling capacitors, it is
F IGURE 5. ICS844004I-04 S CHEMATIC E XAMPLE
recommended to have one decouple capacitor per power pin.Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R2, C3 and C4should also be located as close to the V CCA pin as possible.
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
T ABLE 7. T HERMAL R ESISTANCE θJA FOR 24-L EAD TSSOP , F ORCED C ONVECTION
P OWER C ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004I-04.Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004I-04 is the sum of the core power plus the power dissipated in the load(s).The following is the power dissipation for V CC = 3.3V + 5% = 3.465V , which gives worst case results.NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
?Power (core)MAX = V CC_MAX * I EE_MAX = 3.465V * 120mA = 415.8mW ?
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power _MAX (3.465V , with all outputs switching) = 415.8 + 120mW = 535.8mW
2. Junction T emperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)T A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used.
Assuming an air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7 below.Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.536W * 65°C/W = 119.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
θJA by Velocity (Meters per Second)
1
2.5
Multi-Layer PCB, JEDEC Standard T est Boards
70°C/W
65°C/W
62°C/W
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.LVPECL output driver circuit and termination are shown in the Figure 6.
T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V CC
- 2V .
?
For logic high, V OUT = V OH_MAX = V CC_MAX – 0.9V (V
CC_MAX
- V
OH_MAX
) = 0.9V
?
For logic low, V OUT = V
OL_MAX
= V
CC_MAX
– 1.7V
(V CC_MAX - V OL_MAX ) = 1.7V
Pd_H is power dissipation when the output drives high.Pd_L is the power dissipation when the output drives low.Pd_H = [(V
OH_MAX – (V
CC_MAX - 2V))/R L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC _MAX
- V
OH_MAX
))/R L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC _MAX
- V
OL_MAX
))/R L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
T otal Power Dissipation per output pair = Pd_H + Pd_L = 30mW
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
R ELIABILITY I NFORMATION
T RANSISTOR C OUNT
The transistor count for ICS843004I-04 is: 2273
T ABLE 8. θJA VS . A IR F LOW T ABLE FOR 24 L EAD TSSOP
θJA by Velocity (Meters per Second)
1
2.5
Multi-Layer PCB, JEDEC Standard T est Boards
70°C/W
65°C/W
62°C/W
Integrated
Circuit
Systems, Inc.
ICS843004I-04
F EMTO
C
LOCKS
?
C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
P ACKAGE O UTLINE - G S UFFIX FOR 24 L EAD TSSOP
T ABLE 9. P ACKAGE D IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O B M Y S s
r e t e m i l l i M m
u m i n i M m
u m i x a M N 4
2A --02.11A 50.051.02A 08.050.1b 91.003.0c 90.002.0D 0
7.709.7E C
I S A B 04.61E 0
3.40
5.4e C
I S A B 56.0L 54.057.0α°0°8a
a a --0
1.0
Integrated Circuit
Systems, Inc.
ICS843004I-04
F EMTO C LOCKS ? C RYSTAL /LVCMOS-TO -3.3V LVPECL F REQUENCY S YNTHESIZER
T ABLE 10. O RDERING I NFORMA TION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.The aforementioned trademarks, HiPerClockS and F EMTO C LOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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