74LVTH373MTC中文资料
? 1999 Fairchild Semiconductor Corporation DS012015
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September 1999Revised October 1999
74LVT373 ? 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVT373 ? 74LVTH373
Low Voltage Octal Transparent Latch with 3-STATE Outputs
General Description
The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications.The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state.The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These octal latches are designed for low-voltage (3.3V)V CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.Features
s Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373).s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink ?32 mA/+64 mA
s Functionally compatible with the 74 series 373
Ordering Code:
Logic Symbols
IEEE/IEC
Order Number Package Number
Package Description
74LVT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74LVT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT373MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74LVTH373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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74L V T 373 ? 74L V T H 373
Connection Diagram Pin Descriptions
Truth Table
H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial
O 0 = Previous O 0 before HIGH-to-LOW transition of Latch Enable
Functional Description
The LVT373 and LVTH373 contain eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the D n inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the informa-tion that was present on the D inputs a setup time preced-ing the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE)input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
D 0–D 7Data Inputs L
E Latch Enable Input OE Output Enable Input O 0–O 7
3-STATE Latch Outputs
Inputs
Outputs LE OE D n O n X H X Z H L L L H L H H L
L
X
O 0
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74LVT373 ? 74LVTH373
Absolute Maximum Ratings (Note 1)
Recommended Operating Conditions
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.Note 2: I O Absolute Maximum Rating must be observed.
Symbol Parameter
Value Conditions
Units V CC Supply Voltage ?0.5 to +4.6V V I DC Input Voltage ?0.5 to +7.0V V O DC Output Voltage ?0.5 to +7.0Output in 3-STATE
V ?0.5 to +7.0
Output in HIGH or LOW State (Note 2)V I IK DC Input Diode Current ?50V I < GND mA I OK DC Output Diode Current ?50V O < GND
mA I O DC Output Current
64V O > V CC Output at HIGH State mA 128V O > V CC Output at LOW State
I CC DC Supply Current per Supply Pin ±64mA I GND DC Ground Current per Ground Pin ±128mA T STG
Storage Temperature
?65 to +150
°C
Symbol Parameter
Min Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage
5.5V I OH HIGH Level Output Current ?32mA I OL LOW Level Output Current 64mA T A Free-Air Operating Temperature
?4085°C ?t/?V
Input Edge Rate, V IN = 0.8V–2.0V, V CC = 3.0V
10
ns/V
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74L V T 373 ? 74L V T H 373
DC Electrical Characteristics
Note 3: All typical values are at V CC = 3.3V, T A = 25°C.Note 4: Applies to Bushold versions only (74LVTH373).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.
Dynamic Switching Characteristics (Note 8)
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n ?1 data inputs are driven 0V to 3V. Output under test held LOW.
Symbol Parameter
V CC (V)T A = ?40°C to +85°C Units
Conditions
Min
Typ Max
(Note 3)
V IK Input Clamp Diode Voltage 2.7?1.2
V I I = ?18 mA V IH Input HIGH Voltage 2.7–3.6 2.0
V V O ≤ 0.1V or V IL Input LOW Voltage 2.7–3.60.8
V O ≥ V CC ? 0.1V V OH
Output HIGH Voltage
2.7–
3.6V CC ? 0.2V I OH = ?100 μA 2.7 2.4V I OH = ?8 mA 3.0
2.0
V I OH = ?32 mA V OL
Output LOW Voltage
2.70.2V I OL = 100 μA 2.70.5V I OL = 24 mA
3.00.4V I OL = 16 mA 3.00.5V I OL = 32 mA 3.0
0.55
V I OL = 64 mA I I(HOLD)Bushold Input Minimum Drive 3.075μA V I = 0.8V (Note 4)?75μA V I = 2.0V I I(OD)Bushold Input Over-Drive Current to Change State 3.0500μA (Note 5)(Note 4)?500
μA (Note 6)I I
Input Current
3.610μA V I = 5.5V Control Pins 3.6±1μA V I = 0V or V CC Data Pins
3.6?5μA V I = 0V 1μA V I = V CC
I OFF Power Off Leakage Current 0±100μA 0V ≤ V I or V O ≤ 5.5V I PU/PD Power up/down 3-STATE 0–1.5V ±100μA V O = 0.5V to 3.0V Output Current
V I = GND or V CC I OZL 3-STATE Output Leakage Current 3.6?5μA V O = 0.5V I OZH 3-STATE Output Leakage Current 3.65μA V O = 3.0V I OZH +3-STATE Output Leakage Current 3.610μA V CC < V O ≤ 5.5V I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ +Power Supply Current
3.60.19mA V CC ≤ V O ≤ 5.5V,Outputs Disabled ?I CC
Increase in Power Supply Current 3.6
0.2
mA
One Input at V CC ? 0.6V (Note 7)
Other Inputs at V CC or GND
Symbol Parameter
V CC (V)T A = 25°C
Units Conditions C L = 50 pF R L = 500?Min
Typ Max
V OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 9)V OLV
Quiet Output Minimum Dynamic V OL
3.3
?0.8
V
(Note 9)
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74LVT373 ? 74LVTH373
AC Electrical Characteristics
Note 10: All typical values are at V CC = 3.3V, T A = 25°C.
Capacitance (Note 11)
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T A = ?40°C to +85°C Units
C L = 50 pF, R L = 500?
V CC = 3.3V ±0.3V
V CC = 2.7V
Min
Typ (Note 10)
Max Min Max t PHL Propagation Delay 1.5 4.5 1.5 5.0ns t PLH D n to O n
1.5 4.5 1.5 4.9t PHL Propagation Delay 1.7 4.6 1.7 4.9ns t PLH LE to O n
1.7 4.5 1.7 5.0t PZL Output Enable Time
1.3 4.8 1.3 5.9ns t PZH 1.3 4.8 1.3 5.5t PLZ Output Disable Time 1.9 4.6 1.9 4.9ns t PHZ 1.9 4.6
1.9 4.9
t W LE Pulse Width 3.0 3.0ns t S Setup Time, D n to LE 1.1 1.0ns t H
Hold Time, D n to LE 1.4
1.4
ns Symbol Parameter
Conditions
Typical Units C IN Input Capacitance V CC = OPEN, V I = 0V or V CC 3pF C OUT
Output Capacitance
V CC = 3.0V, V O = 0V or V CC
5
pF
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74L V T 373 ? 74L V T H 373
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74LVT373 ? 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.
2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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