Rev.0.9.0 2006.10.12
YDA148(D-510) 5W-15W Digital Audio Power Amplifier
Evaluation Board EVB-D510-Q-10Z3
Operation Manual
○Overview
“EVB-D510-Q-10Z3” is an evaluation board to evaluate audio characteristics of YDA148(D-510), a digital audio power amplifier IC with maximum output power of 15W (V DDP =15V ,R L =8?) × 2ch. All-in-one board with stereo mini-jack, volumes, and control switches as well as space-saving parts including YDA148 allows easy evaluation.
○Features
?Maximum output
15 W×2ch (V DDP =15V , R L =8?, THD+N=10%) 10 W×2ch (V DDP =12V , R L =8?, THD+N=10%) ?Efficiency
86 % (V DDP =12V , R L =8?) ?Distortion Rate (THD+N)
0.03 % (V DDP =12V , R L =8?, Po=5W, 1kHz) ?S/N Ratio
105dB (V DDP =12V , GAIN[1:0]=L,L NCDRC[1:0]=L,L) ?Non-Clip function /DRC function ?Power-limit function
?Gain setting function (4 step)
?Sleep control function, Output mute control function
?Over-current Protection Function, Over-temperature Protection Function, Low voltage Malfunction Prevention function, and DC detection function
○External View of the Evaluation Board
? This evaluation board and attached documents (including Circuit Diagram and Layout Pattern Diagram) are provided not for guaranteeing your product’s performance and quality based on them but for advancing product development smoothly.
? This evaluation board and attached documents (including Schematic Diagram and Layout Pattern Diagram) are subject to change for their improvement etc. without prior notice.
? Brand names and product names in this document are trademarks or registered trademarks of their respective companies.
○Overview of the Evaluation Board
Table-1
Element Function
Description
Default setting VR1 Stereo volume
Volume for sound level
Max VR2 Power-limit control volume Volume for power-limit control
Max U1 Stereo mini-jack Audio signal input terminal (Stereo-mini) D1
LED
At normal operation: Lighting At PROTN=L: Lights out
CB1 Power supply terminal Use 15V power supply CB2 L-ch Speaker terminal CB3 R-ch Speaker terminal H1 CKOUT output terminal Slave clock output terminal open H2 CKIN input terminal External clock input terminal open H3 GND for CKOUT output terminal open H4 GND for CKIN input terminal open SW1 CK mode and gain setting DIP switch CKIN :On :EMI reduction mode,
Off :Normal mode
GAIN1:On :Gain1=H, Off :Gain1=L GAIN0:On :Gain0=H, Off :Gain0=L NoUse :No use
Off Off Off - SW2 SLEEPN terminal control switch Open :Normal operation, Push :Sleep mode Open SW3 MUTEN terminal control switch Open :Normal operation, Push :Mute mode Open SW4 NCDRC0 setting switch Refer to Table-3 Off SW5 NCDRC1 setting switch Refer to Table-3 Off JP1 Master/Slave setting jumper Short :Master mode, Open :Slave mode Short R07 Input resistor (INRP) (Bottom side)0?:Single input, Open :Differential input 0? R08 Input resistor (INRM) 5.1k ?:Single input, Open :Differential input 5.1k ?R09 Input resistor (INLM) 5.1k ?:Single input, Open :Differential input 5.1k ?R10 Input resistor (INLP) 0?:Single input, Open :Differential input 0? R28 Automatically returned setting element 0?:Automatically returned
Open :Manual returned
0?
The following equipments are required to evaluate YDA148(D-510) using this evaluation board.
?Power Supply
Use a power supply that can supply 2.5A or more at 12V or 15V.
?Audio Equipment
Prepare audio equipment with line-out output such as CD player. And, use audio cable with one stereo mini-plug.
?Speaker
Use a speaker with an impedance of 8?.
○Setting and Connection of Evaluation Board
We describes about setting method for each section of this evaluation board and connection for power supply, audio equipment, and speakers.
①Audio signal input
Connect the line output of audio equipment such as CD player to analog signal input jack [1] on the evaluation board. In the initial state, the input sensitivity is set to 1.0Vrms.
In this state, when volume [VR1] is maximized, the maximum output is obtained in the 1.0Vrms signal input.
When the input sensitivity in the environment used is different from the above-mentioned, the input sensitivity is set with GAIN0 and GAIN1 terminal of SW1.This evaluation board is set to Single input.
When use by the difference input, the input resistor of R07, R08, R09, and R10 are removed, and the signal is input directly to the land of the board.
R07:INRP (Bottom side), R08: INRM, R09: INLM, R10: INLP
R07
R09R 08
R 10
Top layer side
Bottom layer side
Fig-2
②Connection of Power Supply
Connect a power supply with the attached power cable to [CB1] connector. Red cable: Connect to power supply. Black cable: Connect to GND.
③Connection of Speaker Cables
Connect a speaker using the attached speaker cables. Connect the L-ch speaker cable to [CB2] connector. Connect the R-ch speaker cable to [CB3] connector.
(You don't have to pay attention to their miss wiring because cables based on the common specification to the power cable are used.)
Lch: Blue cable: connect to “+” terminal of a speaker.
White cable: connect to “-”terminal of a speaker. Rch: Red cable: connect to “+” terminal of a speaker.
White cable: connect to “-” terminal of a speaker.
The speaker output configures BTL. Be careful not to connect one end to the Ground side during the evaluation.
④Volume Control
Dual-ganged volume [VR1] can control the volume. Rotating it clockwise turns up the volume.
⑤Sleep Control Switch
The state of the SLEEPN terminal is controlled with [SW2]. It enters the sleep state while the switch is being pushed.
⑥Mute Control Switch
The state of the MUTEN terminal is controlled with [SW3]. It enters the mute state while the switch is being pushed.
⑦Automatically returned setting
This evaluation board is initial set to an automatically returned. To release an automatically returned, resistor [R28] is removed.
Fig-3
⑧Gain Setting Switch
The GAIN1 and GAIN0 termianl are set by GAIN1 and GAIN0 of [SW1] dip switch.
GAIN1 GAIN0Digital amplifier gain setting
H H 16dB
L L 22dB
L H 28dB
H L 34dB
Table-2
⑨Operation Mode Setting Switch
The NCDRC1 and NCDRC0 terminal are set by [SW4] and [SW5].
NCDRC1 and NCDRC0 terminal change the setting in the state of SLEEPN=L or Power supply is OFF.
NCDRC1 NCDRC0 Operation mode
OFF
L L Mode
mode
L H Nonclip
H L DRC1
mode
mode
H H DRC2
Table-3
⑩Power Limit Level Setting (Option)
Power limit level is controlled by [VR2].
If [VR2] is turned to the maximum in the right side, it enters the state that the power limit doesn't work because A VSS is input to the PLIMIT terminal.
When [VR2] is turned to the left side, the PLIMIT terminal voltage rises and the level that the power limit works can be set.
?Protection Function Setting
YDA148 has Over-current Protection function for speaker output terminals, IC Thermal Protection function, and DC Detection function. When these unusual states are detected, YDA148 outputs "L" to the PROTN terminal, and protects IC by compulsory output mute at the same time. The LED [D1] doesn't light while the PROTN terminal is output L. In the automatically returned setting, LED turn on and off.
?Multi channel setting
One board is set to the mastering mode (JP1 is short). Other boards are set to the slave mode (JP1 is opened). CKOUT [H1] and CKIN [H2] of master board and slave board are connected as shown in the figure below.
As a result, all YDA148 operates synchronously, and it can be operated as a high-quality multi channel
Reference Constant Tolerance
Part No.
Type
Manufacture
VR1 10k ? RK09712200HA Volume ALPS ELECTRIC
SW2 CHS-04B DIP switch COPAL ELECTRONICS VR2 100k ?
ST-4EB
Volume
COPAL ELECTRONICS
D11,D12 3.3V MAZ8033 Zener diode PANA D01 HLMP1790 GREEN
LED Agilent Tech.
T1 2SC3906K Transistor ROHM U1 YDA148 Class-D Amplifier Yamaha OUTL,OUTR,POWER B2P-VH Connector JST U2
LGY6502-0900
Stereo mini jack
SMK
U3 HD74HC14(TELL) Schmitt inverter Renesas SW4,SW5 FT1E-2M Toggle switch Fujisoku SW2,SW3
SKQMBB Tactile switch ALPS ELECTRIC JP01 Jumper R1,R2,R3 300k ? Chip resistor R4,R5,R6 10k ? Chip resistor R8,R9 5.1k ?±5% Chip resistor
R7,R10,R12,R28,R29,R 31
0?
Chip resistor
R13,R14 56K ? Chip resistor R19,R20,R21,R22,R26,R27, R15,R16,R11
100K ?
Chip resistor
R23,R30 470K ? Chip resistor R25 1.2k ? Chip resistor
0? Chip resistor C1,C2,C3,C17,C25,C26, C27,C28,C29,C30
100pF
Chip capacitor
C4,C5 220pF Chip capacitor C6,C7,C8,C9,C11,C12, C13,C14,C15
1uF
C1608X5R1A105K Chip capacitor TDK
C10,C16,C18,C31,C32 0.1uF
Chip capacitor
C33 220uF 35V UVK1V221MPD Electrolytic capacitor Nichicon
TP1,TP2,TP8
Test pin Mac-Eight
○Circuit Diagram
○Layout Pattern Diagram
1/4
2/4
3/4 4/4
○Revision History
Version Data Description Rev.0.9.0 2006.10.12 Newly created preliminary version